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ericw |
/*
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--------------------------------------------------------------------------------
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Module : boot_code.h
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--------------------------------------------------------------------------------
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Function:
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- Boot code for a processor core.
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Instantiates:
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- Nothing.
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Notes:
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- For testing (@ core.v):
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CLR_BASE = 'h0;
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CLR_SPAN = 2; // gives 4 instructions
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INTR_BASE = 'h20; // 'd32
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INTR_SPAN = 2; // gives 4 instructions
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--------------------------------------------------------------------------------
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*/
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/*
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--------------------
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-- external stuff --
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--------------------
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*/
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`include "op_encode.h"
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`include "reg_set_addr.h"
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`include "boot_code_defs.h"
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/*
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----------------------------------------
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-- initialize: fill with default data --
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----------------------------------------
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*/
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integer i;
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initial begin
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/* // fill with nop (some compilers need this)
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for ( i = 0; i < CAPACITY; i = i+1 ) begin
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ram[i] = { `nop, `__, `__ };
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end
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*/
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/*
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---------------
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-- boot code --
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---------------
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*/
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// Thread 0 : enable interrupts
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// All threads : output thread ID @ interrupt
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///////////////
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// clr space //
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///////////////
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// thread 0 : enable interrupts & loop forever
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i='h0; ram[i] = { `lit_u, `__, `s3 }; // s3='h0100
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i=i+1; ram[i] = 16'h0100 ; //
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i=i+1; ram[i] = { `gsb, `P3, `s3 }; // gsb, pop s3
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i=i+1; ram[i] = { `jmp_ie, -4'd1, `s0, `s0 }; // loop forever
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// all others : loop forever
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i='h04; ram[i] = { `jmp_ie, -4'd1, `s0, `s0 }; // loop forever
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i='h08; ram[i] = { `jmp_ie, -4'd1, `s0, `s0 }; // loop forever
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i='h0c; ram[i] = { `jmp_ie, -4'd1, `s0, `s0 }; // loop forever
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i='h10; ram[i] = { `jmp_ie, -4'd1, `s0, `s0 }; // loop forever
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i='h14; ram[i] = { `jmp_ie, -4'd1, `s0, `s0 }; // loop forever
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i='h18; ram[i] = { `jmp_ie, -4'd1, `s0, `s0 }; // loop forever
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i='h1c; ram[i] = { `jmp_ie, -4'd1, `s0, `s0 }; // loop forever
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////////////////
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// intr space //
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////////////////
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// all threads : read and output thread ID
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i='h20; ram[i] = { `lit_u, `__, `s3 }; // s3='h0110
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i=i+1; ram[i] = 16'h0110 ; //
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i=i+1; ram[i] = { `gsb, `P3, `s3 }; // gsb, pop s3 (addr)
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i=i+1; ram[i] = { `gto, `P0, `__ }; // return, pop s0
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//
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i='h24; ram[i] = { `lit_u, `__, `s3 }; // s3='h0110
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i=i+1; ram[i] = 16'h0110 ; //
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i=i+1; ram[i] = { `gsb, `P3, `s3 }; // gsb, pop s3 (addr)
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i=i+1; ram[i] = { `gto, `P0, `__ }; // return, pop s0
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//
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i='h28; ram[i] = { `lit_u, `__, `s3 }; // s3='h0110
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i=i+1; ram[i] = 16'h0110 ; //
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i=i+1; ram[i] = { `gsb, `P3, `s3 }; // gsb, pop s3 (addr)
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i=i+1; ram[i] = { `gto, `P0, `__ }; // return, pop s0
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//
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i='h2c; ram[i] = { `lit_u, `__, `s3 }; // s3='h0110
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i=i+1; ram[i] = 16'h0110 ; //
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i=i+1; ram[i] = { `gsb, `P3, `s3 }; // gsb, pop s3 (addr)
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i=i+1; ram[i] = { `gto, `P0, `__ }; // return, pop s0
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//
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i='h30; ram[i] = { `lit_u, `__, `s3 }; // s3='h0110
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i=i+1; ram[i] = 16'h0110 ; //
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i=i+1; ram[i] = { `gsb, `P3, `s3 }; // gsb, pop s3 (addr)
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i=i+1; ram[i] = { `gto, `P0, `__ }; // return, pop s0
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//
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i='h34; ram[i] = { `lit_u, `__, `s3 }; // s3='h0110
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i=i+1; ram[i] = 16'h0110 ; //
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i=i+1; ram[i] = { `gsb, `P3, `s3 }; // gsb, pop s3 (addr)
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i=i+1; ram[i] = { `gto, `P0, `__ }; // return, pop s0
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//
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i='h38; ram[i] = { `lit_u, `__, `s3 }; // s3='h0110
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i=i+1; ram[i] = 16'h0110 ; //
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i=i+1; ram[i] = { `gsb, `P3, `s3 }; // gsb, pop s3 (addr)
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i=i+1; ram[i] = { `gto, `P0, `__ }; // return, pop s0
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//
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i='h3c; ram[i] = { `lit_u, `__, `s3 }; // s3='h0110
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i=i+1; ram[i] = 16'h0110 ; //
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i=i+1; ram[i] = { `gsb, `P3, `s3 }; // gsb, pop s3 (addr)
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i=i+1; ram[i] = { `gto, `P0, `__ }; // return, pop s0
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///////////////////////
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// code & data space //
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///////////////////////
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/////////////////
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// subroutines //
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/////////////////
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// sub : enable all ints, return to (s3)
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i='h100; ram[i] = { `dat_is, `INTR_EN, `s1 }; // s1=reg addr
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i=i+1; ram[i] = { `dat_is, -6'd1, `s0 }; // s0=-1
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i=i+1; ram[i] = { `reg_w, `P1, `P0 }; // (s1)=s0, pop both
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i=i+1; ram[i] = { `gto, `P3, `__ }; // return, pop s3
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// sub : read thread ID & write to GPIO, return to (s3)
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i='h110; ram[i] = { `dat_is, `THRD_ID, `s1 }; // s1=reg addr
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i=i+1; ram[i] = { `reg_rs, `P1, `s0 }; // s0=(s1), pop s1
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i=i+1; ram[i] = { `dat_is, `IO_LO, `s1 }; // s1=reg addr
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i=i+1; ram[i] = { `reg_w, `P1, `P0 }; // (s1)=s0, pop both
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i=i+1; ram[i] = { `gto, `P3, `__ }; // return, pop s3
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end
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