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ericw |
/*
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--------------------------------------------------------------------------------
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Module : hive_core.v
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--------------------------------------------------------------------------------
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Function:
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- General purpose barrel processor FPGA core with:
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- 8 threads & 8 stage pipeline
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- 8 simple stacks per thread
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- 32 bit data
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- 16 bit opcode
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- 16 bit address
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Instantiates (at this level):
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- control_ring.v
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- data_ring.v
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- reg_set.v
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- reg_mem_shim.v
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- dp_ram_infer.v
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--------------------
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- Revision History -
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--------------------
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v04.05 - 2014-01-02
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- Note main version jump.
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- Branched design back into main line.
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- OP_CODE_W is now MEM_DATA_W.
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v01.04 - 2014-01-01
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- Moved register set and main memory data port one pipeline stage later.
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- op_pow is back and is now sign neutral.
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- Op renaming: psh_iu => psu_i.
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- `_0, `_1, etc. is now `s* in all boot code.
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- Added header blocking statements to some *.h files (didn't work for all).
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- Use of real rather than integer types in UART calculations for clarity.
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- EP3C5E144C: 2662 LEs, 198MHz (w/o DSE, synthesis optimized for speed).
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- Passes all boot code verification & functional tests.
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v01.03 - 2013-12-23
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- Short 4 bit (+7/-8) immediate (A?B) jumps have replaced all following jumps.
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- Removed unconditional immediate jump (use op_jmp_ie).
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- Immediate (A?0) jumps, data, and add IM value reduced to 6 bits.
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- Removed op_pow_i, op_shl_iu is op_psh_iu: combo pow2 and right shift,
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op_shl_u is strictly unsigned shift.
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- UART added to register set.
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- Op renaming:
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dat_f* => lit_*
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shl_iu => psh_iu
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- Small changes to register set base component parameters & I/O.
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- Opcode encode/decode now over full opcode width.
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- EP3C5E144C: 2650 LEs, 189MHz (w/o DSE).
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- Passes all boot code verification & functional tests.
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v01.02 - 2013-12-06
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- Following jumps (jmp_f) have replaced all skips.
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- Added op_pow & op_pow_i opcodes.
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- A odd testing removed (lack of opcode space).
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- op_pop now covers all stacks at once via {pb, sb, pa, sa} binary field.
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- op_reg_r now signed, added read and write high register ops (_wh is ~free).
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- Added op_lit_u to accomodate 16 bit addresses & such.
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- Op renaming:
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lit => dat_f
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byt => dat_i
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*_sx => *_xs
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*_ux => *_xu
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- Moved PC interrupt & jmp_f address loads to stage 4 of PC pipe.
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- op_dat_fh now uses A as source of low data rather than B,
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which is more consistent and allows unrelated pop.
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- Register set addresses now defined as 8 bits wide.
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- EP3C5E144C: ~2500 LEs, 185MHz (w/o DSE).
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- Passes all boot code verification tests.
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- Passes boot code functional tests: divide, sqrt, log2, exp2.
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v01.01 - 2013-11-19
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- Born. Based on Hive v3.10. Has 8 stacks per thread.
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- Skips are back for A odd and (A?B) testing.
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- Removed op_cls as it seems too dangerous. May put back in register set.
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- Lots of op renaming:
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dat_f => lit
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dat_i => byt
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or_br => bro, etc.
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or => orr
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pc => pgc (to make all op bases 3 letters)
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- Reg access now unsigned low with no immediate offset.
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- Added register to flag decode output, moved all PC changes to stage 3.
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- EP3C5E144C: ~2400 LEs, 178MHz (w/o DSE).
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- BROKEN: reg_mem_shim.v has bad decoding for dmem addr.
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--------------------------------------------------------------------------------
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*/
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module hive_core
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#(
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parameter integer CLK_HZ = 160000000, // master clk_i rate (Hz)
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parameter integer DATA_W = 32, // data width
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parameter integer THREADS = 8, // threads (don't change!)
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parameter [DATA_W/4-1:0] VER_MAJ = 'h04, // core version
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parameter [DATA_W/4-1:0] VER_MIN = 'h05 // core version
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)
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(
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// clocks & resets
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input wire clk_i, // clock
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input wire rst_i, // async. reset, active high
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//
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input wire [THREADS-1:0] intr_req_i, // event request, active high
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//
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input wire [DATA_W-1:0] io_i, // gpio
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output wire [DATA_W-1:0] io_o,
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//
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input wire uart_rx_i, // serial data
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output wire uart_tx_o // serial data
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);
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/*
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----------------------
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-- internal signals --
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----------------------
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*/
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`include "functions.h" // for clog2()
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//
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localparam integer ADDR_W = DATA_W/2; // address width
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localparam integer PNTR_W = 5; // stack pointer width
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localparam integer MEM_ADDR_W = 13; // main memory address width
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localparam integer MEM_DATA_W = DATA_W/2; // main memory data width
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localparam [ADDR_W-1:0] CLR_BASE = 'h0; // clear address base (concat)
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localparam integer CLR_SPAN = 2; // clear address span (2^n)
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localparam [ADDR_W-1:0] INTR_BASE = 'h20; // interrupt address base (concat)
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localparam integer INTR_SPAN = 2; // interrupt address span (2^n)
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localparam integer THRD_W = clog2( THREADS );
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localparam integer STACKS = 8; // number of stacks
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localparam integer STK_W = clog2( STACKS );
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localparam integer IM_W = 6; // immediate width
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localparam integer LG_SEL_W = 4;
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localparam integer REG_ADDR_W = 4;
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localparam integer DM_OFFS_W = 4;
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localparam integer PROT_POP = 1; // 1=error protection, 0=none
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localparam integer PROT_PUSH = 1; // 1=error protection, 0=none
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localparam integer UART_DATA_W = 8; // uart data width (bits)
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localparam integer UART_BAUD_RATE = 115200; // uart baud rate (Hz)
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//
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wire [THREADS-1:0] clr_req;
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wire [THREADS-1:0] intr_en;
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wire [MEM_DATA_W-1:0] op_code;
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wire op_code_er;
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wire [STK_W-1:0] data_sel_a, data_sel_b, addr_sel_b;
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wire imda;
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wire imad;
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wire sgn, ext, hgh;
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wire lg;
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wire [LG_SEL_W-1:0] lg_sel;
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wire add, sub, mul, shl, pow, rtn;
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wire stk_clr;
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wire [STACKS-1:0] pop, push, pop_er_2, push_er_3;
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wire [DATA_W-1:0] a_data;
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wire [ADDR_W-1:0] b_addr;
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wire [IM_W-1:0] im;
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wire flg_od_2, flg_nz_2, flg_lz_2, flg_ne_2, flg_lt_2;
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wire [THRD_W-1:0] thrd_0, thrd_2, thrd_3, thrd_6;
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wire [ADDR_W-1:0] pc_1, pc_3, pc_4;
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wire [MEM_DATA_W-1:0] dm_rd_data_4, rg_rd_data_4;
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wire [MEM_DATA_W-1:0] wr_data_2;
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wire [ADDR_W-1:0] dm_addr_2, rg_addr_2;
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wire dm_rd, dm_wr, rg_rd, rg_wr;
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wire dm_wr_2, rg_rd_2, rg_wr_2;
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wire lit;
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/*
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================
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== code start ==
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================
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*/
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// the control ring
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control_ring
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#(
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.DATA_W ( DATA_W ),
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.ADDR_W ( ADDR_W ),
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.THREADS ( THREADS ),
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.THRD_W ( THRD_W ),
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.STACKS ( STACKS ),
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.STK_W ( STK_W ),
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.IM_W ( IM_W ),
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.MEM_DATA_W ( MEM_DATA_W ),
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.LG_SEL_W ( LG_SEL_W ),
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.CLR_BASE ( CLR_BASE ),
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.CLR_SPAN ( CLR_SPAN ),
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.INTR_BASE ( INTR_BASE ),
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.INTR_SPAN ( INTR_SPAN )
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)
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control_ring
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(
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.clk_i ( clk_i ),
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.rst_i ( rst_i ),
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.clr_req_i ( clr_req ),
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.clr_ack_o ( ), // unused
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.intr_en_i ( intr_en ),
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.intr_req_i ( intr_req_i ),
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.intr_ack_o ( ), // unused
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.op_code_i ( op_code ),
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.op_code_er_o ( op_code_er ),
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.b_addr_i ( b_addr ),
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.im_o ( im ),
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.data_sel_a_o ( data_sel_a ),
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.data_sel_b_o ( data_sel_b ),
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.addr_sel_b_o ( addr_sel_b ),
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.imda_o ( imda ),
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.imad_o ( imad ),
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.sgn_o ( sgn ),
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.hgh_o ( hgh ),
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.ext_o ( ext ),
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.lg_sel_o ( lg_sel ),
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.add_o ( add ),
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.sub_o ( sub ),
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.mul_o ( mul ),
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.shl_o ( shl ),
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.pow_o ( pow ),
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.rtn_o ( rtn ),
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.lit_o ( lit ),
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.dm_rd_o ( dm_rd ),
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.dm_wr_o ( dm_wr ),
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.rg_rd_o ( rg_rd ),
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.rg_wr_o ( rg_wr ),
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.stk_clr_o ( stk_clr ),
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.pop_o ( pop ),
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.push_o ( push ),
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.flg_nz_2_i ( flg_nz_2 ),
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.flg_lz_2_i ( flg_lz_2 ),
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.flg_ne_2_i ( flg_ne_2 ),
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.flg_lt_2_i ( flg_lt_2 ),
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.thrd_0_o ( thrd_0 ),
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.thrd_2_o ( thrd_2 ),
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.thrd_3_o ( thrd_3 ),
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.thrd_6_o ( thrd_6 ),
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.pc_1_o ( pc_1 ),
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.pc_3_o ( pc_3 ),
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.pc_4_o ( pc_4 )
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);
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// the data ring
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data_ring
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#(
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.DATA_W ( DATA_W ),
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.ADDR_W ( ADDR_W ),
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.THREADS ( THREADS ),
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.THRD_W ( THRD_W ),
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.STACKS ( STACKS ),
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.STK_W ( STK_W ),
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.PNTR_W ( PNTR_W ),
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.IM_W ( IM_W ),
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.LG_SEL_W ( LG_SEL_W ),
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.PROT_POP ( PROT_POP ),
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.PROT_PUSH ( PROT_PUSH )
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)
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data_ring
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(
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.clk_i ( clk_i ),
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.rst_i ( rst_i ),
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.data_sel_a_i ( data_sel_a ),
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.data_sel_b_i ( data_sel_b ),
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.addr_sel_b_i ( addr_sel_b ),
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.imda_i ( imda ),
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.imad_i ( imad ),
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.sgn_i ( sgn ),
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.ext_i ( ext ),
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.hgh_i ( hgh ),
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.lg_sel_i ( lg_sel ),
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.add_i ( add ),
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.sub_i ( sub ),
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.mul_i ( mul ),
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.shl_i ( shl ),
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.pow_i ( pow ),
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.rtn_i ( rtn ),
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.dm_rd_i ( dm_rd ),
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.rg_rd_i ( rg_rd ),
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.stk_clr_i ( stk_clr ),
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.pop_i ( pop ),
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.push_i ( push ),
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.thrd_6_i ( thrd_6 ),
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.im_i ( im ),
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.dm_rd_data_4_i ( dm_rd_data_4 ),
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.rg_rd_data_4_i ( rg_rd_data_4 ),
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.pc_3_i ( pc_3 ),
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.a_data_o ( a_data ),
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.b_addr_o ( b_addr ),
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.flg_nz_2_o ( flg_nz_2 ),
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.flg_lz_2_o ( flg_lz_2 ),
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.flg_ne_2_o ( flg_ne_2 ),
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.flg_lt_2_o ( flg_lt_2 ),
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.pop_er_2_o ( pop_er_2 ),
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.push_er_3_o ( push_er_3 )
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);
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// shim for memory and register set access
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reg_mem_shim
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#(
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.DATA_W ( DATA_W ),
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.ADDR_W ( ADDR_W ),
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.IM_W ( DM_OFFS_W )
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)
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reg_mem_shim
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(
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.clk_i ( clk_i ),
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.rst_i ( rst_i ),
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.hgh_i ( hgh ),
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.lit_i ( lit ),
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| 314 |
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.dm_wr_i ( dm_wr ),
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|
.rg_rd_i ( rg_rd ),
|
| 316 |
|
|
.rg_wr_i ( rg_wr ),
|
| 317 |
|
|
.dm_wr_o ( dm_wr_2 ),
|
| 318 |
|
|
.rg_rd_o ( rg_rd_2 ),
|
| 319 |
|
|
.rg_wr_o ( rg_wr_2 ),
|
| 320 |
|
|
.a_data_i ( a_data ),
|
| 321 |
|
|
.wr_data_o ( wr_data_2 ),
|
| 322 |
|
|
.b_addr_i ( b_addr ),
|
| 323 |
|
|
.im_i ( im[DM_OFFS_W-1:0] ),
|
| 324 |
|
|
.pc_1_i ( pc_1 ),
|
| 325 |
|
|
.rg_addr_o ( rg_addr_2 ),
|
| 326 |
|
|
.dm_addr_o ( dm_addr_2 )
|
| 327 |
|
|
);
|
| 328 |
|
|
|
| 329 |
|
|
|
| 330 |
|
|
// internal register set
|
| 331 |
|
|
reg_set
|
| 332 |
|
|
#(
|
| 333 |
|
|
.REGS_IN ( 1 ),
|
| 334 |
|
|
.REGS_OUT ( 1 ),
|
| 335 |
|
|
.DATA_W ( DATA_W/2 ),
|
| 336 |
|
|
.ADDR_W ( REG_ADDR_W ),
|
| 337 |
|
|
.THREADS ( THREADS ),
|
| 338 |
|
|
.THRD_W ( THRD_W ),
|
| 339 |
|
|
.STACKS ( STACKS ),
|
| 340 |
|
|
.STK_W ( STK_W ),
|
| 341 |
|
|
.VER_MAJ ( VER_MAJ ),
|
| 342 |
|
|
.VER_MIN ( VER_MIN ),
|
| 343 |
|
|
.UART_DATA_W ( UART_DATA_W ),
|
| 344 |
|
|
.CLK_HZ ( CLK_HZ ),
|
| 345 |
|
|
.UART_BAUD_RATE ( UART_BAUD_RATE )
|
| 346 |
|
|
)
|
| 347 |
|
|
reg_set
|
| 348 |
|
|
(
|
| 349 |
|
|
.clk_i ( clk_i ),
|
| 350 |
|
|
.rst_i ( rst_i ),
|
| 351 |
|
|
.addr_i ( rg_addr_2[REG_ADDR_W-1:0] ),
|
| 352 |
|
|
.wr_i ( rg_wr_2 ),
|
| 353 |
|
|
.rd_i ( rg_rd_2 ),
|
| 354 |
|
|
.data_i ( wr_data_2 ),
|
| 355 |
|
|
.data_o ( rg_rd_data_4 ),
|
| 356 |
|
|
.clr_req_o ( clr_req ),
|
| 357 |
|
|
.intr_en_o ( intr_en ),
|
| 358 |
|
|
.thrd_0_i ( thrd_0 ),
|
| 359 |
|
|
.op_code_er_i ( op_code_er ),
|
| 360 |
|
|
.thrd_2_i ( thrd_2 ),
|
| 361 |
|
|
.pop_er_2_i ( pop_er_2 ),
|
| 362 |
|
|
.thrd_3_i ( thrd_3 ),
|
| 363 |
|
|
.push_er_3_i ( push_er_3 ),
|
| 364 |
|
|
.io_lo_i ( io_i[DATA_W/2-1:0] ),
|
| 365 |
|
|
.io_hi_i ( io_i[DATA_W-1:DATA_W/2] ),
|
| 366 |
|
|
.io_lo_o ( io_o[DATA_W/2-1:0] ),
|
| 367 |
|
|
.io_hi_o ( io_o[DATA_W-1:DATA_W/2] ),
|
| 368 |
|
|
.uart_rx_i ( uart_rx_i ),
|
| 369 |
|
|
.uart_tx_o ( uart_tx_o )
|
| 370 |
|
|
);
|
| 371 |
|
|
|
| 372 |
|
|
|
| 373 |
|
|
// instruction and data memory
|
| 374 |
|
|
dp_ram_infer
|
| 375 |
|
|
#(
|
| 376 |
|
|
.REG_A_OUT ( 1 ),
|
| 377 |
|
|
.REG_B_OUT ( 1 ),
|
| 378 |
|
|
.DATA_W ( MEM_DATA_W ),
|
| 379 |
|
|
.ADDR_W ( MEM_ADDR_W ),
|
| 380 |
|
|
.MODE ( "RAW" ) // functional don't care
|
| 381 |
|
|
)
|
| 382 |
|
|
main_mem
|
| 383 |
|
|
(
|
| 384 |
|
|
.a_clk_i ( clk_i ),
|
| 385 |
|
|
.a_addr_i ( dm_addr_2 ),
|
| 386 |
|
|
.a_wr_i ( dm_wr_2 ),
|
| 387 |
|
|
.a_data_i ( wr_data_2 ),
|
| 388 |
|
|
.a_data_o ( dm_rd_data_4 ),
|
| 389 |
|
|
.b_clk_i ( clk_i ),
|
| 390 |
|
|
.b_addr_i ( pc_4 ),
|
| 391 |
|
|
.b_wr_i ( 1'b0 ), // unused
|
| 392 |
|
|
.b_data_i ( ), // unused
|
| 393 |
|
|
.b_data_o ( op_code )
|
| 394 |
|
|
);
|
| 395 |
|
|
|
| 396 |
|
|
|
| 397 |
|
|
endmodule
|
