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ericw |
/*
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--------------------------------------------------------------------------------
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Module : op_decode.v
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--------------------------------------------------------------------------------
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Function:
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- Opcode decoder for processor.
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Instantiates:
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- (2x) pipe.v
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- (1x) op_encode.h
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Notes:
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- I/O optionally registered.
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- Middle register is always present.
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- Operates on the current thread in the stage.
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--------------------------------------------------------------------------------
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*/
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module op_decode
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#(
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parameter integer REGS_IN = 1, // register option for inputs
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parameter integer REGS_OUT = 1, // register option for outputs
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parameter integer STACKS = 8, // number of stacks
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parameter integer STK_W = 3, // stack selector width
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parameter integer DATA_W = 32, // data width
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parameter integer IM_W = 6, // immediate width
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parameter integer MEM_DATA_W = 16, // op code width
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parameter integer LG_SEL_W = 4, // logical operation width
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parameter integer TST_W = 4 // test field width
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)
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(
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// clocks & resets
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input wire clk_i, // clock
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input wire rst_i, // async. reset, active high
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// state I/O
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input wire thrd_clr_i, // thread clear
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input wire thrd_intr_i, // thread interrupt
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input wire [MEM_DATA_W-1:0] op_code_i, // op_code
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output wire op_code_er_o, // 1=illegal op code encountered
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// data I/O
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output wire [IM_W-1:0] im_o, // immediate
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// pc pipe control
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output wire pc_clr_o, // 1 : pc clear
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output wire cnd_o, // 1 : conditional
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output wire lit_o, // 1 : pc=pc++ for literal data
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output wire jmp_o, // 1 : pc=pc+B|I for jump (cond)
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output wire gto_o, // 1 : pc=B for goto / gosub
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output wire intr_o, // 1 : pc=intr
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// conditional masks
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output wire [TST_W-1:0] tst_o, // test field (see tst_encode.h)
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// stacks control
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output wire stk_clr_o, // stacks clear
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output wire [STACKS-1:0] pop_o, // stacks pop
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output wire [STACKS-1:0] push_o, // stacks push
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// alu control
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output wire [STK_W-1:0] data_sel_a_o, // a stack selector
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output wire [STK_W-1:0] data_sel_b_o, // b stack selector
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output wire [STK_W-1:0] addr_sel_b_o, // b stack selector
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output wire imda_o, // 1=immediate data
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output wire imad_o, // 1=immediate address
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output wire sgn_o, // 1=signed
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output wire ext_o, // 1=extended
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output wire hgh_o, // 1=high
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output wire [LG_SEL_W-1:0] lg_sel_o, // logic operation (see lg_sel_encode.h)
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output wire add_o, // 1=add
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output wire sub_o, // 1=subtract
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output wire mul_o, // 1=multiply
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output wire shl_o, // 1=shift left
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output wire pow_o, // 1=power of 2
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output wire rtn_o, // 1=return pc
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output wire dm_rd_o, // 1=read
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output wire dm_wr_o, // 1=write
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output wire rg_rd_o, // 1=read
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output wire rg_wr_o // 1=write
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);
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/*
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----------------------
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-- internal signals --
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----------------------
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*/
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`include "lg_sel_encode.h"
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`include "tst_encode.h"
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`include "op_encode.h"
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//
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wire thrd_clr, thrd_intr;
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wire [MEM_DATA_W-1:0] op_code;
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reg op_ok;
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reg [4:0] op_code_ok;
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wire op_code_er;
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//
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reg [IM_W-1:0] im;
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reg pc_clr;
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reg intr, gto, jmp, lit, cnd;
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reg [TST_W-1:0] tst;
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reg stk_clr;
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reg [4:0] push_a;
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reg [4:0] pop_a, pop_b;
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wire [STACKS-1:0] pop, push;
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reg [STK_W-1:0] data_sel_a, data_sel_b, addr_sel_b;
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reg imda;
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reg imad;
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reg rtn, pow, shl, mul, sub, add, hgh, ext, sgn;
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reg [LG_SEL_W-1:0] lg_sel;
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reg dm_rd, dm_wr, rg_rd, rg_wr;
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reg [STACKS-1:0] pop_all;
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/*
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================
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== code start ==
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================
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*/
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// optional input registers
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pipe
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#(
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.DEPTH ( REGS_IN ),
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.WIDTH ( 2+MEM_DATA_W ),
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.RESET_VAL ( 0 )
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)
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in_regs
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(
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.clk_i ( clk_i ),
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.rst_i ( rst_i ),
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.data_i ( { thrd_clr_i, thrd_intr_i, op_code_i } ),
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.data_o ( { thrd_clr, thrd_intr, op_code } )
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);
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// instantiate & split out op_code fields
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wire [2:0] op_code_sa = op_code[2:0];
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wire op_code_pa = op_code[3];
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wire [2:0] op_code_sb = op_code[6:4];
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wire op_code_pb = op_code[7];
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wire [3:0] op_code_th = op_code[15:12];
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wire [3:0] op_code_tm = { 2'b00, op_code[11:10] };
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wire [3:0] op_code_tl = { 2'b00, op_code[9:8] };
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wire [5:0] op_code_i4 = $signed( op_code[11:8] );
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wire [5:0] op_code_i6 = op_code[9:4];
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wire [7:0] op_code_pf = op_code[7:0];
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//
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reg [2:0] sa_reg, sb_reg;
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// mid register if & case: clear, interrupt, and op_code decode
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always @ ( posedge clk_i or posedge rst_i ) begin
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if ( rst_i ) begin
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op_ok <= 'b0;
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op_code_ok <= 'b0;
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pc_clr <= 'b0;
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cnd <= 'b0;
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lit <= 'b0;
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jmp <= 'b0;
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gto <= 'b0;
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intr <= 'b0;
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tst <= 'b0;
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stk_clr <= 'b0;
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pop_all <= 'b0;
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pop_a <= 'b0;
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pop_b <= 'b0;
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push_a <= 'b0;
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data_sel_a <= 'b0;
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data_sel_b <= 'b0;
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addr_sel_b <= 'b0;
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imda <= 'b0;
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imad <= 'b0;
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im <= 'b0;
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sgn <= 'b0;
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ext <= 'b0;
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hgh <= 'b0;
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lg_sel <= `lg_cpy;
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add <= 'b0;
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sub <= 'b0;
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mul <= 'b0;
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shl <= 'b0;
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pow <= 'b0;
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rtn <= 'b0;
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dm_rd <= 'b0;
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dm_wr <= 'b0;
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rg_rd <= 'b0;
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rg_wr <= 'b0;
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sa_reg <= 'b0;
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sb_reg <= 'b0;
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end else begin
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// default values
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op_ok <= 'b0; // default is bad op
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op_code_ok <= 'b0; // default is bad opcode
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pc_clr <= 'b0; // default is no pc clear
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cnd <= 'b0; // default is unconditional
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lit <= 'b0; // default is no follow
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jmp <= 'b0; // default is no jump
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gto <= 'b0; // default is no goto
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intr <= 'b0; // default is no interrupt
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tst <= op_code_tl; // default is low test field
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stk_clr <= 'b0; // default is no stack clear
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pop_all <= 'b0; // default is no pop
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pop_a <= 'b0; // default is no pop
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pop_b <= 'b0; // default is no pop
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push_a <= 'b0; // default is no push
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data_sel_a <= op_code_sa; // default is op_code directive
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data_sel_b <= op_code_sb; // default is op_code directive
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addr_sel_b <= op_code_sb; // default is op_code directive
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imda <= 'b0; // default is not immediate data
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imad <= 'b0; // default is not immediate address
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im <= op_code_i6; // default is full width
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sgn <= 'b0; // default is unsigned
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hgh <= 'b0; // default is not high
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ext <= 'b0; // default is unextended
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lg_sel <= `lg_cpy; // default is thru
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add <= 'b0; // default is thru
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sub <= 'b0; // default is thru
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mul <= 'b0; // default is thru
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shl <= 'b0; // default is thru
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pow <= 'b0; // default is thru
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rtn <= 'b0; // default is thru
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dm_rd <= 'b0; // default is don't read
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dm_wr <= 'b0; // default is don't write
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rg_rd <= 'b0; // default is don't read
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rg_wr <= 'b0; // default is don't write
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sa_reg <= op_code_sa; // default is follow op_code
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sb_reg <= op_code_sb; // default is follow op_code
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if ( thrd_clr ) begin
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op_ok <= 'b1; // good op
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pc_clr <= 'b1; // clear pc
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stk_clr <= 'b1; // clear stacks
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end else if ( thrd_intr ) begin
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op_ok <= 'b1; // good op
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intr <= 'b1; // don't inc PC
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push_a[0] <= 'b1; // push
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data_sel_a <= 'b0; // push return address to stack 0
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rtn <= 'b1; // push pc
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end else begin
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casex ( op_code )
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////////////////////
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// group 0 - misc //
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////////////////////
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op_nop : begin
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op_code_ok[0] <= 'b1;
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end
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op_pop : begin
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op_code_ok[0] <= 'b1;
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pop_all <= op_code_pf;
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end
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op_pgc : begin
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op_code_ok[0] <= 'b1;
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pop_a[0] <= op_code_pa;
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pop_b[0] <= op_code_pb;
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push_a[0] <= 'b1; // push
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rtn <= 'b1; // push pc
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end
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op_lit_s : begin
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op_code_ok[0] <= 'b1;
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pop_a[0] <= op_code_pa;
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pop_b[0] <= op_code_pb;
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push_a[0] <= 'b1; // push
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lit <= 'b1; // lit
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dm_rd <= 'b1; // dm
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sgn <= 'b1; // signed
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end
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op_lit_h : begin
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op_code_ok[0] <= 'b1;
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pop_a[0] <= op_code_pa;
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pop_b[0] <= op_code_pb;
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push_a[0] <= 'b1; // push
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data_sel_b <= op_code_sa; // route A thru ALU bypass
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lit <= 'b1; // lit
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dm_rd <= 'b1; // dm
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hgh <= 'b1; // high
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end
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op_lit_u : begin
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op_code_ok[0] <= 'b1;
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pop_a[0] <= op_code_pa;
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pop_b[0] <= op_code_pb;
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push_a[0] <= 'b1; // push
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lit <= 'b1; // lit
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dm_rd <= 'b1; // dm
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end
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op_reg_rs : begin
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op_code_ok[0] <= 'b1;
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pop_a[0] <= op_code_pa;
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pop_b[0] <= op_code_pb;
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push_a[0] <= 'b1; // push
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rg_rd <= 'b1; // read
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sgn <= 'b1; // signed
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end
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op_reg_rh : begin
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op_code_ok[0] <= 'b1;
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pop_a[0] <= op_code_pa;
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pop_b[0] <= op_code_pb;
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push_a[0] <= 'b1; // push
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data_sel_b <= op_code_sa; // route A thru ALU bypass
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rg_rd <= 'b1; // read
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hgh <= 'b1; // high
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end
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op_reg_w : begin
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op_code_ok[0] <= 'b1;
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pop_a[0] <= op_code_pa;
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pop_b[0] <= op_code_pb;
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rg_wr <= 'b1; // write
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end
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op_reg_wh : begin
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op_code_ok[0] <= 'b1;
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pop_a[0] <= op_code_pa;
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pop_b[0] <= op_code_pb;
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rg_wr <= 'b1; // write
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hgh <= 'b1; // high
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end
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///////////////////////
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// group 1 - logical //
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///////////////////////
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op_cpy : begin
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op_code_ok[1] <= 'b1;
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pop_a[1] <= op_code_pa;
|
| 322 |
|
|
pop_b[1] <= op_code_pb;
|
| 323 |
|
|
push_a[1] <= 'b1; // push
|
| 324 |
|
|
lg_sel <= `lg_cpy;
|
| 325 |
|
|
end
|
| 326 |
|
|
op_nsg : begin
|
| 327 |
|
|
op_code_ok[1] <= 'b1;
|
| 328 |
|
|
pop_a[1] <= op_code_pa;
|
| 329 |
|
|
pop_b[1] <= op_code_pb;
|
| 330 |
|
|
push_a[1] <= 'b1; // push
|
| 331 |
|
|
lg_sel <= `lg_nsg;
|
| 332 |
|
|
end
|
| 333 |
|
|
op_not : begin
|
| 334 |
|
|
op_code_ok[1] <= 'b1;
|
| 335 |
|
|
pop_a[1] <= op_code_pa;
|
| 336 |
|
|
pop_b[1] <= op_code_pb;
|
| 337 |
|
|
push_a[1] <= 'b1; // push
|
| 338 |
|
|
lg_sel <= `lg_not;
|
| 339 |
|
|
end
|
| 340 |
|
|
op_flp : begin
|
| 341 |
|
|
op_code_ok[1] <= 'b1;
|
| 342 |
|
|
pop_a[1] <= op_code_pa;
|
| 343 |
|
|
pop_b[1] <= op_code_pb;
|
| 344 |
|
|
push_a[1] <= 'b1; // push
|
| 345 |
|
|
lg_sel <= `lg_flp;
|
| 346 |
|
|
end
|
| 347 |
|
|
op_lzc : begin
|
| 348 |
|
|
op_code_ok[1] <= 'b1;
|
| 349 |
|
|
pop_a[1] <= op_code_pa;
|
| 350 |
|
|
pop_b[1] <= op_code_pb;
|
| 351 |
|
|
push_a[1] <= 'b1; // push
|
| 352 |
|
|
lg_sel <= `lg_lzc;
|
| 353 |
|
|
end
|
| 354 |
|
|
op_bra : begin
|
| 355 |
|
|
op_code_ok[1] <= 'b1;
|
| 356 |
|
|
pop_a[1] <= op_code_pa;
|
| 357 |
|
|
pop_b[1] <= op_code_pb;
|
| 358 |
|
|
push_a[1] <= 'b1; // push
|
| 359 |
|
|
lg_sel <= `lg_bra;
|
| 360 |
|
|
end
|
| 361 |
|
|
op_bro : begin
|
| 362 |
|
|
op_code_ok[1] <= 'b1;
|
| 363 |
|
|
pop_a[1] <= op_code_pa;
|
| 364 |
|
|
pop_b[1] <= op_code_pb;
|
| 365 |
|
|
push_a[1] <= 'b1; // push
|
| 366 |
|
|
lg_sel <= `lg_bro;
|
| 367 |
|
|
end
|
| 368 |
|
|
op_brx : begin
|
| 369 |
|
|
op_code_ok[1] <= 'b1;
|
| 370 |
|
|
pop_a[1] <= op_code_pa;
|
| 371 |
|
|
pop_b[1] <= op_code_pb;
|
| 372 |
|
|
push_a[1] <= 'b1; // push
|
| 373 |
|
|
lg_sel <= `lg_brx;
|
| 374 |
|
|
end
|
| 375 |
|
|
op_and : begin
|
| 376 |
|
|
op_code_ok[1] <= 'b1;
|
| 377 |
|
|
pop_a[1] <= op_code_pa;
|
| 378 |
|
|
pop_b[1] <= op_code_pb;
|
| 379 |
|
|
push_a[1] <= 'b1; // push
|
| 380 |
|
|
lg_sel <= `lg_and;
|
| 381 |
|
|
end
|
| 382 |
|
|
op_orr : begin
|
| 383 |
|
|
op_code_ok[1] <= 'b1;
|
| 384 |
|
|
pop_a[1] <= op_code_pa;
|
| 385 |
|
|
pop_b[1] <= op_code_pb;
|
| 386 |
|
|
push_a[1] <= 'b1; // push
|
| 387 |
|
|
lg_sel <= `lg_orr;
|
| 388 |
|
|
end
|
| 389 |
|
|
op_xor : begin
|
| 390 |
|
|
op_code_ok[1] <= 'b1;
|
| 391 |
|
|
pop_a[1] <= op_code_pa;
|
| 392 |
|
|
pop_b[1] <= op_code_pb;
|
| 393 |
|
|
push_a[1] <= 'b1; // push
|
| 394 |
|
|
lg_sel <= `lg_xor;
|
| 395 |
|
|
end
|
| 396 |
|
|
//////////////////////////
|
| 397 |
|
|
// group 2 - arithmetic //
|
| 398 |
|
|
//////////////////////////
|
| 399 |
|
|
op_add : begin
|
| 400 |
|
|
op_code_ok[2] <= 'b1;
|
| 401 |
|
|
pop_a[2] <= op_code_pa;
|
| 402 |
|
|
pop_b[2] <= op_code_pb;
|
| 403 |
|
|
push_a[2] <= 'b1; // push
|
| 404 |
|
|
add <= 'b1; // add
|
| 405 |
|
|
end
|
| 406 |
|
|
op_add_xs : begin
|
| 407 |
|
|
op_code_ok[2] <= 'b1;
|
| 408 |
|
|
pop_a[2] <= op_code_pa;
|
| 409 |
|
|
pop_b[2] <= op_code_pb;
|
| 410 |
|
|
push_a[2] <= 'b1; // push
|
| 411 |
|
|
add <= 'b1; // add
|
| 412 |
|
|
ext <= 'b1; // extended
|
| 413 |
|
|
sgn <= 'b1; // signed
|
| 414 |
|
|
end
|
| 415 |
|
|
op_add_xu : begin
|
| 416 |
|
|
op_code_ok[2] <= 'b1;
|
| 417 |
|
|
pop_a[2] <= op_code_pa;
|
| 418 |
|
|
pop_b[2] <= op_code_pb;
|
| 419 |
|
|
push_a[2] <= 'b1; // push
|
| 420 |
|
|
add <= 'b1; // add
|
| 421 |
|
|
ext <= 'b1; // extended
|
| 422 |
|
|
end
|
| 423 |
|
|
op_sub : begin
|
| 424 |
|
|
op_code_ok[2] <= 'b1;
|
| 425 |
|
|
pop_a[2] <= op_code_pa;
|
| 426 |
|
|
pop_b[2] <= op_code_pb;
|
| 427 |
|
|
push_a[2] <= 'b1; // push
|
| 428 |
|
|
sub <= 'b1; // sub
|
| 429 |
|
|
end
|
| 430 |
|
|
op_sub_xs : begin
|
| 431 |
|
|
op_code_ok[2] <= 'b1;
|
| 432 |
|
|
pop_a[2] <= op_code_pa;
|
| 433 |
|
|
pop_b[2] <= op_code_pb;
|
| 434 |
|
|
push_a[2] <= 'b1; // push
|
| 435 |
|
|
sub <= 'b1; // sub
|
| 436 |
|
|
ext <= 'b1; // extended
|
| 437 |
|
|
sgn <= 'b1; // signed
|
| 438 |
|
|
end
|
| 439 |
|
|
op_sub_xu : begin
|
| 440 |
|
|
op_code_ok[2] <= 'b1;
|
| 441 |
|
|
pop_a[2] <= op_code_pa;
|
| 442 |
|
|
pop_b[2] <= op_code_pb;
|
| 443 |
|
|
push_a[2] <= 'b1; // push
|
| 444 |
|
|
sub <= 'b1; // sub
|
| 445 |
|
|
ext <= 'b1; // extended
|
| 446 |
|
|
end
|
| 447 |
|
|
op_mul : begin
|
| 448 |
|
|
op_code_ok[2] <= 'b1;
|
| 449 |
|
|
pop_a[2] <= op_code_pa;
|
| 450 |
|
|
pop_b[2] <= op_code_pb;
|
| 451 |
|
|
push_a[2] <= 'b1; // push
|
| 452 |
|
|
mul <= 'b1; // multiply
|
| 453 |
|
|
end
|
| 454 |
|
|
op_mul_xs : begin
|
| 455 |
|
|
op_code_ok[2] <= 'b1;
|
| 456 |
|
|
pop_a[2] <= op_code_pa;
|
| 457 |
|
|
pop_b[2] <= op_code_pb;
|
| 458 |
|
|
push_a[2] <= 'b1; // push
|
| 459 |
|
|
mul <= 'b1; // multiply
|
| 460 |
|
|
ext <= 'b1; // extended
|
| 461 |
|
|
sgn <= 'b1; // signed
|
| 462 |
|
|
end
|
| 463 |
|
|
op_mul_xu : begin
|
| 464 |
|
|
op_code_ok[2] <= 'b1;
|
| 465 |
|
|
pop_a[2] <= op_code_pa;
|
| 466 |
|
|
pop_b[2] <= op_code_pb;
|
| 467 |
|
|
push_a[2] <= 'b1; // push
|
| 468 |
|
|
mul <= 'b1; // multiply
|
| 469 |
|
|
ext <= 'b1; // extended
|
| 470 |
|
|
end
|
| 471 |
|
|
op_shl_s : begin
|
| 472 |
|
|
op_code_ok[2] <= 'b1;
|
| 473 |
|
|
pop_a[2] <= op_code_pa;
|
| 474 |
|
|
pop_b[2] <= op_code_pb;
|
| 475 |
|
|
push_a[2] <= 'b1; // push
|
| 476 |
|
|
shl <= 'b1; // shift left
|
| 477 |
|
|
sgn <= 'b1; // signed
|
| 478 |
|
|
end
|
| 479 |
|
|
op_shl_u : begin
|
| 480 |
|
|
op_code_ok[2] <= 'b1;
|
| 481 |
|
|
pop_a[2] <= op_code_pa;
|
| 482 |
|
|
pop_b[2] <= op_code_pb;
|
| 483 |
|
|
push_a[2] <= 'b1; // push
|
| 484 |
|
|
shl <= 'b1; // shift left
|
| 485 |
|
|
end
|
| 486 |
|
|
op_pow : begin
|
| 487 |
|
|
op_code_ok[2] <= 'b1;
|
| 488 |
|
|
pop_a[2] <= op_code_pa;
|
| 489 |
|
|
pop_b[2] <= op_code_pb;
|
| 490 |
|
|
push_a[2] <= 'b1; // push
|
| 491 |
|
|
pow <= 'b1; // power of 2
|
| 492 |
|
|
end
|
| 493 |
|
|
////////////////////////
|
| 494 |
|
|
// group 3 - branches //
|
| 495 |
|
|
////////////////////////
|
| 496 |
|
|
op_jmp_z, op_jmp_nz, op_jmp_lz, op_jmp_nlz : begin
|
| 497 |
|
|
op_code_ok[3] <= 'b1;
|
| 498 |
|
|
pop_a[3] <= op_code_pa;
|
| 499 |
|
|
pop_b[3] <= op_code_pb;
|
| 500 |
|
|
jmp <= 'b1; // jump
|
| 501 |
|
|
cnd <= 'b1; // conditional
|
| 502 |
|
|
tst <= op_code_tl; // lo test field
|
| 503 |
|
|
end
|
| 504 |
|
|
op_jmp : begin
|
| 505 |
|
|
op_code_ok[3] <= 'b1;
|
| 506 |
|
|
pop_a[3] <= op_code_pa;
|
| 507 |
|
|
pop_b[3] <= op_code_pb;
|
| 508 |
|
|
jmp <= 'b1; // jump
|
| 509 |
|
|
end
|
| 510 |
|
|
op_gto : begin
|
| 511 |
|
|
op_code_ok[3] <= 'b1;
|
| 512 |
|
|
pop_a[3] <= op_code_pa;
|
| 513 |
|
|
pop_b[3] <= op_code_pb;
|
| 514 |
|
|
gto <= 'b1; // goto
|
| 515 |
|
|
end
|
| 516 |
|
|
op_gsb : begin
|
| 517 |
|
|
op_code_ok[3] <= 'b1;
|
| 518 |
|
|
pop_a[3] <= op_code_pa;
|
| 519 |
|
|
pop_b[3] <= op_code_pb;
|
| 520 |
|
|
push_a[3] <= 'b1; // push
|
| 521 |
|
|
gto <= 'b1; // goto
|
| 522 |
|
|
rtn <= 'b1; // push pc
|
| 523 |
|
|
end
|
| 524 |
|
|
//////////////////////////
|
| 525 |
|
|
// group 4 - immediates //
|
| 526 |
|
|
//////////////////////////
|
| 527 |
|
|
///////////////////////////////////
|
| 528 |
|
|
// immediate memory read & write //
|
| 529 |
|
|
///////////////////////////////////
|
| 530 |
|
|
op_mem_irs : begin
|
| 531 |
|
|
op_code_ok[4] <= 'b1;
|
| 532 |
|
|
pop_a[4] <= op_code_pa;
|
| 533 |
|
|
pop_b[4] <= op_code_pb;
|
| 534 |
|
|
push_a[4] <= 'b1; // push
|
| 535 |
|
|
im <= op_code_i4; // small im
|
| 536 |
|
|
dm_rd <= 'b1; // read
|
| 537 |
|
|
sgn <= 'b1; // signed
|
| 538 |
|
|
end
|
| 539 |
|
|
op_mem_irh : begin
|
| 540 |
|
|
op_code_ok[4] <= 'b1;
|
| 541 |
|
|
pop_a[4] <= op_code_pa;
|
| 542 |
|
|
pop_b[4] <= op_code_pb;
|
| 543 |
|
|
push_a[4] <= 'b1; // push
|
| 544 |
|
|
im <= op_code_i4; // small im
|
| 545 |
|
|
data_sel_b <= op_code_sa; // route A thru ALU bypass
|
| 546 |
|
|
dm_rd <= 'b1; // read
|
| 547 |
|
|
hgh <= 'b1; // high
|
| 548 |
|
|
end
|
| 549 |
|
|
op_mem_iw : begin
|
| 550 |
|
|
op_code_ok[4] <= 'b1;
|
| 551 |
|
|
pop_a[4] <= op_code_pa;
|
| 552 |
|
|
pop_b[4] <= op_code_pb;
|
| 553 |
|
|
im <= op_code_i4; // small im
|
| 554 |
|
|
dm_wr <= 'b1; // write
|
| 555 |
|
|
end
|
| 556 |
|
|
op_mem_iwh : begin
|
| 557 |
|
|
op_code_ok[4] <= 'b1;
|
| 558 |
|
|
pop_a[4] <= op_code_pa;
|
| 559 |
|
|
pop_b[4] <= op_code_pb;
|
| 560 |
|
|
im <= op_code_i4; // small im
|
| 561 |
|
|
dm_wr <= 'b1; // write
|
| 562 |
|
|
hgh <= 'b1; // high
|
| 563 |
|
|
end
|
| 564 |
|
|
/////////////////////////////////
|
| 565 |
|
|
// immediate conditional jumps //
|
| 566 |
|
|
/////////////////////////////////
|
| 567 |
|
|
op_jmp_ie, op_jmp_ine, op_jmp_ilu, op_jmp_inlu : begin
|
| 568 |
|
|
op_code_ok[4] <= 'b1;
|
| 569 |
|
|
pop_a[4] <= op_code_pa;
|
| 570 |
|
|
pop_b[4] <= op_code_pb;
|
| 571 |
|
|
jmp <= 'b1; // jump
|
| 572 |
|
|
cnd <= 'b1; // conditional
|
| 573 |
|
|
imad <= 'b1; // immediate address
|
| 574 |
|
|
im <= op_code_i4; // small im
|
| 575 |
|
|
tst <= op_code_th; // hi test field
|
| 576 |
|
|
end
|
| 577 |
|
|
op_jmp_ils, op_jmp_inls : begin
|
| 578 |
|
|
op_code_ok[4] <= 'b1;
|
| 579 |
|
|
pop_a[4] <= op_code_pa;
|
| 580 |
|
|
pop_b[4] <= op_code_pb;
|
| 581 |
|
|
jmp <= 'b1; // jump
|
| 582 |
|
|
cnd <= 'b1; // conditional
|
| 583 |
|
|
imad <= 'b1; // immediate address
|
| 584 |
|
|
im <= op_code_i4; // small im
|
| 585 |
|
|
tst <= op_code_th; // hi test field
|
| 586 |
|
|
sgn <= 'b1; // signed
|
| 587 |
|
|
end
|
| 588 |
|
|
op_jmp_iz, op_jmp_inz, op_jmp_ilz, op_jmp_inlz : begin
|
| 589 |
|
|
op_code_ok[4] <= 'b1;
|
| 590 |
|
|
pop_a[4] <= op_code_pa;
|
| 591 |
|
|
jmp <= 'b1; // jump
|
| 592 |
|
|
cnd <= 'b1; // conditional
|
| 593 |
|
|
imad <= 'b1; // immediate address
|
| 594 |
|
|
tst <= op_code_tm; // mid test field
|
| 595 |
|
|
end
|
| 596 |
|
|
////////////////////
|
| 597 |
|
|
// immediate data //
|
| 598 |
|
|
////////////////////
|
| 599 |
|
|
op_dat_is : begin
|
| 600 |
|
|
op_code_ok[4] <= 'b1;
|
| 601 |
|
|
pop_a[4] <= op_code_pa;
|
| 602 |
|
|
push_a[4] <= 'b1; // push
|
| 603 |
|
|
imda <= 'b1; // immediate b data
|
| 604 |
|
|
sgn <= 'b1; // signed
|
| 605 |
|
|
end
|
| 606 |
|
|
///////////////////
|
| 607 |
|
|
// immediate add //
|
| 608 |
|
|
///////////////////
|
| 609 |
|
|
op_add_is : begin
|
| 610 |
|
|
op_code_ok[4] <= 'b1;
|
| 611 |
|
|
pop_a[4] <= op_code_pa;
|
| 612 |
|
|
push_a[4] <= 'b1; // push
|
| 613 |
|
|
imda <= 'b1; // immediate b data
|
| 614 |
|
|
add <= 'b1; // add
|
| 615 |
|
|
sgn <= 'b1; // signed
|
| 616 |
|
|
end
|
| 617 |
|
|
//////////////////////
|
| 618 |
|
|
// immediate shifts //
|
| 619 |
|
|
//////////////////////
|
| 620 |
|
|
op_shl_is : begin
|
| 621 |
|
|
op_code_ok[4] <= 'b1;
|
| 622 |
|
|
pop_a[4] <= op_code_pa;
|
| 623 |
|
|
push_a[4] <= 'b1; // push
|
| 624 |
|
|
imda <= 'b1; // immediate b data
|
| 625 |
|
|
shl <= 'b1; // shift left
|
| 626 |
|
|
sgn <= 'b1; // signed
|
| 627 |
|
|
end
|
| 628 |
|
|
op_psu_i : begin
|
| 629 |
|
|
op_code_ok[4] <= 'b1;
|
| 630 |
|
|
pop_a[4] <= op_code_pa;
|
| 631 |
|
|
push_a[4] <= 'b1; // push
|
| 632 |
|
|
imda <= 'b1; // immediate b data
|
| 633 |
|
|
shl <= 'b1; // shift left
|
| 634 |
|
|
pow <= 'b1; // power of 2
|
| 635 |
|
|
end
|
| 636 |
|
|
default: begin
|
| 637 |
|
|
// nothing here
|
| 638 |
|
|
end
|
| 639 |
|
|
endcase
|
| 640 |
|
|
end
|
| 641 |
|
|
end
|
| 642 |
|
|
end
|
| 643 |
|
|
|
| 644 |
|
|
// decode pop & push (note: use registered select fields here)
|
| 645 |
|
|
assign pop = ( ( |pop_a ) << sa_reg ) | ( ( |pop_b ) << sb_reg ) | pop_all;
|
| 646 |
|
|
assign push = ( |push_a ) << sa_reg;
|
| 647 |
|
|
|
| 648 |
|
|
// decode errors
|
| 649 |
|
|
assign op_code_er = ~( op_ok | ( |op_code_ok ) );
|
| 650 |
|
|
|
| 651 |
|
|
|
| 652 |
|
|
// optional output registers
|
| 653 |
|
|
pipe
|
| 654 |
|
|
#(
|
| 655 |
|
|
.DEPTH ( REGS_OUT ),
|
| 656 |
|
|
.WIDTH ( TST_W+LG_SEL_W+STACKS+STACKS+STK_W+STK_W+STK_W+IM_W ),
|
| 657 |
|
|
.RESET_VAL ( 0 )
|
| 658 |
|
|
)
|
| 659 |
|
|
out_regs_vectors
|
| 660 |
|
|
(
|
| 661 |
|
|
.clk_i ( clk_i ),
|
| 662 |
|
|
.rst_i ( rst_i ),
|
| 663 |
|
|
.data_i ( { tst, lg_sel, push, pop, addr_sel_b, data_sel_b, data_sel_a, im } ),
|
| 664 |
|
|
.data_o ( { tst_o, lg_sel_o, push_o, pop_o, addr_sel_b_o, data_sel_b_o, data_sel_a_o, im_o } )
|
| 665 |
|
|
);
|
| 666 |
|
|
|
| 667 |
|
|
|
| 668 |
|
|
pipe
|
| 669 |
|
|
#(
|
| 670 |
|
|
.DEPTH ( REGS_OUT ),
|
| 671 |
|
|
.WIDTH ( 23 ),
|
| 672 |
|
|
.RESET_VAL ( 0 )
|
| 673 |
|
|
)
|
| 674 |
|
|
out_regs_singles
|
| 675 |
|
|
(
|
| 676 |
|
|
.clk_i ( clk_i ),
|
| 677 |
|
|
.rst_i ( rst_i ),
|
| 678 |
|
|
.data_i ( { op_code_er, pc_clr, cnd, lit, jmp, gto, intr, stk_clr, imda, imad, sgn, ext, hgh, add, sub, mul, shl, pow, rtn, dm_rd, dm_wr, rg_rd, rg_wr } ),
|
| 679 |
|
|
.data_o ( { op_code_er_o, pc_clr_o, cnd_o, lit_o, jmp_o, gto_o, intr_o, stk_clr_o, imda_o, imad_o, sgn_o, ext_o, hgh_o, add_o, sub_o, mul_o, shl_o, pow_o, rtn_o, dm_rd_o, dm_wr_o, rg_rd_o, rg_wr_o } )
|
| 680 |
|
|
);
|
| 681 |
|
|
|
| 682 |
|
|
|
| 683 |
|
|
endmodule
|
