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Module: reg_base.v
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Function:
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- Single base processor register w/ multiple type & input options (synchronous).
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Instantiates:
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- Nothing.
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Notes:
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- Init value for each latched bit.
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- LIVE_MASK[i]=1 indicates live bit.
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- LIVE_MASK[i]=0 indicates dead bit, reads zero.
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- Optional resync (2x registering) of inputs.
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- Optional edge detection (rising) of inputs.
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- rd_data_o is driven non-zero if there is an address match, regardless of
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state of rd_i.
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- Use large OR gate to combine multiple register set read data.
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OUT_MODE:
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- "ZERO" : zero out
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- "THRU" : no latch, direct connect
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- "LTCH" : write latch
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- "LOOP" : no latch, output selected read data
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READ_MODE:
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- "THRU" : no latch, direct connect
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- "CORD" : set on input one, clear on read
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- "COW1" : set on input one, clear on write one
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- "DFFE" : D type flip flop with enable
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- "LOOP" : no latch, read selected output data
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--------------------------------------------------------------------------------
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*/
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module reg_base
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#(
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parameter integer DATA_W = 8, // data width (bits)
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parameter integer ADDR_W = 4, // address width (bits)
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parameter [ADDR_W-1:0] ADDRESS = 0, // address this register responds to
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parameter OUT_MODE = "LOOP", // modes are: "ZERO", "THRU", "LTCH", "LOOP"
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parameter READ_MODE = "COW1", // modes are: "THRU", "CORD", "COW1", "DFFE", "LOOP"
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parameter [DATA_W-1:0] LIVE_MASK = { DATA_W{ 1'b1 } }, // 1=live data bit, 0=dead (0)
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parameter IN_RESYNC = 0, // 1=resync (double clock) input, 0=no resync
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parameter IN_EDGE = 0, // 1=edge (rising) sensitive, 0=level sensitive
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parameter [DATA_W-1:0] RESET_VAL = 0 // reset value of latched data
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)
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(
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// clocks & resets
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input wire clk_i, // clock
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input wire rst_i, // async. reset, active high
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// bus interface
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input wire [ADDR_W-1:0] addr_i, // address
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input wire wr_i, // data write enable, active high
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input wire rd_i, // data read enable, active high
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input wire [DATA_W-1:0] wr_data_i, // write data
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output wire [DATA_W-1:0] rd_data_o, // read data
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// register interface
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output wire reg_wr_o, // reg write active, active high
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output wire reg_rd_o, // reg read active, active high
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input wire reg_en_i, // reg enable, active high ("DFFE" mode only)
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input wire [DATA_W-1:0] reg_data_i, // reg data in
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output wire [DATA_W-1:0] reg_data_o // reg data out
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);
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/*
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----------------------
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-- internal signals --
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----------------------
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*/
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wire addr_match;
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genvar i;
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wire [DATA_W-1:0] in_data, out_data, rd_data;
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/*
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================
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== code start ==
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================
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*/
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// check for address match
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assign addr_match = ( addr_i == ADDRESS[ADDR_W-1:0] );
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// decode read & write
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assign reg_rd_o = ( rd_i & addr_match );
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assign reg_wr_o = ( wr_i & addr_match );
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// generate output logic based on mode
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generate
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for ( i=0; i<DATA_W; i=i+1 ) begin : output_loop
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if ( LIVE_MASK[i] ) begin // live bit
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case ( OUT_MODE )
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"ZERO" : begin
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assign out_data[i] = 1'b0;
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end
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"THRU" : begin
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assign out_data[i] = wr_data_i[i];
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end
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"LTCH" : begin
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reg reg_bit;
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always @ ( posedge clk_i or posedge rst_i ) begin
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if ( rst_i ) begin
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reg_bit <= RESET_VAL[i];
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end else begin
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if ( reg_wr_o ) begin
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reg_bit <= wr_data_i[i];
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end
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end
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end
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assign out_data[i] = reg_bit;
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end
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"LOOP" : begin
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assign out_data[i] = rd_data[i];
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end
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default : begin // unknown mode!
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initial $display ( "OUT_MODE %s does not exist!", OUT_MODE );
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end
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endcase
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end else begin // dead bit
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assign out_data[i] = 1'b0;
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end
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end
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endgenerate
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// generate optional input resync & edge detect logic
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generate
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for ( i=0; i<DATA_W; i=i+1 ) begin : input_processing_loop
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if ( LIVE_MASK[i] ) begin // live bit
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wire in_2;
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if ( IN_RESYNC ) begin
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reg in_0, in_1;
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always @ ( posedge clk_i or posedge rst_i ) begin
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if ( rst_i ) begin
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in_0 <= 1'b0;
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in_1 <= 1'b0;
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end else begin
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in_0 <= reg_data_i[i];
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in_1 <= in_0;
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end
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end
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assign in_2 = in_1;
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end else begin
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assign in_2 = reg_data_i[i];
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end
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//
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if ( IN_EDGE ) begin
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reg in_3;
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always @ ( posedge clk_i or posedge rst_i ) begin
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if ( rst_i ) begin
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in_3 <= 1'b0;
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end else begin
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in_3 <= in_2;
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end
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end
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assign in_data[i] = ( in_2 & ~in_3 );
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end else begin
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assign in_data[i] = in_2;
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end
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end else begin // dead bit
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assign in_data[i] = 1'b0;
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end // endif
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end // endfor
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endgenerate
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// generate read logic based on mode
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generate
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for ( i=0; i<DATA_W; i=i+1 ) begin : read_loop
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if ( LIVE_MASK[i] ) begin // live bit
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case ( READ_MODE )
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"THRU" : begin
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assign rd_data[i] = in_data[i];
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end
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"CORD" : begin
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reg reg_bit;
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always @ ( posedge clk_i or posedge rst_i ) begin
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if ( rst_i ) begin
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reg_bit <= RESET_VAL[i];
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end else begin
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if ( reg_rd_o ) begin
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reg_bit <= 1'b0;
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end else begin
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reg_bit <= reg_bit | in_data[i];
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end
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end
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end
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assign rd_data[i] = reg_bit;
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end
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"COW1" : begin
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reg reg_bit;
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always @ ( posedge clk_i or posedge rst_i ) begin
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if ( rst_i ) begin
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reg_bit <= RESET_VAL[i];
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end else begin
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if ( reg_wr_o ) begin
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reg_bit <= reg_bit & ~wr_data_i[i];
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end else begin
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reg_bit <= reg_bit | in_data[i];
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end
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end
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end
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assign rd_data[i] = reg_bit;
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end
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"DFFE" : begin
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reg reg_bit;
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always @ ( posedge clk_i or posedge rst_i ) begin
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if ( rst_i ) begin
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reg_bit <= RESET_VAL[i];
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end else if ( reg_en_i ) begin
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reg_bit <= in_data[i];
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end
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end
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assign rd_data[i] = reg_bit;
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end
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"LOOP" : begin
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assign rd_data[i] = out_data[i];
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end
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default : begin // unknown mode!
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initial $display ( "RD_MODE %s does not exist!", RD_MODE );
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end
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endcase
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end else begin // dead bit
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assign rd_data[i] = 1'b0;
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end
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end
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endgenerate
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// drive outputs
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assign rd_data_o = ( addr_match ) ? rd_data : 1'b0;
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assign reg_data_o = out_data;
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endmodule
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