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[/] [hive/] [trunk/] [v04.05/] [tst_decode.v] - Blame information for rev 10

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/*
--------------------------------------------------------------------------------
 
Module : tst_decode.v
 
--------------------------------------------------------------------------------
 
Function:
- Processor test decoding for conditional jumps, etc.
 
Instantiates:
- (2x) pipe.v
- (1x) tst_encode.h
 
Notes:
- Parameterized register(s) @ test inputs.
- Parameterized register(s) @ output.
 
--------------------------------------------------------------------------------
*/
 
module tst_decode
        #(
        parameter       integer                                                 REGS_TST                        = 0,             // reg option input to test
        parameter       integer                                                 REGS_OUT                        = 0,             // reg option test to output
        parameter       integer                                                 TST_W                           = 4             // test field width
        )
        (
        // clocks & resets
        input                   wire                                                            clk_i,                                          // clock
        input                   wire                                                            rst_i,                                          // async. reset, active high
        // flags (combinatorial)
        input                   wire                                                            flg_nz_i,                                       //      a != 0
        input                   wire                                                            flg_lz_i,                                       //      a < 0
        input                   wire                                                            flg_ne_i,                                       //      a != b
        input                   wire                                                            flg_lt_i,                                       //      a < b
        // tests (optionally registered)
        input                   wire                                                            cnd_i,                                          // 1=conditional
        input                   wire    [TST_W-1:0]                              tst_i,                                          // test field (see tst_encode.h)
        // output (optionally registered)
        output          wire                                                            result_o                                                // 1=true; 0=false
        );
 
 
        /*
        ----------------------
        -- internal signals --
        ----------------------
        */
        `include "tst_encode.h"
        wire                                                                                            cnd, zro;
        wire                    [TST_W-1:0]                                              tst;
        reg                                                                                             res;
        wire                                                                                            result;
 
 
 
        /*
        ================
        == code start ==
        ================
        */
 
 
        // input to test regs
        pipe
        #(
        .DEPTH          ( REGS_TST ),
        .WIDTH          ( 1+TST_W ),
        .RESET_VAL      ( 0 )
        )
        tst_regs
        (
        .clk_i          ( clk_i ),
        .rst_i          ( rst_i ),
        .data_i         ( { cnd_i, tst_i } ),
        .data_o         ( { cnd,   tst   } )
        );
 
 
        // mux
        always @ ( * ) begin
                case ( tst )
                        `z   : res <= ~flg_nz_i;
                        `nz  : res <=  flg_nz_i;
                        `lz  : res <=  flg_lz_i;
                        `nlz : res <= ~flg_lz_i;
                        `e   : res <= ~flg_ne_i;
                        `ne  : res <=  flg_ne_i;
                        `ls  : res <=  flg_lt_i;
                        `nls : res <= ~flg_lt_i;
                        `lu  : res <=  flg_lt_i;
                        `nlu : res <= ~flg_lt_i;
                        default : res <= 1'b1;  // benign default
                endcase
        end
 
        // output result if conditional, output 1 if not
        assign result = ( cnd ) ? res : 1'b1;
 
 
        // result to output regs
        pipe
        #(
        .DEPTH          ( REGS_OUT ),
        .WIDTH          ( 1 ),
        .RESET_VAL      ( 0 )
        )
        out_regs
        (
        .clk_i          ( clk_i ),
        .rst_i          ( rst_i ),
        .data_i         ( result ),
        .data_o         ( result_o )
        );
 
 
endmodule

Line No.	Rev	Author	Line
1	4	ericw	`/*`
2			`--------------------------------------------------------------------------------`
3
4			`Module : tst_decode.v`
5
6			`--------------------------------------------------------------------------------`
7
8			`Function:`
9			`- Processor test decoding for conditional jumps, etc.`
10
11			`Instantiates:`
12			`- (2x) pipe.v`
13			`- (1x) tst_encode.h`
14
15			`Notes:`
16			`- Parameterized register(s) @ test inputs.`
17			`- Parameterized register(s) @ output.`
18
19			`--------------------------------------------------------------------------------`
20			`*/`
21
22			`module tst_decode`
23			`#(`
24			`parameter integer REGS_TST = 0, // reg option input to test`
25			`parameter integer REGS_OUT = 0, // reg option test to output`
26			`parameter integer TST_W = 4 // test field width`
27			`)`
28			`(`
29			`// clocks & resets`
30			`input wire clk_i, // clock`
31			`input wire rst_i, // async. reset, active high`
32			`// flags (combinatorial)`
33			`input wire flg_nz_i, // a != 0`
34			`input wire flg_lz_i, // a < 0`
35			`input wire flg_ne_i, // a != b`
36			`input wire flg_lt_i, // a < b`
37			`// tests (optionally registered)`
38			`input wire cnd_i, // 1=conditional`
39			`input wire [TST_W-1:0] tst_i, // test field (see tst_encode.h)`
40			`// output (optionally registered)`
41			`output wire result_o // 1=true; 0=false`
42			`);`
43
44
45			`/*`
46			`----------------------`
47			`-- internal signals --`
48			`----------------------`
49			`*/`
50			`include "tst_encode.h"
51			`wire cnd, zro;`
52			`wire [TST_W-1:0] tst;`
53			`reg res;`
54			`wire result;`
55
56
57
58			`/*`
59			`================`
60			`== code start ==`
61			`================`
62			`*/`
63
64
65			`// input to test regs`
66			`pipe`
67			`#(`
68			`.DEPTH ( REGS_TST ),`
69			`.WIDTH ( 1+TST_W ),`
70			`.RESET_VAL ( 0 )`
71			`)`
72			`tst_regs`
73			`(`
74			`.clk_i ( clk_i ),`
75			`.rst_i ( rst_i ),`
76			`.data_i ( { cnd_i, tst_i } ),`
77			`.data_o ( { cnd, tst } )`
78			`);`
79
80
81			`// mux`
82			`always @ ( * ) begin`
83			`case ( tst )`
84			`z : res <= ~flg_nz_i;
85			`nz : res <= flg_nz_i;
86			`lz : res <= flg_lz_i;
87			`nlz : res <= ~flg_lz_i;
88			`e : res <= ~flg_ne_i;
89			`ne : res <= flg_ne_i;
90			`ls : res <= flg_lt_i;
91			`nls : res <= ~flg_lt_i;
92			`lu : res <= flg_lt_i;
93			`nlu : res <= ~flg_lt_i;
94			`default : res <= 1'b1; // benign default`
95			`endcase`
96			`end`
97
98			`// output result if conditional, output 1 if not`
99			`assign result = ( cnd ) ? res : 1'b1;`
100
101
102			`// result to output regs`
103			`pipe`
104			`#(`
105			`.DEPTH ( REGS_OUT ),`
106			`.WIDTH ( 1 ),`
107			`.RESET_VAL ( 0 )`
108			`)`
109			`out_regs`
110			`(`
111			`.clk_i ( clk_i ),`
112			`.rst_i ( rst_i ),`
113			`.data_i ( result ),`
114			`.data_o ( result_o )`
115			`);`
116
117
118			`endmodule`

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[/] [hive/] [trunk/] [v04.05/] [tst_decode.v] - Blame information for rev 10