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[/] [hive/] [trunk/] [v04.05/] [uart_core.v] - Blame information for rev 11

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/*
--------------------------------------------------------------------------------
 
Module: uart_core.v
 
Function:
- TX/RX DATA_W,n,1 RS232 UART.
 
Instantiates:
- (1x) dds_static.v
- (1x) uart_tx.v
- (1x) uart_rx.v
 
Notes:
- See individual components for details.
- Serial loopback does not disconnect serial TX interface.
- Baud rate is fixed, baud clock is calculated from the input parameters.
- Common baud rates are 2400, 3600, and 2x multiples of these:
  - 2400, 4800, 9600, 19200, 38400, 76800, 153600
  - 3600, 7200, 14400, 28800, 57600, 115200
 
--------------------------------------------------------------------------------
*/
 
module uart_core
        #(
        parameter               integer                         CLK_HZ                          = 160000000,    // clk_i rate (Hz)
        parameter               integer                         BAUD_RATE                       = 115200,       // baud rate (Hz)
        parameter               integer                         DATA_W                          = 8             // parallel data width (bits)
        )
        (
        // clocks & resets
        input           wire                                                    clk_i,                                                  // clock
        input           wire                                                    rst_i,                                                  // async. reset, active hi
        // parallel interface   
        input           wire    [DATA_W-1:0]             tx_data_i,                                              // data
        output  wire                                                    tx_rdy_o,                                               // ready for data, active hi
        input           wire                                                    tx_wr_i,                                                        // data write, active high
        //
        output  wire    [DATA_W-1:0]             rx_data_o,                                              // data
        output  wire                                                    rx_rdy_o,                                               // ready with data, active hi
        input           wire                                                    rx_rd_i,                                                        // data read, active hi
        // serial interface
        output  wire                                                    tx_o,                                                           // serial data
        input           wire                                                    rx_i,                                                           // serial data
        // debug
        input           wire                                                    loop_i,                                                 // serial loopback enable, active hi
        output  wire                                                    rx_error_o,                                             // 1=bad start/stop bit; 0=OK
        output  wire                                                    rx_bad_buffer_o,                                // bad rx buffering, active hi
        output  wire                                                    baud_clk_o                                              // baud clock
        );
 
 
        /*
        ----------------------
        -- internal signals --
        ----------------------
        */
        `include "functions.h"  // for clog2()
        //
        localparam              integer                         STOP_BITS                       = 1;            // Number of stop bits (1 or larger)
        localparam              integer                         BAUD_OSR                        = 16;           // baud oversample rate (3 or larger)
        //
        // calculations to set DDS parameters
        //
        localparam              integer                         INC_W                                   = 8;  // sets maximum error
        localparam              real                                    BAUD_HZ                         = BAUD_RATE*BAUD_OSR;
        localparam              real                                    N                                               = CLK_HZ/BAUD_HZ;
        localparam              integer                         ACCUM_W                         = clog2(N)+INC_W-1;
        localparam              integer                         INC_VAL                         = (2**ACCUM_W)/N;
        //
        wire                                                                            rx_bad_start, rx_bad_stop;
 
 
 
        /*
        ================
        == code start ==
        ================
        */
 
 
        dds_static
        #(
        .ACCUM_W                                ( ACCUM_W ),
        .INC_VAL                                ( INC_VAL )
        )
        dds_static_inst
        (
        .clk_i                          ( clk_i ),
        .rst_i                          ( rst_i ),
        .clk_o                          ( baud_clk_o )
        );
 
 
        uart_tx
        #(
        .DATA_W                         ( DATA_W ),
        .BAUD_OSR                       ( BAUD_OSR ),
        .STOP_BITS                      ( STOP_BITS )
        )
        uart_tx_inst
        (
        .clk_i                          ( clk_i ),
        .rst_i                          ( rst_i ),
        .baud_clk_i                     ( baud_clk_o ),
        .tx_data_i                      ( tx_data_i ),
        .tx_rdy_o                       ( tx_rdy_o ),
        .tx_wr_i                                ( tx_wr_i ),
        .tx_o                                   ( tx_o )
        );
 
 
        uart_rx
        #(
        .DATA_W                         ( DATA_W ),
        .BAUD_OSR                       ( BAUD_OSR )
        )
        uart_rx_inst
        (
        .clk_i                          ( clk_i ),
        .rst_i                          ( rst_i ),
        .baud_clk_i                     ( baud_clk_o ),
        .rx_data_o                      ( rx_data_o ),
        .rx_rdy_o                       ( rx_rdy_o ),
        .rx_rd_i                                ( rx_rd_i ),
        .rx_i                                   ( loop_i ? tx_o : rx_i ),
        .rx_bad_start_o ( rx_bad_start ),
        .rx_bad_stop_o          ( rx_bad_stop ),
        .rx_bad_buffer_o        ( rx_bad_buffer_o )
        );
 
 
        // combine errors
        assign rx_error_o = ( rx_bad_start | rx_bad_stop );
 
 
endmodule

Line No.	Rev	Author	Line
1	4	ericw	`/*`
2			`--------------------------------------------------------------------------------`
3
4			`Module: uart_core.v`
5
6			`Function:`
7			`- TX/RX DATA_W,n,1 RS232 UART.`
8
9			`Instantiates:`
10			`- (1x) dds_static.v`
11			`- (1x) uart_tx.v`
12			`- (1x) uart_rx.v`
13
14			`Notes:`
15			`- See individual components for details.`
16			`- Serial loopback does not disconnect serial TX interface.`
17			`- Baud rate is fixed, baud clock is calculated from the input parameters.`
18			`- Common baud rates are 2400, 3600, and 2x multiples of these:`
19			`- 2400, 4800, 9600, 19200, 38400, 76800, 153600`
20			`- 3600, 7200, 14400, 28800, 57600, 115200`
21
22			`--------------------------------------------------------------------------------`
23			`*/`
24
25			`module uart_core`
26			`#(`
27			`parameter integer CLK_HZ = 160000000, // clk_i rate (Hz)`
28			`parameter integer BAUD_RATE = 115200, // baud rate (Hz)`
29			`parameter integer DATA_W = 8 // parallel data width (bits)`
30			`)`
31			`(`
32			`// clocks & resets`
33			`input wire clk_i, // clock`
34			`input wire rst_i, // async. reset, active hi`
35			`// parallel interface`
36			`input wire [DATA_W-1:0] tx_data_i, // data`
37			`output wire tx_rdy_o, // ready for data, active hi`
38			`input wire tx_wr_i, // data write, active high`
39			`//`
40			`output wire [DATA_W-1:0] rx_data_o, // data`
41			`output wire rx_rdy_o, // ready with data, active hi`
42			`input wire rx_rd_i, // data read, active hi`
43			`// serial interface`
44			`output wire tx_o, // serial data`
45			`input wire rx_i, // serial data`
46			`// debug`
47			`input wire loop_i, // serial loopback enable, active hi`
48			`output wire rx_error_o, // 1=bad start/stop bit; 0=OK`
49			`output wire rx_bad_buffer_o, // bad rx buffering, active hi`
50			`output wire baud_clk_o // baud clock`
51			`);`
52
53
54			`/*`
55			`----------------------`
56			`-- internal signals --`
57			`----------------------`
58			`*/`
59			`include "functions.h" // for clog2()
60			`//`
61			`localparam integer STOP_BITS = 1; // Number of stop bits (1 or larger)`
62			`localparam integer BAUD_OSR = 16; // baud oversample rate (3 or larger)`
63			`//`
64			`// calculations to set DDS parameters`
65			`//`
66			`localparam integer INC_W = 8; // sets maximum error`
67			`localparam real BAUD_HZ = BAUD_RATE*BAUD_OSR;`
68			`localparam real N = CLK_HZ/BAUD_HZ;`
69			`localparam integer ACCUM_W = clog2(N)+INC_W-1;`
70			`localparam integer INC_VAL = (2**ACCUM_W)/N;`
71			`//`
72			`wire rx_bad_start, rx_bad_stop;`
73
74
75
76			`/*`
77			`================`
78			`== code start ==`
79			`================`
80			`*/`
81
82
83			`dds_static`
84			`#(`
85			`.ACCUM_W ( ACCUM_W ),`
86			`.INC_VAL ( INC_VAL )`
87			`)`
88			`dds_static_inst`
89			`(`
90			`.clk_i ( clk_i ),`
91			`.rst_i ( rst_i ),`
92			`.clk_o ( baud_clk_o )`
93			`);`
94
95
96			`uart_tx`
97			`#(`
98			`.DATA_W ( DATA_W ),`
99			`.BAUD_OSR ( BAUD_OSR ),`
100			`.STOP_BITS ( STOP_BITS )`
101			`)`
102			`uart_tx_inst`
103			`(`
104			`.clk_i ( clk_i ),`
105			`.rst_i ( rst_i ),`
106			`.baud_clk_i ( baud_clk_o ),`
107			`.tx_data_i ( tx_data_i ),`
108			`.tx_rdy_o ( tx_rdy_o ),`
109			`.tx_wr_i ( tx_wr_i ),`
110			`.tx_o ( tx_o )`
111			`);`
112
113
114			`uart_rx`
115			`#(`
116			`.DATA_W ( DATA_W ),`
117			`.BAUD_OSR ( BAUD_OSR )`
118			`)`
119			`uart_rx_inst`
120			`(`
121			`.clk_i ( clk_i ),`
122			`.rst_i ( rst_i ),`
123			`.baud_clk_i ( baud_clk_o ),`
124			`.rx_data_o ( rx_data_o ),`
125			`.rx_rdy_o ( rx_rdy_o ),`
126			`.rx_rd_i ( rx_rd_i ),`
127			`.rx_i ( loop_i ? tx_o : rx_i ),`
128			`.rx_bad_start_o ( rx_bad_start ),`
129			`.rx_bad_stop_o ( rx_bad_stop ),`
130			`.rx_bad_buffer_o ( rx_bad_buffer_o )`
131			`);`
132
133
134			`// combine errors`
135			`assign rx_error_o = ( rx_bad_start \| rx_bad_stop );`
136
137
138			`endmodule`

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[/] [hive/] [trunk/] [v04.05/] [uart_core.v] - Blame information for rev 11