URL https://opencores.org/ocsvn/hpc-16/hpc-16/trunk

Subversion Repositories hpc-16

[/] [hpc-16/] [trunk/] [impl0/] [sim/] [testbench/] [arith.vhd] - Blame information for rev 15

Details | Compare with Previous | View Log


-- VHDL model created from D:\installed-software\xilinx\spartan3\data\drawing\m2_1.sch - Tue Jul 19 11:19:51 2005
 
 
library ieee;
use ieee.std_logic_1164.ALL;
use ieee.numeric_std.ALL;
-- synopsys translate_off
library UNISIM;
use UNISIM.Vcomponents.ALL;
-- synopsys translate_on
 
entity M2_1_MXILINX_arith is
   port ( D0 : in    std_logic;
          D1 : in    std_logic;
          S0 : in    std_logic;
          O  : out   std_logic);
end M2_1_MXILINX_arith;
 
architecture BEHAVIORAL of M2_1_MXILINX_arith is
   attribute BOX_TYPE   : STRING ;
   signal M0 : std_logic;
   signal M1 : std_logic;
   component AND2B1
      port ( I0 : in    std_logic;
             I1 : in    std_logic;
             O  : out   std_logic);
   end component;
   attribute BOX_TYPE of AND2B1 : COMPONENT is "BLACK_BOX";
 
   component OR2
      port ( I0 : in    std_logic;
             I1 : in    std_logic;
             O  : out   std_logic);
   end component;
   attribute BOX_TYPE of OR2 : COMPONENT is "BLACK_BOX";
 
   component AND2
      port ( I0 : in    std_logic;
             I1 : in    std_logic;
             O  : out   std_logic);
   end component;
   attribute BOX_TYPE of AND2 : COMPONENT is "BLACK_BOX";
 
begin
   I_36_7 : AND2B1
      port map (I0=>S0, I1=>D0, O=>M0);
 
   I_36_8 : OR2
      port map (I0=>M1, I1=>M0, O=>O);
 
   I_36_9 : AND2
      port map (I0=>D1, I1=>S0, O=>M1);
 
end BEHAVIORAL;
 
 
-- VHDL model created from D:\installed-software\xilinx\spartan3\data\drawing\adsu16.sch - Tue Jul 19 11:19:52 2005
 
 
library ieee;
use ieee.std_logic_1164.ALL;
use ieee.numeric_std.ALL;
-- synopsys translate_off
library UNISIM;
use UNISIM.Vcomponents.ALL;
-- synopsys translate_on
 
entity ADSU16_MXILINX_arith is
   port ( A   : in    std_logic_vector (15 downto 0);
          ADD : in    std_logic;
          B   : in    std_logic_vector (15 downto 0);
          CI  : in    std_logic;
          CO  : out   std_logic;
          OFL : out   std_logic;
          S   : out   std_logic_vector (15 downto 0));
end ADSU16_MXILINX_arith;
 
architecture BEHAVIORAL of ADSU16_MXILINX_arith is
   attribute BOX_TYPE   : STRING ;
   attribute RLOC       : STRING ;
   signal C0       : std_logic;
   signal C1       : std_logic;
   signal C2       : std_logic;
   signal C3       : std_logic;
   signal C4       : std_logic;
   signal C5       : std_logic;
   signal C6       : std_logic;
   signal C7       : std_logic;
   signal C8       : std_logic;
   signal C9       : std_logic;
   signal C10      : std_logic;
   signal C11      : std_logic;
   signal C12      : std_logic;
   signal C13      : std_logic;
   signal C14      : std_logic;
   signal C14O     : std_logic;
   signal dummy    : std_logic;
   signal I0       : std_logic;
   signal I1       : std_logic;
   signal I2       : std_logic;
   signal I3       : std_logic;
   signal I4       : std_logic;
   signal I5       : std_logic;
   signal I6       : std_logic;
   signal I7       : std_logic;
   signal I8       : std_logic;
   signal I9       : std_logic;
   signal I10      : std_logic;
   signal I11      : std_logic;
   signal I12      : std_logic;
   signal I13      : std_logic;
   signal I14      : std_logic;
   signal I15      : std_logic;
   signal SUB0     : std_logic;
   signal SUB1     : std_logic;
   signal SUB2     : std_logic;
   signal SUB3     : std_logic;
   signal SUB4     : std_logic;
   signal SUB5     : std_logic;
   signal SUB6     : std_logic;
   signal SUB7     : std_logic;
   signal SUB8     : std_logic;
   signal SUB9     : std_logic;
   signal SUB10    : std_logic;
   signal SUB11    : std_logic;
   signal SUB12    : std_logic;
   signal SUB13    : std_logic;
   signal SUB14    : std_logic;
   signal SUB15    : std_logic;
   signal CO_DUMMY : std_logic;
   component FMAP
      port ( I1 : in    std_logic;
             I2 : in    std_logic;
             I3 : in    std_logic;
             I4 : in    std_logic;
             O  : in    std_logic);
   end component;
   attribute BOX_TYPE of FMAP : COMPONENT is "BLACK_BOX";
 
   component XOR3
      port ( I0 : in    std_logic;
             I1 : in    std_logic;
             I2 : in    std_logic;
             O  : out   std_logic);
   end component;
   attribute BOX_TYPE of XOR3 : COMPONENT is "BLACK_BOX";
 
   component MUXCY_L
      port ( CI : in    std_logic;
             DI : in    std_logic;
             S  : in    std_logic;
             LO : out   std_logic);
   end component;
   attribute BOX_TYPE of MUXCY_L : COMPONENT is "BLACK_BOX";
 
   component MUXCY
      port ( CI : in    std_logic;
             DI : in    std_logic;
             S  : in    std_logic;
             O  : out   std_logic);
   end component;
   attribute BOX_TYPE of MUXCY : COMPONENT is "BLACK_BOX";
 
   component XORCY
      port ( CI : in    std_logic;
             LI : in    std_logic;
             O  : out   std_logic);
   end component;
   attribute BOX_TYPE of XORCY : COMPONENT is "BLACK_BOX";
 
   component MUXCY_D
      port ( CI : in    std_logic;
             DI : in    std_logic;
             S  : in    std_logic;
             LO : out   std_logic;
             O  : out   std_logic);
   end component;
   attribute BOX_TYPE of MUXCY_D : COMPONENT is "BLACK_BOX";
 
   component XOR2
      port ( I0 : in    std_logic;
             I1 : in    std_logic;
             O  : out   std_logic);
   end component;
   attribute BOX_TYPE of XOR2 : COMPONENT is "BLACK_BOX";
 
   component INV
      port ( I : in    std_logic;
             O : out   std_logic);
   end component;
   attribute BOX_TYPE of INV : COMPONENT is "BLACK_BOX";
 
   attribute RLOC of I_36_16 : LABEL is "X1Y4";
   attribute RLOC of I_36_17 : LABEL is "X1Y4";
   attribute RLOC of I_36_18 : LABEL is "X1Y5";
   attribute RLOC of I_36_19 : LABEL is "X1Y5";
   attribute RLOC of I_36_20 : LABEL is "X1Y6";
   attribute RLOC of I_36_21 : LABEL is "X1Y6";
   attribute RLOC of I_36_22 : LABEL is "X1Y7";
   attribute RLOC of I_36_23 : LABEL is "X1Y7";
   attribute RLOC of I_36_55 : LABEL is "X1Y4";
   attribute RLOC of I_36_58 : LABEL is "X1Y5";
   attribute RLOC of I_36_62 : LABEL is "X1Y5";
   attribute RLOC of I_36_63 : LABEL is "X1Y6";
   attribute RLOC of I_36_64 : LABEL is "X1Y7";
   attribute RLOC of I_36_107 : LABEL is "X1Y7";
   attribute RLOC of I_36_110 : LABEL is "X1Y6";
   attribute RLOC of I_36_111 : LABEL is "X1Y4";
   attribute RLOC of I_36_248 : LABEL is "X1Y3";
   attribute RLOC of I_36_249 : LABEL is "X1Y3";
   attribute RLOC of I_36_250 : LABEL is "X1Y2";
   attribute RLOC of I_36_251 : LABEL is "X1Y2";
   attribute RLOC of I_36_252 : LABEL is "X1Y1";
   attribute RLOC of I_36_253 : LABEL is "X1Y1";
   attribute RLOC of I_36_254 : LABEL is "X1Y0";
   attribute RLOC of I_36_255 : LABEL is "X1Y0";
   attribute RLOC of I_36_272 : LABEL is "X1Y0";
   attribute RLOC of I_36_275 : LABEL is "X1Y0";
   attribute RLOC of I_36_279 : LABEL is "X1Y1";
   attribute RLOC of I_36_283 : LABEL is "X1Y1";
   attribute RLOC of I_36_287 : LABEL is "X1Y2";
   attribute RLOC of I_36_291 : LABEL is "X1Y2";
   attribute RLOC of I_36_295 : LABEL is "X1Y3";
   attribute RLOC of I_36_299 : LABEL is "X1Y3";
begin
   CO <= CO_DUMMY;
   I_36_16 : FMAP
      port map (I1=>A(8), I2=>B(8), I3=>ADD, I4=>dummy, O=>I8);
 
   I_36_17 : FMAP
      port map (I1=>A(9), I2=>B(9), I3=>ADD, I4=>dummy, O=>I9);
 
   I_36_18 : FMAP
      port map (I1=>A(10), I2=>B(10), I3=>ADD, I4=>dummy, O=>I10);
 
   I_36_19 : FMAP
      port map (I1=>A(11), I2=>B(11), I3=>ADD, I4=>dummy, O=>I11);
 
   I_36_20 : FMAP
      port map (I1=>A(12), I2=>B(12), I3=>ADD, I4=>dummy, O=>I12);
 
   I_36_21 : FMAP
      port map (I1=>A(13), I2=>B(13), I3=>ADD, I4=>dummy, O=>I13);
 
   I_36_22 : FMAP
      port map (I1=>A(14), I2=>B(14), I3=>ADD, I4=>dummy, O=>I14);
 
   I_36_23 : FMAP
      port map (I1=>A(15), I2=>B(15), I3=>ADD, I4=>dummy, O=>I15);
 
   I_36_50 : XOR3
      port map (I0=>A(8), I1=>B(8), I2=>SUB8, O=>I8);
 
   I_36_55 : MUXCY_L
      port map (CI=>C8, DI=>A(9), S=>I9, LO=>C9);
 
   I_36_56 : XOR3
      port map (I0=>A(10), I1=>B(10), I2=>SUB10, O=>I10);
 
   I_36_57 : XOR3
      port map (I0=>A(11), I1=>B(11), I2=>SUB11, O=>I11);
 
   I_36_58 : MUXCY_L
      port map (CI=>C10, DI=>A(11), S=>I11, LO=>C11);
 
   I_36_59 : XOR3
      port map (I0=>A(14), I1=>B(14), I2=>SUB14, O=>I14);
 
   I_36_60 : XOR3
      port map (I0=>A(12), I1=>B(12), I2=>SUB12, O=>I12);
 
   I_36_62 : MUXCY_L
      port map (CI=>C9, DI=>A(10), S=>I10, LO=>C10);
 
   I_36_63 : MUXCY_L
      port map (CI=>C11, DI=>A(12), S=>I12, LO=>C12);
 
   I_36_64 : MUXCY
      port map (CI=>C14, DI=>A(15), S=>I15, O=>CO_DUMMY);
 
   I_36_73 : XORCY
      port map (CI=>C7, LI=>I8, O=>S(8));
 
   I_36_74 : XORCY
      port map (CI=>C8, LI=>I9, O=>S(9));
 
   I_36_75 : XORCY
      port map (CI=>C10, LI=>I11, O=>S(11));
 
   I_36_76 : XORCY
      port map (CI=>C9, LI=>I10, O=>S(10));
 
   I_36_77 : XORCY
      port map (CI=>C12, LI=>I13, O=>S(13));
 
   I_36_78 : XORCY
      port map (CI=>C11, LI=>I12, O=>S(12));
 
   I_36_79 : XOR3
      port map (I0=>A(15), I1=>B(15), I2=>SUB15, O=>I15);
 
   I_36_80 : XORCY
      port map (CI=>C14, LI=>I15, O=>S(15));
 
   I_36_81 : XORCY
      port map (CI=>C13, LI=>I14, O=>S(14));
 
   I_36_100 : XOR3
      port map (I0=>A(9), I1=>B(9), I2=>SUB9, O=>I9);
 
   I_36_107 : MUXCY_D
      port map (CI=>C13, DI=>A(14), S=>I14, LO=>C14, O=>C14O);
 
   I_36_109 : XOR3
      port map (I0=>A(13), I1=>B(13), I2=>SUB13, O=>I13);
 
   I_36_110 : MUXCY_L
      port map (CI=>C12, DI=>A(13), S=>I13, LO=>C13);
 
   I_36_111 : MUXCY_L
      port map (CI=>C7, DI=>A(8), S=>I8, LO=>C8);
 
   I_36_220 : XOR3
      port map (I0=>A(0), I1=>B(0), I2=>SUB0, O=>I0);
 
   I_36_222 : XOR3
      port map (I0=>A(2), I1=>B(2), I2=>SUB2, O=>I2);
 
   I_36_223 : XOR3
      port map (I0=>A(3), I1=>B(3), I2=>SUB3, O=>I3);
 
   I_36_224 : XOR3
      port map (I0=>A(6), I1=>B(6), I2=>SUB6, O=>I6);
 
   I_36_225 : XOR3
      port map (I0=>A(4), I1=>B(4), I2=>SUB4, O=>I4);
 
   I_36_226 : XORCY
      port map (CI=>CI, LI=>I0, O=>S(0));
 
   I_36_227 : XORCY
      port map (CI=>C0, LI=>I1, O=>S(1));
 
   I_36_228 : XORCY
      port map (CI=>C2, LI=>I3, O=>S(3));
 
   I_36_229 : XORCY
      port map (CI=>C1, LI=>I2, O=>S(2));
 
   I_36_230 : XORCY
      port map (CI=>C4, LI=>I5, O=>S(5));
 
   I_36_231 : XORCY
      port map (CI=>C3, LI=>I4, O=>S(4));
 
   I_36_232 : XOR3
      port map (I0=>A(7), I1=>B(7), I2=>SUB7, O=>I7);
 
   I_36_233 : XORCY
      port map (CI=>C6, LI=>I7, O=>S(7));
 
   I_36_234 : XORCY
      port map (CI=>C5, LI=>I6, O=>S(6));
 
   I_36_243 : XOR3
      port map (I0=>A(1), I1=>B(1), I2=>SUB1, O=>I1);
 
   I_36_245 : XOR3
      port map (I0=>A(5), I1=>B(5), I2=>SUB5, O=>I5);
 
   I_36_248 : MUXCY_L
      port map (CI=>C6, DI=>A(7), S=>I7, LO=>C7);
 
   I_36_249 : MUXCY_L
      port map (CI=>C5, DI=>A(6), S=>I6, LO=>C6);
 
   I_36_250 : MUXCY_L
      port map (CI=>C4, DI=>A(5), S=>I5, LO=>C5);
 
   I_36_251 : MUXCY_L
      port map (CI=>C3, DI=>A(4), S=>I4, LO=>C4);
 
   I_36_252 : MUXCY_L
      port map (CI=>C2, DI=>A(3), S=>I3, LO=>C3);
 
   I_36_253 : MUXCY_L
      port map (CI=>C1, DI=>A(2), S=>I2, LO=>C2);
 
   I_36_254 : MUXCY_L
      port map (CI=>C0, DI=>A(1), S=>I1, LO=>C1);
 
   I_36_255 : MUXCY_L
      port map (CI=>CI, DI=>A(0), S=>I0, LO=>C0);
 
   I_36_272 : FMAP
      port map (I1=>A(1), I2=>B(1), I3=>ADD, I4=>dummy, O=>I1);
 
   I_36_275 : FMAP
      port map (I1=>A(0), I2=>B(0), I3=>ADD, I4=>dummy, O=>I0);
 
   I_36_279 : FMAP
      port map (I1=>A(2), I2=>B(2), I3=>ADD, I4=>dummy, O=>I2);
 
   I_36_283 : FMAP
      port map (I1=>A(3), I2=>B(3), I3=>ADD, I4=>dummy, O=>I3);
 
   I_36_287 : FMAP
      port map (I1=>A(4), I2=>B(4), I3=>ADD, I4=>dummy, O=>I4);
 
   I_36_291 : FMAP
      port map (I1=>A(5), I2=>B(5), I3=>ADD, I4=>dummy, O=>I5);
 
   I_36_295 : FMAP
      port map (I1=>A(6), I2=>B(6), I3=>ADD, I4=>dummy, O=>I6);
 
   I_36_299 : FMAP
      port map (I1=>A(7), I2=>B(7), I3=>ADD, I4=>dummy, O=>I7);
 
   I_36_353 : XOR2
      port map (I0=>C14O, I1=>CO_DUMMY, O=>OFL);
 
   I_36_355 : INV
      port map (I=>ADD, O=>SUB0);
 
   I_36_356 : INV
      port map (I=>ADD, O=>SUB1);
 
   I_36_357 : INV
      port map (I=>ADD, O=>SUB2);
 
   I_36_358 : INV
      port map (I=>ADD, O=>SUB3);
 
   I_36_359 : INV
      port map (I=>ADD, O=>SUB4);
 
   I_36_360 : INV
      port map (I=>ADD, O=>SUB5);
 
   I_36_361 : INV
      port map (I=>ADD, O=>SUB6);
 
   I_36_362 : INV
      port map (I=>ADD, O=>SUB7);
 
   I_36_363 : INV
      port map (I=>ADD, O=>SUB8);
 
   I_36_364 : INV
      port map (I=>ADD, O=>SUB9);
 
   I_36_365 : INV
      port map (I=>ADD, O=>SUB10);
 
   I_36_366 : INV
      port map (I=>ADD, O=>SUB11);
 
   I_36_367 : INV
      port map (I=>ADD, O=>SUB12);
 
   I_36_368 : INV
      port map (I=>ADD, O=>SUB13);
 
   I_36_369 : INV
      port map (I=>ADD, O=>SUB14);
 
   I_36_370 : INV
      port map (I=>ADD, O=>SUB15);
 
end BEHAVIORAL;
 
 
-- VHDL model created from arith.sch - Tue Jul 19 11:19:52 2005
 
 
library ieee;
use ieee.std_logic_1164.ALL;
use ieee.numeric_std.ALL;
-- synopsys translate_off
library UNISIM;
use UNISIM.Vcomponents.ALL;
-- synopsys translate_on
 
entity arith is
   port ( a       : in    std_logic_vector (15 downto 0);
          b       : in    std_logic_vector (15 downto 0);
          c_in    : in    std_logic;
          s0      : in    std_logic;
          s1      : in    std_logic;
          c_out   : out   std_logic;
          ofl_out : out   std_logic;
          result  : out   std_logic_vector (15 downto 0));
end arith;
 
architecture BEHAVIORAL of arith is
   attribute HU_SET     : STRING ;
   attribute BOX_TYPE   : STRING ;
   signal XLXN_14 : std_logic;
   signal XLXN_15 : std_logic;
   signal XLXN_18 : std_logic;
   signal XLXN_24 : std_logic;
   signal XLXN_29 : std_logic;
   signal XLXN_30 : std_logic;
   signal XLXN_35 : std_logic;
   signal zero_i  : std_logic;
   component ADSU16_MXILINX_arith
      port ( A   : in    std_logic_vector (15 downto 0);
             ADD : in    std_logic;
             B   : in    std_logic_vector (15 downto 0);
             CI  : in    std_logic;
             CO  : out   std_logic;
             OFL : out   std_logic;
             S   : out   std_logic_vector (15 downto 0));
   end component;
 
   component M2_1_MXILINX_arith
      port ( D0 : in    std_logic;
             D1 : in    std_logic;
             S0 : in    std_logic;
             O  : out   std_logic);
   end component;
 
   component INV
      port ( I : in    std_logic;
             O : out   std_logic);
   end component;
   attribute BOX_TYPE of INV : COMPONENT is "BLACK_BOX";
 
   component GND
      port ( G : out   std_logic);
   end component;
   attribute BOX_TYPE of GND : COMPONENT is "BLACK_BOX";
 
   attribute HU_SET of XLXI_1 : LABEL is "XLXI_1_0";
   attribute HU_SET of XLXI_2 : LABEL is "XLXI_2_1";
   attribute HU_SET of XLXI_3 : LABEL is "XLXI_3_2";
   attribute HU_SET of XLXI_4 : LABEL is "XLXI_4_4";
   attribute HU_SET of XLXI_11 : LABEL is "XLXI_11_3";
begin
   XLXI_1 : ADSU16_MXILINX_arith
      port map (A(15 downto 0)=>a(15 downto 0), ADD=>s0, B(15 downto 0)=>b(15
            downto 0), CI=>XLXN_35, CO=>XLXN_14, OFL=>ofl_out, S(15 downto
            0)=>result(15 downto 0));
 
   XLXI_2 : M2_1_MXILINX_arith
      port map (D0=>XLXN_15, D1=>XLXN_14, S0=>s0, O=>c_out);
 
   XLXI_3 : M2_1_MXILINX_arith
      port map (D0=>XLXN_29, D1=>XLXN_30, S0=>s1, O=>XLXN_35);
 
   XLXI_4 : M2_1_MXILINX_arith
      port map (D0=>XLXN_24, D1=>c_in, S0=>s0, O=>XLXN_30);
 
   XLXI_8 : INV
      port map (I=>zero_i, O=>XLXN_18);
 
   XLXI_10 : INV
      port map (I=>XLXN_14, O=>XLXN_15);
 
   XLXI_11 : M2_1_MXILINX_arith
      port map (D0=>XLXN_18, D1=>zero_i, S0=>s0, O=>XLXN_29);
 
   XLXI_13 : INV
      port map (I=>c_in, O=>XLXN_24);
 
   XLXI_14 : GND
      port map (G=>zero_i);
 
end BEHAVIORAL;
 
 

Browse

Tools

Subversion Repositories hpc-16

[/] [hpc-16/] [trunk/] [impl0/] [sim/] [testbench/] [arith.vhd] - Blame information for rev 15

Line No.	Rev	Author	Line
1	2	umairsiddi	`-- VHDL model created from D:\installed-software\xilinx\spartan3\data\drawing\m2_1.sch - Tue Jul 19 11:19:51 2005`
2
3
4			`library ieee;`
5			`use ieee.std_logic_1164.ALL;`
6			`use ieee.numeric_std.ALL;`
7			`-- synopsys translate_off`
8			`library UNISIM;`
9			`use UNISIM.Vcomponents.ALL;`
10			`-- synopsys translate_on`
11
12			`entity M2_1_MXILINX_arith is`
13			`port ( D0 : in std_logic;`
14			`D1 : in std_logic;`
15			`S0 : in std_logic;`
16			`O : out std_logic);`
17			`end M2_1_MXILINX_arith;`
18
19			`architecture BEHAVIORAL of M2_1_MXILINX_arith is`
20			`attribute BOX_TYPE : STRING ;`
21			`signal M0 : std_logic;`
22			`signal M1 : std_logic;`
23			`component AND2B1`
24			`port ( I0 : in std_logic;`
25			`I1 : in std_logic;`
26			`O : out std_logic);`
27			`end component;`
28			`attribute BOX_TYPE of AND2B1 : COMPONENT is "BLACK_BOX";`
29
30			`component OR2`
31			`port ( I0 : in std_logic;`
32			`I1 : in std_logic;`
33			`O : out std_logic);`
34			`end component;`
35			`attribute BOX_TYPE of OR2 : COMPONENT is "BLACK_BOX";`
36
37			`component AND2`
38			`port ( I0 : in std_logic;`
39			`I1 : in std_logic;`
40			`O : out std_logic);`
41			`end component;`
42			`attribute BOX_TYPE of AND2 : COMPONENT is "BLACK_BOX";`
43
44			`begin`
45			`I_36_7 : AND2B1`
46			`port map (I0=>S0, I1=>D0, O=>M0);`
47
48			`I_36_8 : OR2`
49			`port map (I0=>M1, I1=>M0, O=>O);`
50
51			`I_36_9 : AND2`
52			`port map (I0=>D1, I1=>S0, O=>M1);`
53
54			`end BEHAVIORAL;`
55
56
57			`-- VHDL model created from D:\installed-software\xilinx\spartan3\data\drawing\adsu16.sch - Tue Jul 19 11:19:52 2005`
58
59
60			`library ieee;`
61			`use ieee.std_logic_1164.ALL;`
62			`use ieee.numeric_std.ALL;`
63			`-- synopsys translate_off`
64			`library UNISIM;`
65			`use UNISIM.Vcomponents.ALL;`
66			`-- synopsys translate_on`
67
68			`entity ADSU16_MXILINX_arith is`
69			`port ( A : in std_logic_vector (15 downto 0);`
70			`ADD : in std_logic;`
71			`B : in std_logic_vector (15 downto 0);`
72			`CI : in std_logic;`
73			`CO : out std_logic;`
74			`OFL : out std_logic;`
75			`S : out std_logic_vector (15 downto 0));`
76			`end ADSU16_MXILINX_arith;`
77
78			`architecture BEHAVIORAL of ADSU16_MXILINX_arith is`
79			`attribute BOX_TYPE : STRING ;`
80			`attribute RLOC : STRING ;`
81			`signal C0 : std_logic;`
82			`signal C1 : std_logic;`
83			`signal C2 : std_logic;`
84			`signal C3 : std_logic;`
85			`signal C4 : std_logic;`
86			`signal C5 : std_logic;`
87			`signal C6 : std_logic;`
88			`signal C7 : std_logic;`
89			`signal C8 : std_logic;`
90			`signal C9 : std_logic;`
91			`signal C10 : std_logic;`
92			`signal C11 : std_logic;`
93			`signal C12 : std_logic;`
94			`signal C13 : std_logic;`
95			`signal C14 : std_logic;`
96			`signal C14O : std_logic;`
97			`signal dummy : std_logic;`
98			`signal I0 : std_logic;`
99			`signal I1 : std_logic;`
100			`signal I2 : std_logic;`
101			`signal I3 : std_logic;`
102			`signal I4 : std_logic;`
103			`signal I5 : std_logic;`
104			`signal I6 : std_logic;`
105			`signal I7 : std_logic;`
106			`signal I8 : std_logic;`
107			`signal I9 : std_logic;`
108			`signal I10 : std_logic;`
109			`signal I11 : std_logic;`
110			`signal I12 : std_logic;`
111			`signal I13 : std_logic;`
112			`signal I14 : std_logic;`
113			`signal I15 : std_logic;`
114			`signal SUB0 : std_logic;`
115			`signal SUB1 : std_logic;`
116			`signal SUB2 : std_logic;`
117			`signal SUB3 : std_logic;`
118			`signal SUB4 : std_logic;`
119			`signal SUB5 : std_logic;`
120			`signal SUB6 : std_logic;`
121			`signal SUB7 : std_logic;`
122			`signal SUB8 : std_logic;`
123			`signal SUB9 : std_logic;`
124			`signal SUB10 : std_logic;`
125			`signal SUB11 : std_logic;`
126			`signal SUB12 : std_logic;`
127			`signal SUB13 : std_logic;`
128			`signal SUB14 : std_logic;`
129			`signal SUB15 : std_logic;`
130			`signal CO_DUMMY : std_logic;`
131			`component FMAP`
132			`port ( I1 : in std_logic;`
133			`I2 : in std_logic;`
134			`I3 : in std_logic;`
135			`I4 : in std_logic;`
136			`O : in std_logic);`
137			`end component;`
138			`attribute BOX_TYPE of FMAP : COMPONENT is "BLACK_BOX";`
139
140			`component XOR3`
141			`port ( I0 : in std_logic;`
142			`I1 : in std_logic;`
143			`I2 : in std_logic;`
144			`O : out std_logic);`
145			`end component;`
146			`attribute BOX_TYPE of XOR3 : COMPONENT is "BLACK_BOX";`
147
148			`component MUXCY_L`
149			`port ( CI : in std_logic;`
150			`DI : in std_logic;`
151			`S : in std_logic;`
152			`LO : out std_logic);`
153			`end component;`
154			`attribute BOX_TYPE of MUXCY_L : COMPONENT is "BLACK_BOX";`
155
156			`component MUXCY`
157			`port ( CI : in std_logic;`
158			`DI : in std_logic;`
159			`S : in std_logic;`
160			`O : out std_logic);`
161			`end component;`
162			`attribute BOX_TYPE of MUXCY : COMPONENT is "BLACK_BOX";`
163
164			`component XORCY`
165			`port ( CI : in std_logic;`
166			`LI : in std_logic;`
167			`O : out std_logic);`
168			`end component;`
169			`attribute BOX_TYPE of XORCY : COMPONENT is "BLACK_BOX";`
170
171			`component MUXCY_D`
172			`port ( CI : in std_logic;`
173			`DI : in std_logic;`
174			`S : in std_logic;`
175			`LO : out std_logic;`
176			`O : out std_logic);`
177			`end component;`
178			`attribute BOX_TYPE of MUXCY_D : COMPONENT is "BLACK_BOX";`
179
180			`component XOR2`
181			`port ( I0 : in std_logic;`
182			`I1 : in std_logic;`
183			`O : out std_logic);`
184			`end component;`
185			`attribute BOX_TYPE of XOR2 : COMPONENT is "BLACK_BOX";`
186
187			`component INV`
188			`port ( I : in std_logic;`
189			`O : out std_logic);`
190			`end component;`
191			`attribute BOX_TYPE of INV : COMPONENT is "BLACK_BOX";`
192
193			`attribute RLOC of I_36_16 : LABEL is "X1Y4";`
194			`attribute RLOC of I_36_17 : LABEL is "X1Y4";`
195			`attribute RLOC of I_36_18 : LABEL is "X1Y5";`
196			`attribute RLOC of I_36_19 : LABEL is "X1Y5";`
197			`attribute RLOC of I_36_20 : LABEL is "X1Y6";`
198			`attribute RLOC of I_36_21 : LABEL is "X1Y6";`
199			`attribute RLOC of I_36_22 : LABEL is "X1Y7";`
200			`attribute RLOC of I_36_23 : LABEL is "X1Y7";`
201			`attribute RLOC of I_36_55 : LABEL is "X1Y4";`
202			`attribute RLOC of I_36_58 : LABEL is "X1Y5";`
203			`attribute RLOC of I_36_62 : LABEL is "X1Y5";`
204			`attribute RLOC of I_36_63 : LABEL is "X1Y6";`
205			`attribute RLOC of I_36_64 : LABEL is "X1Y7";`
206			`attribute RLOC of I_36_107 : LABEL is "X1Y7";`
207			`attribute RLOC of I_36_110 : LABEL is "X1Y6";`
208			`attribute RLOC of I_36_111 : LABEL is "X1Y4";`
209			`attribute RLOC of I_36_248 : LABEL is "X1Y3";`
210			`attribute RLOC of I_36_249 : LABEL is "X1Y3";`
211			`attribute RLOC of I_36_250 : LABEL is "X1Y2";`
212			`attribute RLOC of I_36_251 : LABEL is "X1Y2";`
213			`attribute RLOC of I_36_252 : LABEL is "X1Y1";`
214			`attribute RLOC of I_36_253 : LABEL is "X1Y1";`
215			`attribute RLOC of I_36_254 : LABEL is "X1Y0";`
216			`attribute RLOC of I_36_255 : LABEL is "X1Y0";`
217			`attribute RLOC of I_36_272 : LABEL is "X1Y0";`
218			`attribute RLOC of I_36_275 : LABEL is "X1Y0";`
219			`attribute RLOC of I_36_279 : LABEL is "X1Y1";`
220			`attribute RLOC of I_36_283 : LABEL is "X1Y1";`
221			`attribute RLOC of I_36_287 : LABEL is "X1Y2";`
222			`attribute RLOC of I_36_291 : LABEL is "X1Y2";`
223			`attribute RLOC of I_36_295 : LABEL is "X1Y3";`
224			`attribute RLOC of I_36_299 : LABEL is "X1Y3";`
225			`begin`
226			`CO <= CO_DUMMY;`
227			`I_36_16 : FMAP`
228			`port map (I1=>A(8), I2=>B(8), I3=>ADD, I4=>dummy, O=>I8);`
229
230			`I_36_17 : FMAP`
231			`port map (I1=>A(9), I2=>B(9), I3=>ADD, I4=>dummy, O=>I9);`
232
233			`I_36_18 : FMAP`
234			`port map (I1=>A(10), I2=>B(10), I3=>ADD, I4=>dummy, O=>I10);`
235
236			`I_36_19 : FMAP`
237			`port map (I1=>A(11), I2=>B(11), I3=>ADD, I4=>dummy, O=>I11);`
238
239			`I_36_20 : FMAP`
240			`port map (I1=>A(12), I2=>B(12), I3=>ADD, I4=>dummy, O=>I12);`
241
242			`I_36_21 : FMAP`
243			`port map (I1=>A(13), I2=>B(13), I3=>ADD, I4=>dummy, O=>I13);`
244
245			`I_36_22 : FMAP`
246			`port map (I1=>A(14), I2=>B(14), I3=>ADD, I4=>dummy, O=>I14);`
247
248			`I_36_23 : FMAP`
249			`port map (I1=>A(15), I2=>B(15), I3=>ADD, I4=>dummy, O=>I15);`
250
251			`I_36_50 : XOR3`
252			`port map (I0=>A(8), I1=>B(8), I2=>SUB8, O=>I8);`
253
254			`I_36_55 : MUXCY_L`
255			`port map (CI=>C8, DI=>A(9), S=>I9, LO=>C9);`
256
257			`I_36_56 : XOR3`
258			`port map (I0=>A(10), I1=>B(10), I2=>SUB10, O=>I10);`
259
260			`I_36_57 : XOR3`
261			`port map (I0=>A(11), I1=>B(11), I2=>SUB11, O=>I11);`
262
263			`I_36_58 : MUXCY_L`
264			`port map (CI=>C10, DI=>A(11), S=>I11, LO=>C11);`
265
266			`I_36_59 : XOR3`
267			`port map (I0=>A(14), I1=>B(14), I2=>SUB14, O=>I14);`
268
269			`I_36_60 : XOR3`
270			`port map (I0=>A(12), I1=>B(12), I2=>SUB12, O=>I12);`
271
272			`I_36_62 : MUXCY_L`
273			`port map (CI=>C9, DI=>A(10), S=>I10, LO=>C10);`
274
275			`I_36_63 : MUXCY_L`
276			`port map (CI=>C11, DI=>A(12), S=>I12, LO=>C12);`
277
278			`I_36_64 : MUXCY`
279			`port map (CI=>C14, DI=>A(15), S=>I15, O=>CO_DUMMY);`
280
281			`I_36_73 : XORCY`
282			`port map (CI=>C7, LI=>I8, O=>S(8));`
283
284			`I_36_74 : XORCY`
285			`port map (CI=>C8, LI=>I9, O=>S(9));`
286
287			`I_36_75 : XORCY`
288			`port map (CI=>C10, LI=>I11, O=>S(11));`
289
290			`I_36_76 : XORCY`
291			`port map (CI=>C9, LI=>I10, O=>S(10));`
292
293			`I_36_77 : XORCY`
294			`port map (CI=>C12, LI=>I13, O=>S(13));`
295
296			`I_36_78 : XORCY`
297			`port map (CI=>C11, LI=>I12, O=>S(12));`
298
299			`I_36_79 : XOR3`
300			`port map (I0=>A(15), I1=>B(15), I2=>SUB15, O=>I15);`
301
302			`I_36_80 : XORCY`
303			`port map (CI=>C14, LI=>I15, O=>S(15));`
304
305			`I_36_81 : XORCY`
306			`port map (CI=>C13, LI=>I14, O=>S(14));`
307
308			`I_36_100 : XOR3`
309			`port map (I0=>A(9), I1=>B(9), I2=>SUB9, O=>I9);`
310
311			`I_36_107 : MUXCY_D`
312			`port map (CI=>C13, DI=>A(14), S=>I14, LO=>C14, O=>C14O);`
313
314			`I_36_109 : XOR3`
315			`port map (I0=>A(13), I1=>B(13), I2=>SUB13, O=>I13);`
316
317			`I_36_110 : MUXCY_L`
318			`port map (CI=>C12, DI=>A(13), S=>I13, LO=>C13);`
319
320			`I_36_111 : MUXCY_L`
321			`port map (CI=>C7, DI=>A(8), S=>I8, LO=>C8);`
322
323			`I_36_220 : XOR3`
324			`port map (I0=>A(0), I1=>B(0), I2=>SUB0, O=>I0);`
325
326			`I_36_222 : XOR3`
327			`port map (I0=>A(2), I1=>B(2), I2=>SUB2, O=>I2);`
328
329			`I_36_223 : XOR3`
330			`port map (I0=>A(3), I1=>B(3), I2=>SUB3, O=>I3);`
331
332			`I_36_224 : XOR3`
333			`port map (I0=>A(6), I1=>B(6), I2=>SUB6, O=>I6);`
334
335			`I_36_225 : XOR3`
336			`port map (I0=>A(4), I1=>B(4), I2=>SUB4, O=>I4);`
337
338			`I_36_226 : XORCY`
339			`port map (CI=>CI, LI=>I0, O=>S(0));`
340
341			`I_36_227 : XORCY`
342			`port map (CI=>C0, LI=>I1, O=>S(1));`
343
344			`I_36_228 : XORCY`
345			`port map (CI=>C2, LI=>I3, O=>S(3));`
346
347			`I_36_229 : XORCY`
348			`port map (CI=>C1, LI=>I2, O=>S(2));`
349
350			`I_36_230 : XORCY`
351			`port map (CI=>C4, LI=>I5, O=>S(5));`
352
353			`I_36_231 : XORCY`
354			`port map (CI=>C3, LI=>I4, O=>S(4));`
355
356			`I_36_232 : XOR3`
357			`port map (I0=>A(7), I1=>B(7), I2=>SUB7, O=>I7);`
358
359			`I_36_233 : XORCY`
360			`port map (CI=>C6, LI=>I7, O=>S(7));`
361
362			`I_36_234 : XORCY`
363			`port map (CI=>C5, LI=>I6, O=>S(6));`
364
365			`I_36_243 : XOR3`
366			`port map (I0=>A(1), I1=>B(1), I2=>SUB1, O=>I1);`
367
368			`I_36_245 : XOR3`
369			`port map (I0=>A(5), I1=>B(5), I2=>SUB5, O=>I5);`
370
371			`I_36_248 : MUXCY_L`
372			`port map (CI=>C6, DI=>A(7), S=>I7, LO=>C7);`
373
374			`I_36_249 : MUXCY_L`
375			`port map (CI=>C5, DI=>A(6), S=>I6, LO=>C6);`
376
377			`I_36_250 : MUXCY_L`
378			`port map (CI=>C4, DI=>A(5), S=>I5, LO=>C5);`
379
380			`I_36_251 : MUXCY_L`
381			`port map (CI=>C3, DI=>A(4), S=>I4, LO=>C4);`
382
383			`I_36_252 : MUXCY_L`
384			`port map (CI=>C2, DI=>A(3), S=>I3, LO=>C3);`
385
386			`I_36_253 : MUXCY_L`
387			`port map (CI=>C1, DI=>A(2), S=>I2, LO=>C2);`
388
389			`I_36_254 : MUXCY_L`
390			`port map (CI=>C0, DI=>A(1), S=>I1, LO=>C1);`
391
392			`I_36_255 : MUXCY_L`
393			`port map (CI=>CI, DI=>A(0), S=>I0, LO=>C0);`
394
395			`I_36_272 : FMAP`
396			`port map (I1=>A(1), I2=>B(1), I3=>ADD, I4=>dummy, O=>I1);`
397
398			`I_36_275 : FMAP`
399			`port map (I1=>A(0), I2=>B(0), I3=>ADD, I4=>dummy, O=>I0);`
400
401			`I_36_279 : FMAP`
402			`port map (I1=>A(2), I2=>B(2), I3=>ADD, I4=>dummy, O=>I2);`
403
404			`I_36_283 : FMAP`
405			`port map (I1=>A(3), I2=>B(3), I3=>ADD, I4=>dummy, O=>I3);`
406
407			`I_36_287 : FMAP`
408			`port map (I1=>A(4), I2=>B(4), I3=>ADD, I4=>dummy, O=>I4);`
409
410			`I_36_291 : FMAP`
411			`port map (I1=>A(5), I2=>B(5), I3=>ADD, I4=>dummy, O=>I5);`
412
413			`I_36_295 : FMAP`
414			`port map (I1=>A(6), I2=>B(6), I3=>ADD, I4=>dummy, O=>I6);`
415
416			`I_36_299 : FMAP`
417			`port map (I1=>A(7), I2=>B(7), I3=>ADD, I4=>dummy, O=>I7);`
418
419			`I_36_353 : XOR2`
420			`port map (I0=>C14O, I1=>CO_DUMMY, O=>OFL);`
421
422			`I_36_355 : INV`
423			`port map (I=>ADD, O=>SUB0);`
424
425			`I_36_356 : INV`
426			`port map (I=>ADD, O=>SUB1);`
427
428			`I_36_357 : INV`
429			`port map (I=>ADD, O=>SUB2);`
430
431			`I_36_358 : INV`
432			`port map (I=>ADD, O=>SUB3);`
433
434			`I_36_359 : INV`
435			`port map (I=>ADD, O=>SUB4);`
436
437			`I_36_360 : INV`
438			`port map (I=>ADD, O=>SUB5);`
439
440			`I_36_361 : INV`
441			`port map (I=>ADD, O=>SUB6);`
442
443			`I_36_362 : INV`
444			`port map (I=>ADD, O=>SUB7);`
445
446			`I_36_363 : INV`
447			`port map (I=>ADD, O=>SUB8);`
448
449			`I_36_364 : INV`
450			`port map (I=>ADD, O=>SUB9);`
451
452			`I_36_365 : INV`
453			`port map (I=>ADD, O=>SUB10);`
454
455			`I_36_366 : INV`
456			`port map (I=>ADD, O=>SUB11);`
457
458			`I_36_367 : INV`
459			`port map (I=>ADD, O=>SUB12);`
460
461			`I_36_368 : INV`
462			`port map (I=>ADD, O=>SUB13);`
463
464			`I_36_369 : INV`
465			`port map (I=>ADD, O=>SUB14);`
466
467			`I_36_370 : INV`
468			`port map (I=>ADD, O=>SUB15);`
469
470			`end BEHAVIORAL;`
471
472
473			`-- VHDL model created from arith.sch - Tue Jul 19 11:19:52 2005`
474
475
476			`library ieee;`
477			`use ieee.std_logic_1164.ALL;`
478			`use ieee.numeric_std.ALL;`
479			`-- synopsys translate_off`
480			`library UNISIM;`
481			`use UNISIM.Vcomponents.ALL;`
482			`-- synopsys translate_on`
483
484			`entity arith is`
485			`port ( a : in std_logic_vector (15 downto 0);`
486			`b : in std_logic_vector (15 downto 0);`
487			`c_in : in std_logic;`
488			`s0 : in std_logic;`
489			`s1 : in std_logic;`
490			`c_out : out std_logic;`
491			`ofl_out : out std_logic;`
492			`result : out std_logic_vector (15 downto 0));`
493			`end arith;`
494
495			`architecture BEHAVIORAL of arith is`
496			`attribute HU_SET : STRING ;`
497			`attribute BOX_TYPE : STRING ;`
498			`signal XLXN_14 : std_logic;`
499			`signal XLXN_15 : std_logic;`
500			`signal XLXN_18 : std_logic;`
501			`signal XLXN_24 : std_logic;`
502			`signal XLXN_29 : std_logic;`
503			`signal XLXN_30 : std_logic;`
504			`signal XLXN_35 : std_logic;`
505			`signal zero_i : std_logic;`
506			`component ADSU16_MXILINX_arith`
507			`port ( A : in std_logic_vector (15 downto 0);`
508			`ADD : in std_logic;`
509			`B : in std_logic_vector (15 downto 0);`
510			`CI : in std_logic;`
511			`CO : out std_logic;`
512			`OFL : out std_logic;`
513			`S : out std_logic_vector (15 downto 0));`
514			`end component;`
515
516			`component M2_1_MXILINX_arith`
517			`port ( D0 : in std_logic;`
518			`D1 : in std_logic;`
519			`S0 : in std_logic;`
520			`O : out std_logic);`
521			`end component;`
522
523			`component INV`
524			`port ( I : in std_logic;`
525			`O : out std_logic);`
526			`end component;`
527			`attribute BOX_TYPE of INV : COMPONENT is "BLACK_BOX";`
528
529			`component GND`
530			`port ( G : out std_logic);`
531			`end component;`
532			`attribute BOX_TYPE of GND : COMPONENT is "BLACK_BOX";`
533
534			`attribute HU_SET of XLXI_1 : LABEL is "XLXI_1_0";`
535			`attribute HU_SET of XLXI_2 : LABEL is "XLXI_2_1";`
536			`attribute HU_SET of XLXI_3 : LABEL is "XLXI_3_2";`
537			`attribute HU_SET of XLXI_4 : LABEL is "XLXI_4_4";`
538			`attribute HU_SET of XLXI_11 : LABEL is "XLXI_11_3";`
539			`begin`
540			`XLXI_1 : ADSU16_MXILINX_arith`
541			`port map (A(15 downto 0)=>a(15 downto 0), ADD=>s0, B(15 downto 0)=>b(15`
542			`downto 0), CI=>XLXN_35, CO=>XLXN_14, OFL=>ofl_out, S(15 downto`
543			`0)=>result(15 downto 0));`
544
545			`XLXI_2 : M2_1_MXILINX_arith`
546			`port map (D0=>XLXN_15, D1=>XLXN_14, S0=>s0, O=>c_out);`
547
548			`XLXI_3 : M2_1_MXILINX_arith`
549			`port map (D0=>XLXN_29, D1=>XLXN_30, S0=>s1, O=>XLXN_35);`
550
551			`XLXI_4 : M2_1_MXILINX_arith`
552			`port map (D0=>XLXN_24, D1=>c_in, S0=>s0, O=>XLXN_30);`
553
554			`XLXI_8 : INV`
555			`port map (I=>zero_i, O=>XLXN_18);`
556
557			`XLXI_10 : INV`
558			`port map (I=>XLXN_14, O=>XLXN_15);`
559
560			`XLXI_11 : M2_1_MXILINX_arith`
561			`port map (D0=>XLXN_18, D1=>zero_i, S0=>s0, O=>XLXN_29);`
562
563			`XLXI_13 : INV`
564			`port map (I=>c_in, O=>XLXN_24);`
565
566			`XLXI_14 : GND`
567			`port map (G=>zero_i);`
568
569			`end BEHAVIORAL;`
570
571