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umairsiddi |
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-- ramNx16.vhd
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--------------------------------------------------------------
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-- project: HPC-16 Microprocessor
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--
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-- usage: RAM with async read and sync write operation (not synthsizable, without timing params)
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--
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-- dependency: none
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--
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-- Author: M. Umair Siddiqui (umairsiddiqui@opencores.org)
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---------------------------------------------------------------
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------------------------------------------------------------------------------------
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-- --
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-- Copyright (c) 2005, M. Umair Siddiqui all rights reserved --
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-- --
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-- This file is part of HPC-16. --
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-- --
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-- HPC-16 is free software; you can redistribute it and/or modify --
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-- it under the terms of the GNU Lesser General Public License as published by --
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-- the Free Software Foundation; either version 2.1 of the License, or --
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-- (at your option) any later version. --
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-- --
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-- HPC-16 is distributed in the hope that it will be useful, --
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-- but WITHOUT ANY WARRANTY; without even the implied warranty of --
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-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the --
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-- GNU Lesser General Public License for more details. --
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-- --
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-- You should have received a copy of the GNU Lesser General Public License --
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-- along with HPC-16; if not, write to the Free Software --
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-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA --
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-- --
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------------------------------------------------------------------------------------
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_arith.all;
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use ieee.std_logic_unsigned.all;
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-- synopsis synthesis_off
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use std.textio.all;
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use ieee.std_logic_textio.all;
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-- synopsis synthesis_on
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-------------------------------------
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entity ramNx16 is
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generic
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(
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-- synopsis synthesis_off
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init_file_name : string := "init_ramNx16.txt";
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-- synopsis synthesis_on
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adr_width : integer := 4;
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dat_width : integer := 16
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);
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port
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(
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clk : in std_logic;
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adr : in std_logic_vector(adr_width - 1 downto 0);
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dat_i : in std_logic_vector(dat_width - 1 downto 0);
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--
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cs : in std_logic;
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we : in std_logic;
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ub : in std_logic;
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lb : in std_logic;
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oe : in std_logic;
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--
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dat_o : out std_logic_vector(dat_width - 1 downto 0)
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);
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end ramNx16;
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-----------------------------------------------------------------------
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-----------------------------------------------------------------------
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architecture async of ramNx16 is
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constant locs : integer := 2 ** adr_width;
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type rtype is array(0 to locs - 1) of std_logic_vector((dat_width/2) - 1 downto 0);
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shared variable ram_data_lower : rtype;
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shared variable ram_data_upper : rtype;
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--
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signal s_init : boolean := false;
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--
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signal write_lower : std_logic;
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signal write_upper : std_logic;
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signal out_lower : std_logic;
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signal out_upper : std_logic;
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begin
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----------------------------------------------------------------------------
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-- assertion
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----------------------------------------------------------------------------
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assert dat_width = 16
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report "module is designed for 16-bit data"
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severity error;
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----------------------------------------------------------------------------
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-- init
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----------------------------------------------------------------------------
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-- synopsis sythesis_off
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init: process
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file init_file : text;
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variable buf : line;
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variable address: integer;
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variable sep : character;
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variable data : std_logic_vector(dat_width - 1 downto 0);
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begin
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if ((not s_init) and (init_file_name /= "none")) then
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file_open(init_file, init_file_name, read_mode);
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while (not endfile(init_file)) loop
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readline(init_file, buf);
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read(buf, address);
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read(buf, sep);
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read(buf, data);
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ram_data_lower(address) := data(7 downto 0);
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ram_data_upper(address) := data(15 downto 8);
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end loop;
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file_close(init_file);
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s_init <= true;
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end if;
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wait;
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end process init;
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-- synopsis synthesis_on
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----------------------------------------------------------------------------
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-- main
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----------------------------------------------------------------------------
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write_low: write_lower <= cs and lb and we;
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write_up : write_upper <= cs and ub and we;
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----------------------------------------------------------------------------
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upper: process(clk)
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begin
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-- synopsis synthesis_off
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if (s_init) then
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-- synopsis synthesis_on
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if rising_edge(clk) then
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if write_upper = '1' then
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ram_data_upper(conv_integer(adr)) := dat_i(15 downto 8);
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end if;
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end if;
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-- synopsis synthesis_off
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end if;
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-- synopsis synthesis_on
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end process upper;
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----------------------------------------------------------------------------
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lower: process(clk)
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begin
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-- synopsis synthesis_off
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if (s_init) then
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-- synopsis synthesis_on
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if rising_edge(clk) then
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if write_lower = '1' then
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ram_data_lower(conv_integer(adr)) := dat_i(7 downto 0);
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end if;
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end if;
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-- synopsis synthesis_off
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end if;
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-- synopsis synthesis_on
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end process lower;
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-----------------------------------------------------------------------
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out_low : out_lower <= cs and lb and (not we) and oe;
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out_up : out_upper <= cs and ub and (not we) and oe;
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----------------------------------------------------------------------
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dat_low : dat_o(15 downto 8) <= ram_data_upper(conv_integer(adr)) when out_upper = '1' else
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(others => 'Z');
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dat_up : dat_o(7 downto 0) <= ram_data_lower(conv_integer(adr)) when out_lower = '1' else
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(others => 'Z');
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----------------------------------------------------------------------
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end async;
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