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URL https://opencores.org/ocsvn/hpc-16/hpc-16/trunk

Subversion Repositories hpc-16

[/] [hpc-16/] [trunk/] [impl0/] [sim_junk/] [complete_wave_no_ramcs.do] - Blame information for rev 15

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Line No. Rev Author Line
1 2 umairsiddi
onerror {resume}
2
quietly WaveActivateNextPane {} 0
3
add wave -noupdate -divider {CPU interfacing}
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add wave -noupdate -format Logic -label CLK_I /test/clk_i
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add wave -noupdate -format Logic -label RST_I /test/rst_i
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add wave -noupdate -format Logic -label ACK_I /test/ack_i
7
add wave -noupdate -format Logic -label INTR_I /test/intr_i
8
add wave -noupdate -format Literal -label SEL_O /test/sel_o
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add wave -noupdate -format Logic -label STB_O /test/stb_o
10
add wave -noupdate -format Logic -label CYC_O /test/cyc_o
11
add wave -noupdate -format Logic -label WE_O /test/we_o
12
add wave -noupdate -format Logic -label INTA_CYC_O /test/inta_cyc_o
13
add wave -noupdate -format Logic -label I_CYC_O /test/i_cyc_o
14
add wave -noupdate -format Logic -label C_CYC_O /test/c_cyc_o
15
add wave -noupdate -format Logic -label D_CYC_O /test/d_cyc_o
16
add wave -noupdate -format Literal -label ADR_O -radix hexadecimal /test/adr_o
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add wave -noupdate -format Literal -label DAT_IO -radix hexadecimal /test/dat_io
18
add wave -noupdate -divider {CPU internal (DP)}
19
add wave -noupdate -format Literal -label GPRs -radix hexadecimal -expand /test/cpu/datapath/u1/regfile_data
20
add wave -noupdate -format Literal -label IR -radix hexadecimal /test/cpu/datapath/ir_out
21
add wave -noupdate -format Literal -label MDRI -radix hexadecimal /test/cpu/datapath/mdri_out
22
add wave -noupdate -format Literal -label TR2 -radix hexadecimal /test/cpu/datapath/tr2_out
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add wave -noupdate -format Literal -label PC -radix hexadecimal /test/cpu/datapath/pc_out
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add wave -noupdate -format Literal -label SP -radix hexadecimal /test/cpu/datapath/sp_out
25
add wave -noupdate -format Literal -label FLAGS /test/cpu/datapath/flags_out
26
add wave -noupdate -format Literal -label INTR /test/cpu/datapath/intr_out
27
add wave -noupdate -format Literal -label MAR -radix hexadecimal /test/cpu/datapath/mar_out
28
add wave -noupdate -format Literal -label DFH -radix hexadecimal /test/cpu/datapath/dfh_out
29
add wave -noupdate -format Literal -label MDRO -radix hexadecimal /test/cpu/datapath/mdro_out
30
add wave -noupdate -divider {CPU Internal (Con)}
31
add wave -noupdate -format Logic -label Jcc_OK /test/cpu/control/jcc_ok
32
add wave -noupdate -format Logic -label rst_sync /test/cpu/control/rst_sync
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add wave -noupdate -format Logic -label ack_sync /test/cpu/control/ack_sync
34
add wave -noupdate -format Logic -label intr_sync /test/cpu/control/intr_sync
35
add wave -noupdate -format Literal -label cur_state /test/cpu/control/cur_state
36
add wave -noupdate -format Literal -label nxt_state /test/cpu/control/nxt_state
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add wave -noupdate -format Literal -label cur_ic /test/cpu/control/cur_ic
38
add wave -noupdate -divider RAM
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add wave -noupdate -format Literal -label RAM_data_upper -radix hexadecimal /test/ram/line__87/ram_data_upper
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add wave -noupdate -format Literal -label RAM_data_lower -radix hexadecimal /test/ram/line__87/ram_data_lower
41
add wave -noupdate -divider RAM2
42
add wave -noupdate -format Literal -label RAM2_data_upper -radix hexadecimal /test/ram2/write_low/ram_data_upper
43
add wave -noupdate -format Literal -label RAM2_data_lower -radix hexadecimal /test/ram2/write_low/ram_data_lower
44
TreeUpdate [SetDefaultTree]
45
WaveRestoreCursors {{Cursor 1} {200000 ps} 0}
46
WaveRestoreZoom {0 ps} {197600 ps}
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configure wave -namecolwidth 139
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configure wave -valuecolwidth 95
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configure wave -justifyvalue left
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configure wave -signalnamewidth 0
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configure wave -snapdistance 10
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configure wave -datasetprefix 0
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configure wave -rowmargin 4
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configure wave -childrowmargin 2
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configure wave -gridoffset 0
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configure wave -gridperiod 1
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configure wave -griddelta 40
58
configure wave -timeline 0

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