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[/] [hpc-16/] [trunk/] [impl0/] [sim_junk/] [hpc.cr.mti] - Blame information for rev 18

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1 2 umairsiddi 
D:/MyOpenCoresProjects/hpc-16/impl0/rtl/vhdl/cpu_pkg.vhd {1 {vcom -work work -93 -explicit D:/MyOpenCoresProjects/hpc-16/impl0/rtl/vhdl/cpu_pkg.vhd
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Model Technology ModelSim XE II vcom 5.7g Compiler 2003.10 Oct 13 2003
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-- Loading package standard
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-- Loading package std_logic_1164
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-- Compiling package cpu_pkg
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} {} {}} D:/MyOpenCoresProjects/hpc-16/impl0/rtl/vhdl/con_pkg.vhd {1 {vcom -work work -93 -explicit D:/MyOpenCoresProjects/hpc-16/impl0/rtl/vhdl/con_pkg.vhd
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Model Technology ModelSim XE II vcom 5.7g Compiler 2003.10 Oct 13 2003
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-- Loading package standard
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-- Loading package std_logic_1164
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-- Compiling package con_pkg
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} {} {}} D:/MyOpenCoresProjects/hpc-16/impl0/rtl/vhdl/log.vhd {1 {vcom -work work -93 -explicit D:/MyOpenCoresProjects/hpc-16/impl0/rtl/vhdl/log.vhd
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Model Technology ModelSim XE II vcom 5.7g Compiler 2003.10 Oct 13 2003
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-- Loading package standard
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-- Loading package std_logic_1164
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-- Compiling entity log
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-- Compiling architecture dataflow of log
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} {} {}} D:/MyOpenCoresProjects/hpc-16/impl0/rtl/vhdl/dp.vhd {1 {vcom -work work -93 -explicit D:/MyOpenCoresProjects/hpc-16/impl0/rtl/vhdl/dp.vhd
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Model Technology ModelSim XE II vcom 5.7g Compiler 2003.10 Oct 13 2003
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-- Loading package standard
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-- Loading package std_logic_1164
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-- Loading package std_logic_arith
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-- Loading package dp_pkg
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-- Compiling entity dp
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-- Compiling architecture rtl of dp
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-- Loading package std_logic_unsigned
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-- Loading entity regfile
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-- Loading entity alu
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-- Loading entity shifter
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-- Loading entity flags
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-- Loading entity fcmp
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} {} {}} D:/MyOpenCoresProjects/hpc-16/impl0/rtl/vhdl/shifter.vhd {1 {vcom -work work -93 -explicit D:/MyOpenCoresProjects/hpc-16/impl0/rtl/vhdl/shifter.vhd
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Model Technology ModelSim XE II vcom 5.7g Compiler 2003.10 Oct 13 2003
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-- Loading package standard
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-- Loading package std_logic_1164
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-- Loading package std_logic_arith
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-- Loading package std_logic_unsigned
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-- Compiling entity shifter
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-- Compiling architecture dataflow of shifter
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} {} {}} D:/MyOpenCoresProjects/hpc-16/impl0/rtl/vhdl/dp_pkg.vhd {1 {vcom -work work -93 -explicit D:/MyOpenCoresProjects/hpc-16/impl0/rtl/vhdl/dp_pkg.vhd
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Model Technology ModelSim XE II vcom 5.7g Compiler 2003.10 Oct 13 2003
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-- Loading package standard
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-- Loading package std_logic_1164
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-- Compiling package dp_pkg
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} {} {}} D:/MyOpenCoresProjects/hpc-16/impl0/rtl/vhdl/sync.vhd {1 {vcom -work work -93 -explicit D:/MyOpenCoresProjects/hpc-16/impl0/rtl/vhdl/sync.vhd
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Model Technology ModelSim XE II vcom 5.7g Compiler 2003.10 Oct 13 2003
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-- Loading package standard
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-- Loading package std_logic_1164
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-- Compiling entity sync
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-- Compiling architecture behavioral of sync
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-- Compiling architecture behave2 of sync
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-- Loading entity sync
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} {} {}} D:/MyOpenCoresProjects/hpc-16/impl0/sim/testbench/ram8x16.vhd {1 {vcom -work work -93 -explicit D:/MyOpenCoresProjects/hpc-16/impl0/sim/testbench/ram8x16.vhd
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Model Technology ModelSim XE II vcom 5.7g Compiler 2003.10 Oct 13 2003
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-- Loading package standard
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-- Loading package std_logic_1164
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-- Loading package std_logic_arith
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-- Loading package std_logic_unsigned
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-- Compiling entity ram8x16
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-- Compiling architecture sim of ram8x16
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} {} {}} D:/MyOpenCoresProjects/hpc-16/impl0/sim/testbench/test.vhd {1 {vcom -work work -93 -explicit D:/MyOpenCoresProjects/hpc-16/impl0/sim/testbench/test.vhd
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Model Technology ModelSim XE II vcom 5.7g Compiler 2003.10 Oct 13 2003
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-- Loading package standard
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-- Loading package std_logic_1164
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-- Loading package std_logic_arith
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-- Loading package std_logic_unsigned
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-- Compiling entity test
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-- Compiling architecture sim of test
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-- Loading package textio
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-- Loading package std_logic_textio
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-- Loading entity ramnx16
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-- Loading package cpu_pkg
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-- Loading entity cpu
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-- Loading entity ram8x16
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} {} {}} D:/MyOpenCoresProjects/hpc-16/impl0/sim/testbench/arith.vhd {1 {vcom -work work -93 -explicit D:/MyOpenCoresProjects/hpc-16/impl0/sim/testbench/arith.vhd
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Model Technology ModelSim XE II vcom 5.7g Compiler 2003.10 Oct 13 2003
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-- Loading package standard
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-- Loading package std_logic_1164
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-- Loading package numeric_std
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-- Loading package vital_timing
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-- Loading package vcomponents
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-- Compiling entity m2_1_mxilinx_arith
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-- Compiling architecture behavioral of m2_1_mxilinx_arith
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-- Loading entity and2b1
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-- Loading entity or2
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-- Loading entity and2
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-- Compiling entity adsu16_mxilinx_arith
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-- Compiling architecture behavioral of adsu16_mxilinx_arith
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-- Loading entity fmap
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-- Loading entity xor3
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-- Loading package vital_primitives
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-- Loading entity muxcy_l
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-- Loading entity muxcy
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-- Loading entity xorcy
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-- Loading entity muxcy_d
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-- Loading entity xor2
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-- Loading entity inv
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-- Compiling entity arith
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-- Compiling architecture behavioral of arith
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-- Loading entity adsu16_mxilinx_arith
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-- Loading entity m2_1_mxilinx_arith
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-- Loading entity gnd
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} {} {}} D:/MyOpenCoresProjects/hpc-16/impl0/rtl/vhdl/con1.vhd {1 {vcom -work work -93 -explicit D:/MyOpenCoresProjects/hpc-16/impl0/rtl/vhdl/con1.vhd
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Model Technology ModelSim XE II vcom 5.7g Compiler 2003.10 Oct 13 2003
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-- Loading package standard
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-- Loading package std_logic_1164
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-- Loading package con_pkg
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-- Compiling entity con1
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-- Compiling architecture rtl of con1
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-- Loading entity sync
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} {} {}} D:/MyOpenCoresProjects/hpc-16/impl0/rtl/vhdl/alu.vhd {1 {vcom -work work -93 -explicit D:/MyOpenCoresProjects/hpc-16/impl0/rtl/vhdl/alu.vhd
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Model Technology ModelSim XE II vcom 5.7g Compiler 2003.10 Oct 13 2003
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-- Loading package standard
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-- Loading package std_logic_1164
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-- Compiling entity alu
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-- Compiling architecture struct of alu
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-- Loading package numeric_std
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-- Loading package vital_timing
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-- Loading package vcomponents
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-- Loading entity arith
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-- Loading entity log
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} {} {}} D:/MyOpenCoresProjects/hpc-16/impl0/rtl/vhdl/flags.vhd {1 {vcom -work work -93 -explicit D:/MyOpenCoresProjects/hpc-16/impl0/rtl/vhdl/flags.vhd
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Model Technology ModelSim XE II vcom 5.7g Compiler 2003.10 Oct 13 2003
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-- Loading package standard
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-- Loading package std_logic_1164
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-- Compiling entity flags
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-- Compiling architecture behavioral of flags
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} {} {}} D:/MyOpenCoresProjects/hpc-16/impl0/sim/testbench/ramNx16.vhd {1 {vcom -work work -93 -explicit D:/MyOpenCoresProjects/hpc-16/impl0/sim/testbench/ramNx16.vhd
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Model Technology ModelSim XE II vcom 5.7g Compiler 2003.10 Oct 13 2003
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-- Loading package standard
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-- Loading package std_logic_1164
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-- Loading package std_logic_arith
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-- Loading package std_logic_unsigned
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-- Loading package textio
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-- Loading package std_logic_textio
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-- Compiling entity ramnx16
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-- Compiling architecture async of ramnx16
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} {} {}} D:/MyOpenCoresProjects/hpc-16/impl0/rtl/vhdl/fcmp.vhd {1 {vcom -work work -93 -explicit D:/MyOpenCoresProjects/hpc-16/impl0/rtl/vhdl/fcmp.vhd
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Model Technology ModelSim XE II vcom 5.7g Compiler 2003.10 Oct 13 2003
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-- Loading package standard
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-- Loading package std_logic_1164
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-- Compiling entity fcmp
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-- Compiling architecture behavioral of fcmp
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} {} {}} D:/MyOpenCoresProjects/hpc-16/impl0/rtl/vhdl/regfile.vhd {1 {vcom -work work -93 -explicit D:/MyOpenCoresProjects/hpc-16/impl0/rtl/vhdl/regfile.vhd
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Model Technology ModelSim XE II vcom 5.7g Compiler 2003.10 Oct 13 2003
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-- Loading package standard
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-- Loading package std_logic_1164
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-- Loading package std_logic_arith
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-- Loading package std_logic_unsigned
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-- Compiling entity regfile
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-- Compiling architecture behavioral of regfile
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} {} {}} D:/MyOpenCoresProjects/hpc-16/impl0/rtl/vhdl/cpu.vhd {1 {vcom -work work -93 -explicit D:/MyOpenCoresProjects/hpc-16/impl0/rtl/vhdl/cpu.vhd
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Model Technology ModelSim XE II vcom 5.7g Compiler 2003.10 Oct 13 2003
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-- Loading package standard
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-- Loading package std_logic_1164
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-- Loading package cpu_pkg
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-- Compiling entity cpu
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-- Compiling architecture struct of cpu
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-- Loading package con_pkg
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-- Loading entity con1
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-- Loading package std_logic_arith
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-- Loading package dp_pkg
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-- Loading entity dp
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} {} {}}

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