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lekernel |
/*
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* Milkymist VJ SoC
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* Copyright (C) 2007, 2008, 2009 Sebastien Bourdeauducq
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*
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* This program is free software: you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation, version 3 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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module hpdmc_mgmt #(
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parameter sdram_depth = 26,
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parameter sdram_columndepth = 9
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) (
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input sys_clk,
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input sdram_rst,
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input [2:0] tim_rp,
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input [2:0] tim_rcd,
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input [10:0] tim_refi,
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input [3:0] tim_rfc,
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input stb,
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input we,
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input [sdram_depth-3-1:0] address, /* in 64-bit words */
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output reg ack,
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output reg read,
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output reg write,
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output [3:0] concerned_bank,
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input read_safe,
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input write_safe,
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input [3:0] precharge_safe,
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output sdram_cs_n,
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output sdram_we_n,
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output sdram_cas_n,
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output sdram_ras_n,
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output [12:0] sdram_adr,
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output [1:0] sdram_ba
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);
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/*
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* Address Mapping :
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* | ROW ADDRESS | BANK NUMBER | COL ADDRESS | for 32-bit words
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* |depth-1 coldepth+2|coldepth+1 coldepth|coldepth-1 0|
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* (depth for 32-bit words, which is sdram_depth-2)
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*/
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parameter rowdepth = sdram_depth-2-1-(sdram_columndepth+2)+1;
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wire [sdram_depth-2-1:0] address32 = {address, 1'b0};
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wire [sdram_columndepth-1:0] col_address = address32[sdram_columndepth-1:0];
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wire [1:0] bank_address = address32[sdram_columndepth+1:sdram_columndepth];
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wire [rowdepth-1:0] row_address = address32[sdram_depth-2-1:sdram_columndepth+2];
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reg [3:0] bank_address_onehot;
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always @(*) begin
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case(bank_address)
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2'b00: bank_address_onehot <= 4'b0001;
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2'b01: bank_address_onehot <= 4'b0010;
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2'b10: bank_address_onehot <= 4'b0100;
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2'b11: bank_address_onehot <= 4'b1000;
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endcase
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end
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/* Track open rows */
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reg [3:0] has_openrow;
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reg [rowdepth-1:0] openrows[0:3];
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reg [3:0] track_close;
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reg [3:0] track_open;
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always @(posedge sys_clk) begin
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if(sdram_rst) begin
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has_openrow = 4'h0;
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end else begin
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has_openrow = (has_openrow | track_open) & ~track_close;
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if(track_open[0]) openrows[0] <= row_address;
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if(track_open[1]) openrows[1] <= row_address;
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if(track_open[2]) openrows[2] <= row_address;
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if(track_open[3]) openrows[3] <= row_address;
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end
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end
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/* Bank precharge safety */
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assign concerned_bank = bank_address_onehot;
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wire current_precharge_safe =
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(precharge_safe[0] | ~bank_address_onehot[0])
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&(precharge_safe[1] | ~bank_address_onehot[1])
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&(precharge_safe[2] | ~bank_address_onehot[2])
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&(precharge_safe[3] | ~bank_address_onehot[3]);
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/* Check for page hits */
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wire bank_open = has_openrow[bank_address];
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wire page_hit = bank_open & (openrows[bank_address] == row_address);
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/* Address drivers */
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reg sdram_adr_loadrow;
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reg sdram_adr_loadcol;
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reg sdram_adr_loadA10;
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assign sdram_adr =
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({13{sdram_adr_loadrow}} & row_address)
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|({13{sdram_adr_loadcol}} & col_address)
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|({13{sdram_adr_loadA10}} & 13'd1024);
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assign sdram_ba = bank_address;
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/* Command drivers */
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reg sdram_cs;
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reg sdram_we;
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reg sdram_cas;
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reg sdram_ras;
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assign sdram_cs_n = ~sdram_cs;
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assign sdram_we_n = ~sdram_we;
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assign sdram_cas_n = ~sdram_cas;
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assign sdram_ras_n = ~sdram_ras;
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/* Timing counters */
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/* The number of clocks we must wait following a PRECHARGE command (usually tRP). */
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reg [2:0] precharge_counter;
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reg reload_precharge_counter;
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wire precharge_done = (precharge_counter == 3'd0);
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always @(posedge sys_clk) begin
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if(reload_precharge_counter)
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precharge_counter <= tim_rp;
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else if(~precharge_done)
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precharge_counter <= precharge_counter - 3'd1;
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end
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/* The number of clocks we must wait following an ACTIVATE command (usually tRCD). */
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reg [2:0] activate_counter;
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reg reload_activate_counter;
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wire activate_done = (activate_counter == 3'd0);
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always @(posedge sys_clk) begin
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if(reload_activate_counter)
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activate_counter <= tim_rcd;
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else if(~activate_done)
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activate_counter <= activate_counter - 3'd1;
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end
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/* The number of clocks we have left before we must refresh one row in the SDRAM array (usually tREFI). */
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reg [10:0] refresh_counter;
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reg reload_refresh_counter;
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wire must_refresh = refresh_counter == 11'd0;
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always @(posedge sys_clk) begin
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if(sdram_rst)
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refresh_counter <= 11'd0;
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else begin
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if(reload_refresh_counter)
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refresh_counter <= tim_refi;
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else if(~must_refresh)
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refresh_counter <= refresh_counter - 11'd1;
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end
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end
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/* The number of clocks we must wait following an AUTO REFRESH command (usually tRFC). */
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reg [3:0] autorefresh_counter;
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reg reload_autorefresh_counter;
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wire autorefresh_done = (autorefresh_counter == 4'd0);
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always @(posedge sys_clk) begin
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if(reload_autorefresh_counter)
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autorefresh_counter <= tim_rfc;
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else if(~autorefresh_done)
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autorefresh_counter <= autorefresh_counter - 4'd1;
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end
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/* FSM that pushes commands into the SDRAM */
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reg [3:0] state;
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reg [3:0] next_state;
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parameter IDLE = 4'd0;
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parameter ACTIVATE = 4'd1;
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parameter READ = 4'd2;
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parameter WRITE = 4'd3;
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parameter PRECHARGEALL = 4'd4;
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parameter AUTOREFRESH = 4'd5;
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parameter AUTOREFRESH_WAIT = 4'd6;
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always @(posedge sys_clk) begin
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if(sdram_rst)
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state <= IDLE;
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else begin
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//$display("state: %d -> %d", state, next_state);
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state <= next_state;
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end
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end
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always @(*) begin
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next_state = state;
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reload_precharge_counter = 1'b0;
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reload_activate_counter = 1'b0;
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reload_refresh_counter = 1'b0;
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reload_autorefresh_counter = 1'b0;
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sdram_cs = 1'b0;
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sdram_we = 1'b0;
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sdram_cas = 1'b0;
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sdram_ras = 1'b0;
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sdram_adr_loadrow = 1'b0;
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sdram_adr_loadcol = 1'b0;
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sdram_adr_loadA10 = 1'b0;
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track_close = 4'b0000;
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track_open = 4'b0000;
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read = 1'b0;
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write = 1'b0;
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ack = 1'b0;
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case(state)
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IDLE: begin
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if(must_refresh)
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next_state = PRECHARGEALL;
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else begin
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if(stb) begin
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if(page_hit) begin
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if(we) begin
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if(write_safe) begin
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/* Write */
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sdram_cs = 1'b1;
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sdram_ras = 1'b0;
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sdram_cas = 1'b1;
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sdram_we = 1'b1;
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sdram_adr_loadcol = 1'b1;
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write = 1'b1;
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ack = 1'b1;
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end
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end else begin
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if(read_safe) begin
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/* Read */
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sdram_cs = 1'b1;
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sdram_ras = 1'b0;
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sdram_cas = 1'b1;
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sdram_we = 1'b0;
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sdram_adr_loadcol = 1'b1;
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read = 1'b1;
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ack = 1'b1;
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end
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end
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end else begin
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if(bank_open) begin
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if(current_precharge_safe) begin
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/* Precharge Bank */
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sdram_cs = 1'b1;
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sdram_ras = 1'b1;
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sdram_cas = 1'b0;
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sdram_we = 1'b1;
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track_close = bank_address_onehot;
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reload_precharge_counter = 1'b1;
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next_state = ACTIVATE;
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end
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end else begin
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/* Activate */
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sdram_cs = 1'b1;
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sdram_ras = 1'b1;
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sdram_cas = 1'b0;
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sdram_we = 1'b0;
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sdram_adr_loadrow = 1'b1;
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| 278 |
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track_open = bank_address_onehot;
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reload_activate_counter = 1'b1;
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if(we)
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next_state = WRITE;
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else
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next_state = READ;
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end
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end
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end
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end
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end
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ACTIVATE: begin
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| 291 |
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if(precharge_done) begin
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| 292 |
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sdram_cs = 1'b1;
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| 293 |
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sdram_ras = 1'b1;
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| 294 |
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sdram_cas = 1'b0;
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| 295 |
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sdram_we = 1'b0;
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| 296 |
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sdram_adr_loadrow = 1'b1;
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| 297 |
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| 298 |
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track_open = bank_address_onehot;
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| 299 |
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reload_activate_counter = 1'b1;
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| 300 |
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if(we)
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| 301 |
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next_state = WRITE;
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| 302 |
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else
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| 303 |
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next_state = READ;
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| 304 |
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end
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| 305 |
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end
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| 306 |
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READ: begin
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| 307 |
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if(activate_done) begin
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| 308 |
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if(read_safe) begin
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| 309 |
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sdram_cs = 1'b1;
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| 310 |
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sdram_ras = 1'b0;
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| 311 |
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sdram_cas = 1'b1;
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| 312 |
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sdram_we = 1'b0;
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| 313 |
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sdram_adr_loadcol = 1'b1;
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| 314 |
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| 315 |
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read = 1'b1;
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| 316 |
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ack = 1'b1;
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| 317 |
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next_state = IDLE;
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| 318 |
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end
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| 319 |
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end
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| 320 |
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end
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| 321 |
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WRITE: begin
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| 322 |
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if(activate_done) begin
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| 323 |
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if(write_safe) begin
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| 324 |
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sdram_cs = 1'b1;
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| 325 |
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sdram_ras = 1'b0;
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| 326 |
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sdram_cas = 1'b1;
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| 327 |
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sdram_we = 1'b1;
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| 328 |
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sdram_adr_loadcol = 1'b1;
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| 329 |
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| 330 |
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write = 1'b1;
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| 331 |
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ack = 1'b1;
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| 332 |
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next_state = IDLE;
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| 333 |
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end
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| 334 |
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end
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| 335 |
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end
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| 336 |
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| 337 |
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PRECHARGEALL: begin
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| 338 |
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if(precharge_safe == 4'b1111) begin
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| 339 |
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sdram_cs = 1'b1;
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| 340 |
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sdram_ras = 1'b1;
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| 341 |
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sdram_cas = 1'b0;
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| 342 |
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sdram_we = 1'b1;
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| 343 |
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sdram_adr_loadA10 = 1'b1;
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| 344 |
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| 345 |
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reload_precharge_counter = 1'b1;
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| 346 |
|
|
|
| 347 |
|
|
track_close = 4'b1111;
|
| 348 |
|
|
|
| 349 |
|
|
next_state = AUTOREFRESH;
|
| 350 |
|
|
end
|
| 351 |
|
|
end
|
| 352 |
|
|
AUTOREFRESH: begin
|
| 353 |
|
|
if(precharge_done) begin
|
| 354 |
|
|
sdram_cs = 1'b1;
|
| 355 |
|
|
sdram_ras = 1'b1;
|
| 356 |
|
|
sdram_cas = 1'b1;
|
| 357 |
|
|
sdram_we = 1'b0;
|
| 358 |
|
|
reload_refresh_counter = 1'b1;
|
| 359 |
|
|
reload_autorefresh_counter = 1'b1;
|
| 360 |
|
|
next_state = AUTOREFRESH_WAIT;
|
| 361 |
|
|
end
|
| 362 |
|
|
end
|
| 363 |
|
|
AUTOREFRESH_WAIT: begin
|
| 364 |
|
|
if(autorefresh_done)
|
| 365 |
|
|
next_state = IDLE;
|
| 366 |
|
|
end
|
| 367 |
|
|
|
| 368 |
|
|
endcase
|
| 369 |
|
|
end
|
| 370 |
|
|
|
| 371 |
|
|
endmodule
|
