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1 21 lekernel 
/****************************************************************************************
2 
*
3 
*    File Name:  ddr.v
4 
*      Version:  6.00
5 
*        Model:  BUS Functional
6 
*
7 
* Dependencies:  ddr_parameters.v
8 
*
9 
*  Description:  Micron SDRAM DDR (Double Data Rate)
10 
*
11 
*   Limitation:  - Doesn't check for 8K-cycle refresh.
12 
*                - Doesn't check power-down entry/exit
13 
*                - Doesn't check self-refresh entry/exit.
14 
*
15 
*         Note:  - Set simulator resolution to "ps" accuracy
16 
*                - Set DEBUG = 0 to disable $display messages
17 
*                - Model assume Clk and Clk# crossing at both edge
18 
*
19 
*   Disclaimer   This software code and all associated documentation, comments or other
20 
*  of Warranty:  information (collectively "Software") is provided "AS IS" without
21 
*                warranty of any kind. MICRON TECHNOLOGY, INC. ("MTI") EXPRESSLY
22 
*                DISCLAIMS ALL WARRANTIES EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED
23 
*                TO, NONINFRINGEMENT OF THIRD PARTY RIGHTS, AND ANY IMPLIED WARRANTIES
24 
*                OF MERCHANTABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE. MTI DOES NOT
25 
*                WARRANT THAT THE SOFTWARE WILL MEET YOUR REQUIREMENTS, OR THAT THE
26 
*                OPERATION OF THE SOFTWARE WILL BE UNINTERRUPTED OR ERROR-FREE.
27 
*                FURTHERMORE, MTI DOES NOT MAKE ANY REPRESENTATIONS REGARDING THE USE OR
28 
*                THE RESULTS OF THE USE OF THE SOFTWARE IN TERMS OF ITS CORRECTNESS,
29 
*                ACCURACY, RELIABILITY, OR OTHERWISE. THE ENTIRE RISK ARISING OUT OF USE
30 
*                OR PERFORMANCE OF THE SOFTWARE REMAINS WITH YOU. IN NO EVENT SHALL MTI,
31 
*                ITS AFFILIATED COMPANIES OR THEIR SUPPLIERS BE LIABLE FOR ANY DIRECT,
32 
*                INDIRECT, CONSEQUENTIAL, INCIDENTAL, OR SPECIAL DAMAGES (INCLUDING,
33 
*                WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS INTERRUPTION,
34 
*                OR LOSS OF INFORMATION) ARISING OUT OF YOUR USE OF OR INABILITY TO USE
35 
*                THE SOFTWARE, EVEN IF MTI HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH
36 
*                DAMAGES. Because some jurisdictions prohibit the exclusion or
37 
*                limitation of liability for consequential or incidental damages, the
38 
*                above limitation may not apply to you.
39 
*
40 
*                Copyright 2003 Micron Technology, Inc. All rights reserved.
41 
*
42 
* Rev  Author Date        Changes
43 
* ---  ------ ----------  ---------------------------------------
44 
* 2.1   SPH    03/19/2002  - Second Release
45 
*                          - Fix tWR and several incompatability
46 
*                            between different simulators
47 
* 3.0   TFK    02/18/2003  - Added tDSS and tDSH timing checks.
48 
*                          - Added tDQSH and tDQSL timing checks.
49 
* 3.1   CAH    05/28/2003  - update all models to release version 3.1
50 
*                            (no changes to this model)
51 
* 3.2   JMK    06/16/2003  - updated all DDR400 models to support CAS Latency 3
52 
* 3.3   JMK    09/11/2003  - Added initialization sequence checks.
53 
* 4.0   JMK    12/01/2003  - Grouped parameters into "ddr_parameters.v"
54 
*                          - Fixed tWTR check
55 
* 4.1   JMK    01/14/2004  - Grouped specify parameters by speed grade
56 
*                          - Fixed mem_sizes parameter
57 
* 4.2   JMK    03/19/2004  - Fixed pulse width checking on Dqs
58 
* 4.3   JMK    04/27/2004  - Changed BL wire size in tb module
59 
*                          - Changed Dq_buf size to [15:0]
60 
* 5.0   JMK    06/16/2004  - Added read to write checking.
61 
*                          - Added read with precharge truncation to write checking.
62 
*                          - Added associative memory array to reduce memory consumption.
63 
*                          - Added checking for required DQS edges during write.
64 
* 5.1   JMK    08/16/2004  - Fixed checking for required DQS edges during write.
65 
*                          - Fixed wdqs_valid window.
66 
* 5.2   JMK    09/24/2004  - Read or Write without activate will be ignored.
67 
* 5.3   JMK    10/27/2004  - Added tMRD checking during Auto Refresh and Activate.
68 
*                          - Added tRFC checking during Load Mode and Precharge.
69 
* 5.4   JMK    12/13/2004  - The model will not respond to illegal command sequences.
70 
* 5.5   SPH    01/13/2005  - The model will issue a halt on illegal command sequences.
71 
*       JMK    02/11/2005  - Changed the display format for numbers to hex.
72 
* 5.6   JMK    04/22/2005  - Fixed Write with auto precharge calculation.
73 
* 5.7   JMK    08/05/2005  - Changed conditions for read with precharge truncation error.
74 
*                          - Renamed parameters file with .vh extension.
75 
* 5.8   BAS    12/26/2006  - Added parameters for T46A part - 256Mb
76 
*                          - Added x32 functionality
77 
* 6.00  JMK    05/31/2007  - Added ddr_184_dimm module model
78 
* 6.00  BAS    05/31/2007  - Updated 128Mb, 256Mb, 512Mb, and 1024Mb parameter sheets
79 
****************************************************************************************/
80 
 
81 
// DO NOT CHANGE THE TIMESCALE
82 
// MAKE SURE YOUR SIMULATOR USE "PS" RESOLUTION
83 
`timescale 1ns / 1ps
84 
 
85 
module ddr (Clk, Clk_n, Cke, Cs_n, Ras_n, Cas_n, We_n, Ba , Addr, Dm, Dq, Dqs);
86 
    `include "ddr_parameters.vh"
87 
 
88 
    // Port Declarations
89 
    input                         Clk;
90 
    input                         Clk_n;
91 
    input                         Cke;
92 
    input                         Cs_n;
93 
    input                         Ras_n;
94 
    input                         Cas_n;
95 
    input                         We_n;
96 
    input                 [1 : 0] Ba;
97 
    input     [ADDR_BITS - 1 : 0] Addr;
98 
    input       [DM_BITS - 1 : 0] Dm;
99 
    inout       [DQ_BITS - 1 : 0] Dq;
100 
    inout      [DQS_BITS - 1 : 0] Dqs;
101 
 
102 
    // Internal Wires (fixed width)
103 
    wire                 [31 : 0] Dq_in;
104 
    wire                  [3 : 0] Dqs_in;
105 
    wire                  [3 : 0] Dm_in;
106 
 
107 
    assign Dq_in   [DQ_BITS - 1 : 0] = Dq;
108 
    assign Dqs_in [DQS_BITS - 1 : 0] = Dqs;
109 
    assign Dm_in   [DM_BITS - 1 : 0] = Dm;
110 
 
111 
    // Data pair
112 
    reg                  [31 : 0] dq_rise;
113 
    reg                   [3 : 0] dm_rise;
114 
    reg                  [31 : 0] dq_fall;
115 
    reg                   [3 : 0] dm_fall;
116 
    reg                   [7 : 0] dm_pair;
117 
    reg                  [31 : 0] Dq_buf;
118 
 
119 
    // Mode Register
120 
    reg       [ADDR_BITS - 1 : 0] Mode_reg;
121 
 
122 
    // Internal System Clock
123 
    reg                           CkeZ, Sys_clk;
124 
 
125 
    // Internal Dqs initialize
126 
    reg                           Dqs_int;
127 
 
128 
    // Dqs buffer
129 
    reg        [DQS_BITS - 1 : 0] Dqs_out;
130 
 
131 
    // Dq buffer
132 
    reg         [DQ_BITS - 1 : 0] Dq_out;
133 
 
134 
    // Read pipeline variables
135 
    reg                           Read_cmnd [0 : 6];
136 
    reg                   [1 : 0] Read_bank [0 : 6];
137 
    reg        [COL_BITS - 1 : 0] Read_cols [0 : 6];
138 
 
139 
    // Write pipeline variables
140 
    reg                           Write_cmnd [0 : 3];
141 
    reg                   [1 : 0] Write_bank [0 : 3];
142 
    reg        [COL_BITS - 1 : 0] Write_cols [0 : 3];
143 
 
144 
    // Auto precharge variables
145 
    reg                           Read_precharge  [0 : 3];
146 
    reg                           Write_precharge [0 : 3];
147 
    integer                       Count_precharge [0 : 3];
148 
 
149 
    // Manual precharge variables
150 
    reg                           A10_precharge  [0 : 6];
151 
    reg                   [1 : 0] Bank_precharge [0 : 6];
152 
    reg                           Cmnd_precharge [0 : 6];
153 
 
154 
    // Burst terminate variables
155 
    reg                           Cmnd_bst [0 : 6];
156 
 
157 
    // Memory Banks
158 
`ifdef FULL_MEM
159 
    reg         [DQ_BITS - 1 : 0] mem_array  [0 : (1<<full_mem_bits)-1];
160 
`else
161 
    reg         [DQ_BITS - 1 : 0] mem_array  [0 : (1<<part_mem_bits)-1];
162 
    reg   [full_mem_bits - 1 : 0] addr_array [0 : (1<<part_mem_bits)-1];
163 
    reg   [part_mem_bits     : 0] mem_used;
164 
    initial mem_used = 0;
165 
`endif
166 
 
167 
    // Dqs edge checking
168 
    integer i;
169 
    reg  [3 :0] expect_pos_dqs;
170 
    reg  [3 :0] expect_neg_dqs;
171 
 
172 
    // Burst counter
173 
    reg        [COL_BITS - 1 : 0] Burst_counter;
174 
 
175 
    // Precharge variables
176 
    reg                           Pc_b0, Pc_b1, Pc_b2, Pc_b3;
177 
 
178 
    // Activate variables
179 
    reg                           Act_b0, Act_b1, Act_b2, Act_b3;
180 
 
181 
    // Data IO variables
182 
    reg                           Data_in_enable;
183 
    reg                           Data_out_enable;
184 
 
185 
    // Internal address mux variables
186 
    reg                   [1 : 0] Prev_bank;
187 
    reg                   [1 : 0] Bank_addr;
188 
    reg        [COL_BITS - 1 : 0] Cols_addr, Cols_brst, Cols_temp;
189 
    reg       [ADDR_BITS - 1 : 0] Rows_addr;
190 
    reg       [ADDR_BITS - 1 : 0] B0_row_addr;
191 
    reg       [ADDR_BITS - 1 : 0] B1_row_addr;
192 
    reg       [ADDR_BITS - 1 : 0] B2_row_addr;
193 
    reg       [ADDR_BITS - 1 : 0] B3_row_addr;
194 
 
195 
    // DLL Reset variable
196 
    reg                           DLL_enable;
197 
    reg                           DLL_reset;
198 
    reg                           DLL_done;
199 
    integer                       DLL_count;
200 
    integer                       aref_count;
201 
    integer                       Prech_count;
202 
    reg                           power_up_done;
203 
 
204 
    // Write DQS for tDSS, tDSH, tDQSH, tDQSL checks
205 
    wire      wdqs_valid = Write_cmnd[2] || Write_cmnd[1] || Data_in_enable;
206 
 
207 
    // Commands Decode
208 
    wire      Active_enable   = ~Cs_n & ~Ras_n &  Cas_n &  We_n;
209 
    wire      Aref_enable     = ~Cs_n & ~Ras_n & ~Cas_n &  We_n;
210 
    wire      Burst_term      = ~Cs_n &  Ras_n &  Cas_n & ~We_n;
211 
    wire      Ext_mode_enable = ~Cs_n & ~Ras_n & ~Cas_n & ~We_n &  Ba[0] & ~Ba[1];
212 
    wire      Mode_reg_enable = ~Cs_n & ~Ras_n & ~Cas_n & ~We_n & ~Ba[0] & ~Ba[1];
213 
    wire      Prech_enable    = ~Cs_n & ~Ras_n &  Cas_n & ~We_n;
214 
    wire      Read_enable     = ~Cs_n &  Ras_n & ~Cas_n &  We_n;
215 
    wire      Write_enable    = ~Cs_n &  Ras_n & ~Cas_n & ~We_n;
216 
 
217 
    // Burst Length Decode
218 
    wire [3:0] burst_length = 1 << (Mode_reg[2:0]);
219 
    reg  [3:0] read_precharge_truncation;
220 
 
221 
    // CAS Latency Decode
222 
    wire [2:0] cas_latency_x2 = (Mode_reg[6:4] === 3'o6) ? 5 : 2*Mode_reg[6:4];
223 
 
224 
    // DQS Buffer
225 
    assign    Dqs = Dqs_out;
226 
 
227 
    // DQ Buffer
228 
    assign    Dq  = Dq_out;
229 
 
230 
    // Timing Check
231 
    time      MRD_chk;
232 
    time      RFC_chk;
233 
    time      RRD_chk;
234 
    time      RAS_chk0, RAS_chk1, RAS_chk2, RAS_chk3;
235 
    time      RAP_chk0, RAP_chk1, RAP_chk2, RAP_chk3;
236 
    time      RC_chk0, RC_chk1, RC_chk2, RC_chk3;
237 
    time      RCD_chk0, RCD_chk1, RCD_chk2, RCD_chk3;
238 
    time      RP_chk0, RP_chk1, RP_chk2, RP_chk3;
239 
    time      WR_chk0, WR_chk1, WR_chk2, WR_chk3;
240 
 
241 
    initial begin
242 
        CkeZ = 1'b0;
243 
        Sys_clk = 1'b0;
244 
        {Pc_b0, Pc_b1, Pc_b2, Pc_b3} = 4'b0000;
245 
        {Act_b0, Act_b1, Act_b2, Act_b3} = 4'b1111;
246 
        Dqs_int = 1'b0;
247 
        Dqs_out = {DQS_BITS{1'bz}};
248 
        Dq_out = {DQ_BITS{1'bz}};
249 
        Data_in_enable = 1'b0;
250 
        Data_out_enable = 1'b0;
251 
        DLL_enable = 1'b0;
252 
        DLL_reset = 1'b0;
253 
        DLL_done = 1'b0;
254 
        DLL_count = 0;
255 
        aref_count = 0;
256 
        Prech_count = 0;
257 
        power_up_done = 0;
258 
        MRD_chk = 0;
259 
        RFC_chk = 0;
260 
        RRD_chk = 0;
261 
        Mode_reg = 0; // added by lekernel to suppress warnings during first commands
262 
        {RAS_chk0, RAS_chk1, RAS_chk2, RAS_chk3} = 0;
263 
        {RAP_chk0, RAP_chk1, RAP_chk2, RAP_chk3} = 0;
264 
        {RC_chk0, RC_chk1, RC_chk2, RC_chk3} = 0;
265 
        {RCD_chk0, RCD_chk1, RCD_chk2, RCD_chk3} = 0;
266 
        {RP_chk0, RP_chk1, RP_chk2, RP_chk3} = 0;
267 
        {WR_chk0, WR_chk1, WR_chk2, WR_chk3} = 0;
268 
        $timeformat (-9, 3, " ns", 12);
269 
    end
270 
 
271 
    // System Clock
272 
    always begin
273 
        @ (posedge Clk) begin
274 
            Sys_clk = CkeZ;
275 
            CkeZ = Cke;
276 
        end
277 
        @ (negedge Clk) begin
278 
            Sys_clk = 1'b0;
279 
        end
280 
    end
281 
 
282 
    // Check to make sure that we have a Deselect or NOP command on the bus when CKE is brought high
283 
    always @(Cke) begin
284 
        if (Cke === 1'b1) begin
285 
            if (!((Cs_n) || (~Cs_n &  Ras_n & Cas_n &  We_n))) begin
286 
                $display ("%m: at time %t MEMORY ERROR:  You must have a Deselect or NOP command applied", $time);
287 
                $display ("%m:           when the Clock Enable is brought High.");
288 
            end
289 
        end
290 
    end
291 
 
292 
    // Check the initialization sequence
293 
    initial begin
294 
        @ (posedge Cke) begin
295 
            @ (posedge DLL_enable) begin
296 
                aref_count = 0;
297 
                @ (posedge DLL_reset) begin
298 
                    @ (Prech_count) begin
299 
                        if (aref_count >= 2) begin
300 
                            if (DEBUG) $display ("%m: at time %t MEMORY:  Power Up and Initialization Sequence is complete", $time);
301 
                            power_up_done = 1;
302 
                        end else begin
303 
                            aref_count = 0;
304 
                            @ (aref_count >= 2) begin
305 
                                if (DEBUG) $display ("%m: at time %t MEMORY:  Power Up and Initialization Sequence is complete", $time);
306 
                                power_up_done = 1;
307 
                            end
308 
                        end
309 
                    end
310 
                end
311 
            end
312 
        end
313 
    end
314 
 
315 
    // Write Memory
316 
    task write_mem;
317 
        input [full_mem_bits - 1 : 0] addr;
318 
        input       [DQ_BITS - 1 : 0] data;
319 
        reg       [part_mem_bits : 0] i;
320 
        begin
321 
`ifdef FULL_MEM
322 
            mem_array[addr] = data;
323 
`else
324 
            begin : loop
325 
                for (i = 0; i < mem_used; i = i + 1) begin
326 
                    if (addr_array[i] === addr) begin
327 
                        disable loop;
328 
                    end
329 
                end
330 
            end
331 
            if (i === mem_used) begin
332 
                if (i === (1<<part_mem_bits)) begin
333 
                    $display ("%m: At time %t ERROR: Memory overflow.\n  Write to Address %h with Data %h will be lost.\n  You must increase the part_mem_bits parameter or define FULL_MEM.", $time, addr, data);
334 
                end else begin
335 
                    mem_used = mem_used + 1;
336 
                    addr_array[i] = addr;
337 
                end
338 
            end
339 
            mem_array[i] = data;
340 
`endif
341 
        end
342 
    endtask
343 
 
344 
    // Read Memory
345 
    task read_mem;
346 
        input [full_mem_bits - 1 : 0] addr;
347 
        output      [DQ_BITS - 1 : 0] data;
348 
        reg       [part_mem_bits : 0] i;
349 
        begin
350 
`ifdef FULL_MEM
351 
            data = mem_array[addr];
352 
`else
353 
            begin : loop
354 
                for (i = 0; i < mem_used; i = i + 1) begin
355 
                    if (addr_array[i] === addr) begin
356 
                        disable loop;
357 
                    end
358 
                end
359 
            end
360 
            if (i <= mem_used) begin
361 
                data = mem_array[i];
362 
            end
363 
`endif
364 
        end
365 
    endtask
366 
 
367 
    // Burst Decode
368 
    task Burst_Decode;
369 
    begin
370 
 
371 
        // Advance Burst Counter
372 
        if (Burst_counter < burst_length) begin
373 
            Burst_counter = Burst_counter + 1;
374 
        end
375 
 
376 
        // Burst Type
377 
        if (Mode_reg[3] === 1'b0) begin                         // Sequential Burst
378 
            Cols_temp = Cols_addr + 1;
379 
        end else if (Mode_reg[3] === 1'b1) begin                // Interleaved Burst
380 
            Cols_temp[2] =  Burst_counter[2] ^ Cols_brst[2];
381 
            Cols_temp[1] =  Burst_counter[1] ^ Cols_brst[1];
382 
            Cols_temp[0] =  Burst_counter[0] ^ Cols_brst[0];
383 
        end
384 
 
385 
        // Burst Length
386 
        if (burst_length === 2) begin
387 
            Cols_addr [0] = Cols_temp [0];
388 
        end else if (burst_length === 4) begin
389 
            Cols_addr [1 : 0] = Cols_temp [1 : 0];
390 
        end else if (burst_length === 8) begin
391 
            Cols_addr [2 : 0] = Cols_temp [2 : 0];
392 
        end else begin
393 
            Cols_addr = Cols_temp;
394 
        end
395 
 
396 
        // Data Counter
397 
        if (Burst_counter >= burst_length) begin
398 
            Data_in_enable = 1'b0;
399 
            Data_out_enable = 1'b0;
400 
            read_precharge_truncation = 4'h0;
401 
        end
402 
 
403 
    end
404 
    endtask
405 
 
406 
    // Manual Precharge Pipeline
407 
    task Manual_Precharge_Pipeline;
408 
    begin
409 
        // A10 Precharge Pipeline
410 
        A10_precharge[0] = A10_precharge[1];
411 
        A10_precharge[1] = A10_precharge[2];
412 
        A10_precharge[2] = A10_precharge[3];
413 
        A10_precharge[3] = A10_precharge[4];
414 
        A10_precharge[4] = A10_precharge[5];
415 
        A10_precharge[5] = A10_precharge[6];
416 
        A10_precharge[6] = 1'b0;
417 
 
418 
        // Bank Precharge Pipeline
419 
        Bank_precharge[0] = Bank_precharge[1];
420 
        Bank_precharge[1] = Bank_precharge[2];
421 
        Bank_precharge[2] = Bank_precharge[3];
422 
        Bank_precharge[3] = Bank_precharge[4];
423 
        Bank_precharge[4] = Bank_precharge[5];
424 
        Bank_precharge[5] = Bank_precharge[6];
425 
        Bank_precharge[6] = 2'b0;
426 
 
427 
        // Command Precharge Pipeline
428 
        Cmnd_precharge[0] = Cmnd_precharge[1];
429 
        Cmnd_precharge[1] = Cmnd_precharge[2];
430 
        Cmnd_precharge[2] = Cmnd_precharge[3];
431 
        Cmnd_precharge[3] = Cmnd_precharge[4];
432 
        Cmnd_precharge[4] = Cmnd_precharge[5];
433 
        Cmnd_precharge[5] = Cmnd_precharge[6];
434 
        Cmnd_precharge[6] = 1'b0;
435 
 
436 
        // Terminate a Read if same bank or all banks
437 
        if (Cmnd_precharge[0] === 1'b1) begin
438 
            if (Bank_precharge[0] === Bank_addr || A10_precharge[0] === 1'b1) begin
439 
                if (Data_out_enable === 1'b1) begin
440 
                    Data_out_enable = 1'b0;
441 
                    read_precharge_truncation = 4'hF;
442 
                end
443 
            end
444 
        end
445 
    end
446 
    endtask
447 
 
448 
    // Burst Terminate Pipeline
449 
    task Burst_Terminate_Pipeline;
450 
    begin
451 
        // Command Precharge Pipeline
452 
        Cmnd_bst[0] = Cmnd_bst[1];
453 
        Cmnd_bst[1] = Cmnd_bst[2];
454 
        Cmnd_bst[2] = Cmnd_bst[3];
455 
        Cmnd_bst[3] = Cmnd_bst[4];
456 
        Cmnd_bst[4] = Cmnd_bst[5];
457 
        Cmnd_bst[5] = Cmnd_bst[6];
458 
        Cmnd_bst[6] = 1'b0;
459 
 
460 
        // Terminate a Read regardless of banks
461 
        if (Cmnd_bst[0] === 1'b1 && Data_out_enable === 1'b1) begin
462 
            Data_out_enable = 1'b0;
463 
        end
464 
    end
465 
    endtask
466 
 
467 
    // Dq and Dqs Drivers
468 
    task Dq_Dqs_Drivers;
469 
    begin
470 
        // read command pipeline
471 
        Read_cmnd [0] = Read_cmnd [1];
472 
        Read_cmnd [1] = Read_cmnd [2];
473 
        Read_cmnd [2] = Read_cmnd [3];
474 
        Read_cmnd [3] = Read_cmnd [4];
475 
        Read_cmnd [4] = Read_cmnd [5];
476 
        Read_cmnd [5] = Read_cmnd [6];
477 
        Read_cmnd [6] = 1'b0;
478 
 
479 
        // read bank pipeline
480 
        Read_bank [0] = Read_bank [1];
481 
        Read_bank [1] = Read_bank [2];
482 
        Read_bank [2] = Read_bank [3];
483 
        Read_bank [3] = Read_bank [4];
484 
        Read_bank [4] = Read_bank [5];
485 
        Read_bank [5] = Read_bank [6];
486 
        Read_bank [6] = 2'b0;
487 
 
488 
        // read column pipeline
489 
        Read_cols [0] = Read_cols [1];
490 
        Read_cols [1] = Read_cols [2];
491 
        Read_cols [2] = Read_cols [3];
492 
        Read_cols [3] = Read_cols [4];
493 
        Read_cols [4] = Read_cols [5];
494 
        Read_cols [5] = Read_cols [6];
495 
        Read_cols [6] = 0;
496 
 
497 
        // Initialize Read command
498 
        if (Read_cmnd [0] === 1'b1) begin
499 
            Data_out_enable = 1'b1;
500 
            Bank_addr = Read_bank [0];
501 
            Cols_addr = Read_cols [0];
502 
            Cols_brst = Cols_addr [2 : 0];
503 
            Burst_counter = 0;
504 
 
505 
            // Row Address Mux
506 
            case (Bank_addr)
507 
                2'd0    : Rows_addr = B0_row_addr;
508 
                2'd1    : Rows_addr = B1_row_addr;
509 
                2'd2    : Rows_addr = B2_row_addr;
510 
                2'd3    : Rows_addr = B3_row_addr;
511 
                default : $display ("%m: At time %t ERROR: Invalid Bank Address", $time);
512 
            endcase
513 
        end
514 
 
515 
        // Toggle Dqs during Read command
516 
        if (Data_out_enable === 1'b1) begin
517 
            Dqs_int = 1'b0;
518 
            if (Dqs_out === {DQS_BITS{1'b0}}) begin
519 
                Dqs_out = {DQS_BITS{1'b1}};
520 
            end else if (Dqs_out === {DQS_BITS{1'b1}}) begin
521 
                Dqs_out = {DQS_BITS{1'b0}};
522 
            end else begin
523 
                Dqs_out = {DQS_BITS{1'b0}};
524 
            end
525 
        end else if (Data_out_enable === 1'b0 && Dqs_int === 1'b0) begin
526 
            Dqs_out = {DQS_BITS{1'bz}};
527 
        end
528 
 
529 
        // Initialize dqs for Read command
530 
        if (Read_cmnd [2] === 1'b1) begin
531 
            if (Data_out_enable === 1'b0) begin
532 
                Dqs_int = 1'b1;
533 
                Dqs_out = {DQS_BITS{1'b0}};
534 
            end
535 
        end
536 
 
537 
        // Read latch
538 
        if (Data_out_enable === 1'b1) begin
539 
            // output data
540 
            read_mem({Bank_addr, Rows_addr, Cols_addr}, Dq_out);
541 
            if (DEBUG) begin
542 
                $display ("%m: At time %t READ : Bank = %h, Row = %h, Col = %h, Data = %h", $time, Bank_addr, Rows_addr, Cols_addr, Dq_out);
543 
            end
544 
        end else begin
545 
            Dq_out = {DQ_BITS{1'bz}};
546 
        end
547 
    end
548 
    endtask
549 
 
550 
    // Write FIFO and DM Mask Logic
551 
    task Write_FIFO_DM_Mask_Logic;
552 
    begin
553 
        // Write command pipeline
554 
        Write_cmnd [0] = Write_cmnd [1];
555 
        Write_cmnd [1] = Write_cmnd [2];
556 
        Write_cmnd [2] = Write_cmnd [3];
557 
        Write_cmnd [3] = 1'b0;
558 
 
559 
        // Write command pipeline
560 
        Write_bank [0] = Write_bank [1];
561 
        Write_bank [1] = Write_bank [2];
562 
        Write_bank [2] = Write_bank [3];
563 
        Write_bank [3] = 2'b0;
564 
 
565 
        // Write column pipeline
566 
        Write_cols [0] = Write_cols [1];
567 
        Write_cols [1] = Write_cols [2];
568 
        Write_cols [2] = Write_cols [3];
569 
        Write_cols [3] = {COL_BITS{1'b0}};
570 
 
571 
        // Initialize Write command
572 
        if (Write_cmnd [0] === 1'b1) begin
573 
            Data_in_enable = 1'b1;
574 
            Bank_addr = Write_bank [0];
575 
            Cols_addr = Write_cols [0];
576 
            Cols_brst = Cols_addr [2 : 0];
577 
            Burst_counter = 0;
578 
 
579 
            // Row address mux
580 
            case (Bank_addr)
581 
                2'd0    : Rows_addr = B0_row_addr;
582 
                2'd1    : Rows_addr = B1_row_addr;
583 
                2'd2    : Rows_addr = B2_row_addr;
584 
                2'd3    : Rows_addr = B3_row_addr;
585 
                default : $display ("%m: At time %t ERROR: Invalid Row Address", $time);
586 
            endcase
587 
        end
588 
 
589 
        // Write data
590 
        if (Data_in_enable === 1'b1) begin
591 
 
592 
            // Data Buffer
593 
            read_mem({Bank_addr, Rows_addr, Cols_addr}, Dq_buf);
594 
 
595 
            // write negedge Dqs on posedge Sys_clk
596 
            if (Sys_clk) begin
597 
                if (!dm_fall[0]) begin
598 
                    Dq_buf [ 7 : 0] = dq_fall [ 7 : 0];
599 
                end
600 
                if (!dm_fall[1]) begin
601 
                    Dq_buf [15 : 8] = dq_fall [15 : 8];
602 
                end
603 
                if (!dm_fall[2]) begin
604 
                    Dq_buf [23 : 16] = dq_fall [23 : 16];
605 
                end
606 
                if (!dm_fall[3]) begin
607 
                    Dq_buf [31 : 24] = dq_fall [31 : 24];
608 
                end
609 
                if (~&dm_fall) begin
610 
                    if (DEBUG) begin
611 
                        $display ("%m: At time %t WRITE: Bank = %h, Row = %h, Col = %h, Data = %h", $time, Bank_addr, Rows_addr, Cols_addr, Dq_buf[DQ_BITS-1:0]);
612 
                    end
613 
                end
614 
            // write posedge Dqs on negedge Sys_clk
615 
            end else begin
616 
                if (!dm_rise[0]) begin
617 
                    Dq_buf [ 7 : 0] = dq_rise [ 7 : 0];
618 
                end
619 
                if (!dm_rise[1]) begin
620 
                    Dq_buf [15 : 8] = dq_rise [15 : 8];
621 
                end
622 
                if (!dm_rise[2]) begin
623 
                    Dq_buf [23 : 16] = dq_rise [23 : 16];
624 
                end
625 
                if (!dm_rise[3]) begin
626 
                    Dq_buf [31 : 24] = dq_rise [31 : 24];
627 
                end
628 
                if (~&dm_rise) begin
629 
                    if (DEBUG) begin
630 
                        $display ("%m: At time %t WRITE: Bank = %h, Row = %h, Col = %h, Data = %h", $time, Bank_addr, Rows_addr, Cols_addr, Dq_buf[DQ_BITS-1:0]);
631 
                    end
632 
                end
633 
            end
634 
 
635 
            // Write Data
636 
            write_mem({Bank_addr, Rows_addr, Cols_addr}, Dq_buf);
637 
 
638 
            // tWR start and tWTR check
639 
            if (Sys_clk && &dm_pair === 1'b0)  begin
640 
                case (Bank_addr)
641 
                    2'd0    : WR_chk0 = $time;
642 
                    2'd1    : WR_chk1 = $time;
643 
                    2'd2    : WR_chk2 = $time;
644 
                    2'd3    : WR_chk3 = $time;
645 
                    default : $display ("%m: At time %t ERROR: Invalid Bank Address (tWR)", $time);
646 
                endcase
647 
 
648 
                // tWTR check
649 
                if (Read_enable === 1'b1) begin
650 
                    $display ("%m: At time %t ERROR: tWTR violation during Read", $time);
651 
                end
652 
            end
653 
        end
654 
    end
655 
    endtask
656 
 
657 
    // Auto Precharge Calculation
658 
    task Auto_Precharge_Calculation;
659 
    begin
660 
        // Precharge counter
661 
        if (Read_precharge [0] === 1'b1 || Write_precharge [0] === 1'b1) begin
662 
            Count_precharge [0] = Count_precharge [0] + 1;
663 
        end
664 
        if (Read_precharge [1] === 1'b1 || Write_precharge [1] === 1'b1) begin
665 
            Count_precharge [1] = Count_precharge [1] + 1;
666 
        end
667 
        if (Read_precharge [2] === 1'b1 || Write_precharge [2] === 1'b1) begin
668 
            Count_precharge [2] = Count_precharge [2] + 1;
669 
        end
670 
        if (Read_precharge [3] === 1'b1 || Write_precharge [3] === 1'b1) begin
671 
            Count_precharge [3] = Count_precharge [3] + 1;
672 
        end
673 
 
674 
        // Read with AutoPrecharge Calculation
675 
        //      The device start internal precharge when:
676 
        //          1.  Meet tRAS requirement
677 
        //          2.  BL/2 cycles after command
678 
        if ((Read_precharge[0] === 1'b1) && ($time - RAS_chk0 >= tRAS)) begin
679 
            if (Count_precharge[0] >= burst_length/2) begin
680 
                Pc_b0 = 1'b1;
681 
                Act_b0 = 1'b0;
682 
                RP_chk0 = $time;
683 
                Read_precharge[0] = 1'b0;
684 
            end
685 
        end
686 
        if ((Read_precharge[1] === 1'b1) && ($time - RAS_chk1 >= tRAS)) begin
687 
            if (Count_precharge[1] >= burst_length/2) begin
688 
                Pc_b1 = 1'b1;
689 
                Act_b1 = 1'b0;
690 
                RP_chk1 = $time;
691 
                Read_precharge[1] = 1'b0;
692 
            end
693 
        end
694 
        if ((Read_precharge[2] === 1'b1) && ($time - RAS_chk2 >= tRAS)) begin
695 
            if (Count_precharge[2] >= burst_length/2) begin
696 
                Pc_b2 = 1'b1;
697 
                Act_b2 = 1'b0;
698 
                RP_chk2 = $time;
699 
                Read_precharge[2] = 1'b0;
700 
            end
701 
        end
702 
        if ((Read_precharge[3] === 1'b1) && ($time - RAS_chk3 >= tRAS)) begin
703 
            if (Count_precharge[3] >= burst_length/2) begin
704 
                Pc_b3 = 1'b1;
705 
                Act_b3 = 1'b0;
706 
                RP_chk3 = $time;
707 
                Read_precharge[3] = 1'b0;
708 
            end
709 
        end
710 
 
711 
        // Write with AutoPrecharge Calculation
712 
        //      The device start internal precharge when:
713 
        //          1.  Meet tRAS requirement
714 
        //          2.  Write Latency PLUS BL/2 cycles PLUS tWR after Write command
715 
 
716 
        if ((Write_precharge[0] === 1'b1) && ($time - RAS_chk0 >= tRAS)) begin
717 
            if ((Count_precharge[0] >= burst_length/2+1) && ($time - WR_chk0 >= tWR)) begin
718 
                Pc_b0 = 1'b1;
719 
                Act_b0 = 1'b0;
720 
                RP_chk0 = $time;
721 
                Write_precharge[0] = 1'b0;
722 
            end
723 
        end
724 
        if ((Write_precharge[1] === 1'b1) && ($time - RAS_chk1 >= tRAS)) begin
725 
            if ((Count_precharge[1] >= burst_length/2+1) && ($time - WR_chk1 >= tWR)) begin
726 
                Pc_b1 = 1'b1;
727 
                Act_b1 = 1'b0;
728 
                RP_chk1 = $time;
729 
                Write_precharge[1] = 1'b0;
730 
            end
731 
        end
732 
        if ((Write_precharge[2] === 1'b1) && ($time - RAS_chk2 >= tRAS)) begin
733 
            if ((Count_precharge[2] >= burst_length/2+1) && ($time - WR_chk2 >= tWR)) begin
734 
                Pc_b2 = 1'b1;
735 
                Act_b2 = 1'b0;
736 
                RP_chk2 = $time;
737 
                Write_precharge[2] = 1'b0;
738 
            end
739 
        end
740 
        if ((Write_precharge[3] === 1'b1) && ($time - RAS_chk3 >= tRAS)) begin
741 
            if ((Count_precharge[3] >= burst_length/2+1) && ($time - WR_chk3 >= tWR)) begin
742 
                Pc_b3 = 1'b1;
743 
                Act_b3 = 1'b0;
744 
                RP_chk3 = $time;
745 
                Write_precharge[3] = 1'b0;
746 
            end
747 
        end
748 
    end
749 
    endtask
750 
 
751 
    // DLL Counter
752 
    task DLL_Counter;
753 
    begin
754 
        if (DLL_reset === 1'b1 && DLL_done === 1'b0) begin
755 
            DLL_count = DLL_count + 1;
756 
            if (DLL_count >= 200) begin
757 
                DLL_done = 1'b1;
758 
            end
759 
        end
760 
    end
761 
    endtask
762 
 
763 
    // Control Logic
764 
    task Control_Logic;
765 
    begin
766 
        // Auto Refresh
767 
        if (Aref_enable === 1'b1) begin
768 
            // Display DEBUG Message
769 
            if (DEBUG) begin
770 
                $display ("%m: At time %t AREF : Auto Refresh", $time);
771 
            end
772 
 
773 
            // Precharge to Auto Refresh
774 
            if (($time - RP_chk0 < tRP) || ($time - RP_chk1 < tRP) ||
775 
                ($time - RP_chk2 < tRP) || ($time - RP_chk3 < tRP)) begin
776 
                $display ("%m: At time %t ERROR: tRP violation during Auto Refresh", $time);
777 
            end
778 
 
779 
            // LMR/EMR to Auto Refresh
780 
            if ($time - MRD_chk < tMRD) begin
781 
                $display ("%m: At time %t ERROR: tMRD violation during Auto Refresh", $time);
782 
            end
783 
 
784 
            // Auto Refresh to Auto Refresh
785 
            if ($time - RFC_chk < tRFC) begin
786 
                $display ("%m: At time %t ERROR: tRFC violation during Auto Refresh", $time);
787 
            end
788 
 
789 
            // Precharge to Auto Refresh
790 
            if (Pc_b0 === 1'b0 || Pc_b1 === 1'b0 || Pc_b2 === 1'b0 || Pc_b3 === 1'b0) begin
791 
                $display ("%m: At time %t ERROR: All banks must be Precharged before Auto Refresh", $time);
792 
                if (!no_halt) $stop (0);
793 
            end else begin
794 
                aref_count = aref_count + 1;
795 
                RFC_chk = $time;
796 
            end
797 
        end
798 
 
799 
        // Extended Mode Register
800 
        if (Ext_mode_enable === 1'b1) begin
801 
            if (DEBUG) begin
802 
                $display ("%m: At time %t EMR  : Extended Mode Register", $time);
803 
            end
804 
 
805 
            // Precharge to LMR/EMR
806 
            if (($time - RP_chk0 < tRP) || ($time - RP_chk1 < tRP) ||
807 
                ($time - RP_chk2 < tRP) || ($time - RP_chk3 < tRP)) begin
808 
                $display ("%m: At time %t ERROR: tRP violation during Extended Mode Register", $time);
809 
            end
810 
 
811 
            // LMR/EMR to LMR/EMR
812 
            if ($time - MRD_chk < tMRD) begin
813 
                $display ("%m: At time %t ERROR: tMRD violation during Extended Mode Register", $time);
814 
            end
815 
 
816 
            // Auto Refresh to LMR/EMR
817 
            if ($time - RFC_chk < tRFC) begin
818 
                $display ("%m: At time %t ERROR: tRFC violation during Extended Mode Register", $time);
819 
            end
820 
 
821 
            // Precharge to LMR/EMR
822 
            if (Pc_b0 === 1'b0 || Pc_b1 === 1'b0 || Pc_b2 === 1'b0 || Pc_b3 === 1'b0) begin
823 
                $display ("%m: At time %t ERROR: all banks must be Precharged before Extended Mode Register", $time);
824 
                if (!no_halt) $stop (0);
825 
            end else begin
826 
                if (Addr[0] === 1'b0) begin
827 
                    DLL_enable = 1'b1;
828 
                    if (DEBUG) begin
829 
                        $display ("%m: At time %t EMR  : Enable DLL", $time);
830 
                    end
831 
                end else begin
832 
                    DLL_enable = 1'b0;
833 
                    if (DEBUG) begin
834 
                        $display ("%m: At time %t EMR  : Disable DLL", $time);
835 
                    end
836 
                end
837 
                MRD_chk = $time;
838 
            end
839 
        end
840 
 
841 
        // Load Mode Register
842 
        if (Mode_reg_enable === 1'b1) begin
843 
            if (DEBUG) begin
844 
                $display ("%m: At time %t LMR  : Load Mode Register", $time);
845 
            end
846 
 
847 
            // Precharge to LMR/EMR
848 
            if (($time - RP_chk0 < tRP) || ($time - RP_chk1 < tRP) ||
849 
                ($time - RP_chk2 < tRP) || ($time - RP_chk3 < tRP)) begin
850 
                $display ("%m: At time %t ERROR: tRP violation during Load Mode Register", $time);
851 
            end
852 
 
853 
            // LMR/EMR to LMR/EMR
854 
            if ($time - MRD_chk < tMRD) begin
855 
                $display ("%m: At time %t ERROR: tMRD violation during Load Mode Register", $time);
856 
            end
857 
 
858 
            // Auto Refresh to LMR/EMR
859 
            if ($time - RFC_chk < tRFC) begin
860 
                $display ("%m: At time %t ERROR: tRFC violation during Load Mode Register", $time);
861 
            end
862 
 
863 
            // Precharge to LMR/EMR
864 
            if (Pc_b0 === 1'b0 || Pc_b1 === 1'b0 || Pc_b2 === 1'b0 || Pc_b3 === 1'b0) begin
865 
                $display ("%m: At time %t ERROR: all banks must be Precharged before Load Mode Register", $time);
866 
            end else begin
867 
                // Register Mode
868 
                Mode_reg = Addr;
869 
 
870 
                // DLL Reset
871 
                if (DLL_enable === 1'b1 && Addr [8] === 1'b1) begin
872 
                    DLL_reset = 1'b1;
873 
                    DLL_done = 1'b0;
874 
                    DLL_count = 0;
875 
                end else if (DLL_enable === 1'b1 && DLL_reset === 1'b0 && Addr [8] === 1'b0) begin
876 
                    $display ("%m: At time %t ERROR: DLL is ENABLE: DLL RESET is required.", $time);
877 
                end else if (DLL_enable === 1'b0 && Addr [8] === 1'b1) begin
878 
                    $display ("%m: At time %t ERROR: DLL is DISABLE: DLL RESET will be ignored.", $time);
879 
                end
880 
 
881 
                // Burst Length
882 
                case (Addr [2 : 0])
883 
                    3'b001  : $display ("%m: At time %t LMR  : Burst Length = 2", $time);
884 
                    3'b010  : $display ("%m: At time %t LMR  : Burst Length = 4", $time);
885 
                    3'b011  : $display ("%m: At time %t LMR  : Burst Length = 8", $time);
886 
                    default : $display ("%m: At time %t ERROR: Burst Length not supported", $time);
887 
                endcase
888 
 
889 
                // CAS Latency
890 
                case (Addr [6 : 4])
891 
                    3'b010  : $display ("%m: At time %t LMR  : CAS Latency = 2", $time);
892 
                    3'b110  : $display ("%m: At time %t LMR  : CAS Latency = 2.5", $time);
893 
                    3'b011  : $display ("%m: At time %t LMR  : CAS Latency = 3", $time);
894 
                    default : $display ("%m: At time %t ERROR: CAS Latency not supported", $time);
895 
                endcase
896 
 
897 
                // Record current tMRD time
898 
                MRD_chk = $time;
899 
            end
900 
        end
901 
 
902 
        // Activate Block
903 
        if (Active_enable === 1'b1) begin
904 
            if (!(power_up_done)) begin
905 
                $display ("%m: %m: at time %t ERROR: Power Up and Initialization Sequence not completed before executing Activate command", $time);
906 
            end
907 
            // Display DEBUG Message
908 
            if (DEBUG) begin
909 
                $display ("%m: At time %t ACT  : Bank = %h, Row = %h", $time, Ba, Addr);
910 
            end
911 
 
912 
            // Activate to Activate (different bank)
913 
            if ((Prev_bank != Ba) && ($time - RRD_chk < tRRD)) begin
914 
                $display ("%m: At time %t ERROR: tRRD violation during Activate bank %h", $time, Ba);
915 
            end
916 
 
917 
            // LMR/EMR to Activate
918 
            if ($time - MRD_chk < tMRD) begin
919 
                $display ("%m: At time %t ERROR: tMRD violation during Activate bank %h", $time, Ba);
920 
            end
921 
 
922 
            // AutoRefresh to Activate
923 
            if ($time - RFC_chk < tRFC) begin
924 
                $display ("%m: At time %t ERROR: tRFC violation during Activate bank %h", $time, Ba);
925 
            end
926 
 
927 
            // Precharge to Activate
928 
            if ((Ba === 2'b00 && Pc_b0  === 1'b0) || (Ba === 2'b01 && Pc_b1  === 1'b0) ||
929 
                (Ba === 2'b10 && Pc_b2  === 1'b0) || (Ba === 2'b11 && Pc_b3  === 1'b0)) begin
930 
                $display ("%m: At time %t ERROR: Bank = %h is already activated - Command Ignored", $time, Ba);
931 
                if (!no_halt) $stop (0);
932 
            end else begin
933 
                // Activate Bank 0
934 
                if (Ba === 2'b00 && Pc_b0 === 1'b1) begin
935 
                    // Activate to Activate (same bank)
936 
                    if ($time - RC_chk0 < tRC) begin
937 
                        $display ("%m: At time %t ERROR: tRC violation during Activate bank %h", $time, Ba);
938 
                    end
939 
 
940 
                    // Precharge to Activate
941 
                    if ($time - RP_chk0 < tRP) begin
942 
                        $display ("%m: At time %t ERROR: tRP violation during Activate bank %h", $time, Ba);
943 
                    end
944 
 
945 
                    // Record variables for checking violation
946 
                    Act_b0 = 1'b1;
947 
                    Pc_b0 = 1'b0;
948 
                    B0_row_addr = Addr;
949 
                    RC_chk0  = $time;
950 
                    RCD_chk0 = $time;
951 
                    RAS_chk0 = $time;
952 
                    RAP_chk0 = $time;
953 
                end
954 
 
955 
                // Activate Bank 1
956 
                if (Ba === 2'b01 && Pc_b1 === 1'b1) begin
957 
                    // Activate to Activate (same bank)
958 
                    if ($time - RC_chk1 < tRC) begin
959 
                        $display ("%m: At time %t ERROR: tRC violation during Activate bank %h", $time, Ba);
960 
                    end
961 
 
962 
                    // Precharge to Activate
963 
                    if ($time - RP_chk1 < tRP) begin
964 
                        $display ("%m: At time %t ERROR: tRP violation during Activate bank %h", $time, Ba);
965 
                    end
966 
 
967 
                    // Record variables for checking violation
968 
                    Act_b1 = 1'b1;
969 
                    Pc_b1 = 1'b0;
970 
                    B1_row_addr = Addr;
971 
                    RC_chk1  = $time;
972 
                    RCD_chk1 = $time;
973 
                    RAS_chk1 = $time;
974 
                    RAP_chk1 = $time;
975 
                end
976 
 
977 
                // Activate Bank 2
978 
                if (Ba === 2'b10 && Pc_b2 === 1'b1) begin
979 
                    // Activate to Activate (same bank)
980 
                    if ($time - RC_chk2 < tRC) begin
981 
                        $display ("%m: At time %t ERROR: tRC violation during Activate bank %h", $time, Ba);
982 
                    end
983 
 
984 
                    // Precharge to Activate
985 
                    if ($time - RP_chk2 < tRP) begin
986 
                        $display ("%m: At time %t ERROR: tRP violation during Activate bank %h", $time, Ba);
987 
                    end
988 
 
989 
                    // Record variables for checking violation
990 
                    Act_b2 = 1'b1;
991 
                    Pc_b2 = 1'b0;
992 
                    B2_row_addr = Addr;
993 
                    RC_chk2  = $time;
994 
                    RCD_chk2 = $time;
995 
                    RAS_chk2 = $time;
996 
                    RAP_chk2 = $time;
997 
                end
998 
 
999 
                // Activate Bank 3
1000 
                if (Ba === 2'b11 && Pc_b3 === 1'b1) begin
1001 
                    // Activate to Activate (same bank)
1002 
                    if ($time - RC_chk3 < tRC) begin
1003 
                        $display ("%m: At time %t ERROR: tRC violation during Activate bank %h", $time, Ba);
1004 
                    end
1005 
 
1006 
                    // Precharge to Activate
1007 
                    if ($time - RP_chk3 < tRP) begin
1008 
                        $display ("%m: At time %t ERROR: tRP violation during Activate bank %h", $time, Ba);
1009 
                    end
1010 
 
1011 
                    // Record variables for checking violation
1012 
                    Act_b3 = 1'b1;
1013 
                    Pc_b3 = 1'b0;
1014 
                    B3_row_addr = Addr;
1015 
                    RC_chk3  = $time;
1016 
                    RCD_chk3 = $time;
1017 
                    RAS_chk3 = $time;
1018 
                    RAP_chk3 = $time;
1019 
                end
1020 
                // Record variable for checking violation
1021 
                RRD_chk = $time;
1022 
                Prev_bank = Ba;
1023 
                read_precharge_truncation[Ba] = 1'b0;
1024 
            end
1025 
        end
1026 
 
1027 
        // Precharge Block - consider NOP if bank already precharged or in process of precharging
1028 
        if (Prech_enable === 1'b1) begin
1029 
            // Display DEBUG Message
1030 
            if (DEBUG) begin
1031 
                $display ("%m: At time %t PRE  : Addr[10] = %b, Bank = %b", $time, Addr[10], Ba);
1032 
            end
1033 
 
1034 
            // LMR/EMR to Precharge
1035 
            if ($time - MRD_chk < tMRD) begin
1036 
                $display ("%m: At time %t ERROR: tMRD violation during Precharge", $time);
1037 
                if (!no_halt) $stop (0);
1038 
            end
1039 
 
1040 
            // AutoRefresh to Precharge
1041 
            if ($time - RFC_chk < tRFC) begin
1042 
                $display ("%m: At time %t ERROR: tRFC violation during Precharge", $time);
1043 
                if (!no_halt) $stop (0);
1044 
            end
1045 
 
1046 
            // Precharge bank 0
1047 
            if ((Addr[10] === 1'b1 || (Addr[10] === 1'b0 && Ba === 2'b00)) && Act_b0 === 1'b1) begin
1048 
                Act_b0 = 1'b0;
1049 
                Pc_b0 = 1'b1;
1050 
                RP_chk0 = $time;
1051 
 
1052 
                // Activate to Precharge Bank
1053 
                if ($time - RAS_chk0 < tRAS) begin
1054 
                    $display ("%m: At time %t ERROR: tRAS violation during Precharge", $time);
1055 
                    if (!no_halt) $stop (0);
1056 
                end
1057 
 
1058 
                // tWR violation check for Write
1059 
                if ($time - WR_chk0 < tWR) begin
1060 
                    $display ("%m: At time %t ERROR: tWR violation during Precharge", $time);
1061 
                    if (!no_halt) $stop (0);
1062 
                end
1063 
            end
1064 
 
1065 
            // Precharge bank 1
1066 
            if ((Addr[10] === 1'b1 || (Addr[10] === 1'b0 && Ba === 2'b01)) && Act_b1 === 1'b1) begin
1067 
                Act_b1 = 1'b0;
1068 
                Pc_b1 = 1'b1;
1069 
                RP_chk1 = $time;
1070 
 
1071 
                // Activate to Precharge Bank 1
1072 
                if ($time - RAS_chk1 < tRAS) begin
1073 
                    $display ("%m: At time %t ERROR: tRAS violation during Precharge", $time);
1074 
                    if (!no_halt) $stop (0);
1075 
                end
1076 
 
1077 
                // tWR violation check for Write
1078 
                if ($time - WR_chk1 < tWR) begin
1079 
                    $display ("%m: At time %t ERROR: tWR violation during Precharge", $time);
1080 
                    if (!no_halt) $stop (0);
1081 
                end
1082 
            end
1083 
 
1084 
            // Precharge bank 2
1085 
            if ((Addr[10] === 1'b1 || (Addr[10] === 1'b0 && Ba === 2'b10)) && Act_b2 === 1'b1) begin
1086 
                Act_b2 = 1'b0;
1087 
                Pc_b2 = 1'b1;
1088 
                RP_chk2 = $time;
1089 
 
1090 
                // Activate to Precharge Bank 2
1091 
                if ($time - RAS_chk2 < tRAS) begin
1092 
                    $display ("%m: At time %t ERROR: tRAS violation during Precharge", $time);
1093 
                    if (!no_halt) $stop (0);
1094 
                end
1095 
 
1096 
                // tWR violation check for Write
1097 
                if ($time - WR_chk2 < tWR) begin
1098 
                    $display ("%m: At time %t ERROR: tWR violation during Precharge", $time);
1099 
                    if (!no_halt) $stop (0);
1100 
                end
1101 
            end
1102 
 
1103 
            // Precharge bank 3
1104 
            if ((Addr[10] === 1'b1 || (Addr[10] === 1'b0 && Ba === 2'b11)) && Act_b3 === 1'b1) begin
1105 
                Act_b3 = 1'b0;
1106 
                Pc_b3 = 1'b1;
1107 
                RP_chk3 = $time;
1108 
 
1109 
                // Activate to Precharge Bank 3
1110 
                if ($time - RAS_chk3 < tRAS) begin
1111 
                    $display ("%m: At time %t ERROR: tRAS violation during Precharge", $time);
1112 
                    if (!no_halt) $stop (0);
1113 
                end
1114 
 
1115 
                // tWR violation check for Write
1116 
                if ($time - WR_chk3 < tWR) begin
1117 
                    $display ("%m: At time %t ERROR: tWR violation during Precharge", $time);
1118 
                    if (!no_halt) $stop (0);
1119 
                end
1120 
            end
1121 
 
1122 
            // Prech_count is to make sure we have met part of the initialization sequence
1123 
            Prech_count = Prech_count + 1;
1124 
 
1125 
            // Pipeline for READ
1126 
            A10_precharge [cas_latency_x2] = Addr[10];
1127 
            Bank_precharge[cas_latency_x2] = Ba;
1128 
            Cmnd_precharge[cas_latency_x2] = 1'b1;
1129 
        end
1130 
 
1131 
        // Burst terminate
1132 
        if (Burst_term === 1'b1) begin
1133 
            // Display DEBUG Message
1134 
            if (DEBUG) begin
1135 
                $display ("%m: At time %t BST  : Burst Terminate",$time);
1136 
            end
1137 
 
1138 
            if (Data_in_enable === 1'b1) begin
1139 
                // Illegal to burst terminate a Write
1140 
                $display ("%m: At time %t ERROR: It's illegal to burst terminate a Write", $time);
1141 
                if (!no_halt) $stop (0);
1142 
            end else if (Read_precharge[0] === 1'b1 || Read_precharge[1] === 1'b1 ||
1143 
                // Illegal to burst terminate a Read with Auto Precharge
1144 
                Read_precharge[2] === 1'b1 || Read_precharge[3] === 1'b1) begin
1145 
                $display ("%m: At time %t ERROR: It's illegal to burst terminate a Read with Auto Precharge", $time);
1146 
                if (!no_halt) $stop (0);
1147 
            end else begin
1148 
                // Burst Terminate Command Pipeline for Read
1149 
                Cmnd_bst[cas_latency_x2] = 1'b1;
1150 
            end
1151 
 
1152 
        end
1153 
 
1154 
        // Read Command
1155 
        if (Read_enable === 1'b1) begin
1156 
            if (!(power_up_done)) begin
1157 
                $display ("%m: at time %t ERROR: Power Up and Initialization Sequence not completed before executing Read Command", $time);
1158 
            end
1159 
            // Check for DLL reset before Read
1160 
            if (DLL_reset === 1 && DLL_done === 0) begin
1161 
                $display ("%m: at time %t ERROR: You need to wait 200 tCK after DLL Reset Enable to Read, Not %0d clocks.", $time, DLL_count);
1162 
            end
1163 
            // Display DEBUG Message
1164 
            if (DEBUG) begin
1165 
                $display ("%m: At time %t READ : Bank = %h, Col = %h", $time, Ba, {Addr [11], Addr [9 : 0]});
1166 
            end
1167 
 
1168 
            // Terminate a Write
1169 
            if (Data_in_enable === 1'b1) begin
1170 
                Data_in_enable = 1'b0;
1171 
            end
1172 
 
1173 
            // Activate to Read without Auto Precharge
1174 
            if ((Addr [10] === 1'b0 && Ba === 2'b00 && $time - RCD_chk0 < tRCD) ||
1175 
                (Addr [10] === 1'b0 && Ba === 2'b01 && $time - RCD_chk1 < tRCD) ||
1176 
                (Addr [10] === 1'b0 && Ba === 2'b10 && $time - RCD_chk2 < tRCD) ||
1177 
                (Addr [10] === 1'b0 && Ba === 2'b11 && $time - RCD_chk3 < tRCD)) begin
1178 
                $display("%m: At time %t ERROR: tRCD violation during Read", $time);
1179 
            end
1180 
 
1181 
            // Activate to Read with Auto Precharge
1182 
            if ((Addr [10] === 1'b1 && Ba === 2'b00 && $time - RAP_chk0 < tRAP) ||
1183 
                (Addr [10] === 1'b1 && Ba === 2'b01 && $time - RAP_chk1 < tRAP) ||
1184 
                (Addr [10] === 1'b1 && Ba === 2'b10 && $time - RAP_chk2 < tRAP) ||
1185 
                (Addr [10] === 1'b1 && Ba === 2'b11 && $time - RAP_chk3 < tRAP)) begin
1186 
                $display ("%m: At time %t ERROR: tRAP violation during Read", $time);
1187 
            end
1188 
 
1189 
            // Interrupt a Read with Auto Precharge (same bank only)
1190 
            if (Read_precharge [Ba] === 1'b1) begin
1191 
                $display ("%m: At time %t ERROR: It's illegal to interrupt a Read with Auto Precharge", $time);
1192 
                if (!no_halt) $stop (0);
1193 
                // Cancel Auto Precharge
1194 
                if (Addr[10] === 1'b0) begin
1195 
                    Read_precharge [Ba]= 1'b0;
1196 
                end
1197 
            end
1198 
            // Activate to Read
1199 
            if ((Ba === 2'b00 && Pc_b0 === 1'b1) || (Ba === 2'b01 && Pc_b1 === 1'b1) ||
1200 
                (Ba === 2'b10 && Pc_b2 === 1'b1) || (Ba === 2'b11 && Pc_b3 === 1'b1)) begin
1201 
                $display("%m: At time %t ERROR: Bank is not Activated for Read", $time);
1202 
                if (!no_halt) $stop (0);
1203 
            end else begin
1204 
                // CAS Latency pipeline
1205 
                Read_cmnd[cas_latency_x2] = 1'b1;
1206 
                Read_bank[cas_latency_x2] = Ba;
1207 
                Read_cols[cas_latency_x2] = {Addr [ADDR_BITS - 1 : 11], Addr [9 : 0]};
1208 
                // Auto Precharge
1209 
                if (Addr[10] === 1'b1) begin
1210 
                    Read_precharge [Ba]= 1'b1;
1211 
                    Count_precharge [Ba]= 0;
1212 
                end
1213 
            end
1214 
        end
1215 
 
1216 
        // Write Command
1217 
        if (Write_enable === 1'b1) begin
1218 
            if (!(power_up_done)) begin
1219 
                $display ("%m: at time %t ERROR: Power Up and Initialization Sequence not completed before executing Write Command", $time);
1220 
                if (!no_halt) $stop (0);
1221 
            end
1222 
            // display DEBUG message
1223 
            if (DEBUG) begin
1224 
                $display ("At time %t WRITE: Bank = %h, Col = %h", $time, Ba, {Addr [ADDR_BITS - 1 : 11], Addr [9 : 0]});
1225 
            end
1226 
 
1227 
            // Activate to Write
1228 
            if ((Ba === 2'b00 && $time - RCD_chk0 < tRCD) ||
1229 
                (Ba === 2'b01 && $time - RCD_chk1 < tRCD) ||
1230 
                (Ba === 2'b10 && $time - RCD_chk2 < tRCD) ||
1231 
                (Ba === 2'b11 && $time - RCD_chk3 < tRCD)) begin
1232 
                $display("%m: At time %t ERROR: tRCD violation during Write to Bank %h", $time, Ba);
1233 
            end
1234 
 
1235 
            // Read to Write
1236 
            if (Read_cmnd[0] || Read_cmnd[1] || Read_cmnd[2] || Read_cmnd[3] ||
1237 
                Read_cmnd[4] || Read_cmnd[5] || Read_cmnd[6] || (Burst_counter < burst_length)) begin
1238 
                if (Data_out_enable || read_precharge_truncation[Ba]) begin
1239 
                    $display("%m: At time %t ERROR: Read to Write violation", $time);
1240 
                end
1241 
            end
1242 
 
1243 
            // Interrupt a Write with Auto Precharge (same bank only)
1244 
            if (Write_precharge [Ba] === 1'b1) begin
1245 
                $display ("At time %t ERROR: it's illegal to interrupt a Write with Auto Precharge", $time);
1246 
                if (!no_halt) $stop (0);
1247 
                // Cancel Auto Precharge
1248 
                if (Addr[10] === 1'b0) begin
1249 
                    Write_precharge [Ba]= 1'b0;
1250 
                end
1251 
            end
1252 
            // Activate to Write
1253 
            if ((Ba === 2'b00 && Pc_b0 === 1'b1) || (Ba === 2'b01 && Pc_b1 === 1'b1) ||
1254 
                (Ba === 2'b10 && Pc_b2 === 1'b1) || (Ba === 2'b11 && Pc_b3 === 1'b1)) begin
1255 
                $display("%m: At time %t ERROR: Bank is not Activated for Write", $time);
1256 
                if (!no_halt) $stop (0);
1257 
            end else begin
1258 
                // Pipeline for Write
1259 
                Write_cmnd [3] = 1'b1;
1260 
                Write_bank [3] = Ba;
1261 
                Write_cols [3] = {Addr [ADDR_BITS - 1 : 11], Addr [9 : 0]};
1262 
                // Auto Precharge
1263 
                if (Addr[10] === 1'b1) begin
1264 
                    Write_precharge [Ba]= 1'b1;
1265 
                    Count_precharge [Ba]= 0;
1266 
                end
1267 
            end
1268 
        end
1269 
    end
1270 
    endtask
1271 
 
1272 
    task check_neg_dqs;
1273 
    begin
1274 
        if (Write_cmnd[2] || Write_cmnd[1] || Data_in_enable) begin
1275 
            for (i=0; i<DQS_BITS; i=i+1) begin
1276 
                if (expect_neg_dqs[i]) begin
1277 
                    $display ("%m: At time %t ERROR: Negative DQS[%d] transition required.", $time, i);
1278 
                end
1279 
                expect_neg_dqs[i] = 1'b1;
1280 
            end
1281 
        end else begin
1282 
            expect_pos_dqs = 0;
1283 
            expect_neg_dqs = 0;
1284 
        end
1285 
    end
1286 
    endtask
1287 
 
1288 
    task check_pos_dqs;
1289 
    begin
1290 
        if (Write_cmnd[2] || Write_cmnd[1] || Data_in_enable) begin
1291 
            for (i=0; i<DQS_BITS; i=i+1) begin
1292 
                if (expect_pos_dqs[i]) begin
1293 
                    $display ("%m: At time %t ERROR: Positive DQS[%d] transition required.", $time, i);
1294 
                end
1295 
                expect_pos_dqs[i] = 1'b1;
1296 
            end
1297 
        end else begin
1298 
            expect_pos_dqs = 0;
1299 
            expect_neg_dqs = 0;
1300 
        end
1301 
    end
1302 
    endtask
1303 
 
1304 
    // Main Logic
1305 
    always @ (posedge Sys_clk) begin
1306 
        Manual_Precharge_Pipeline;
1307 
        Burst_Terminate_Pipeline;
1308 
        Dq_Dqs_Drivers;
1309 
        Write_FIFO_DM_Mask_Logic;
1310 
        Burst_Decode;
1311 
        check_neg_dqs;
1312 
        Auto_Precharge_Calculation;
1313 
        DLL_Counter;
1314 
        Control_Logic;
1315 
    end
1316 
 
1317 
    always @ (negedge Sys_clk) begin
1318 
        Manual_Precharge_Pipeline;
1319 
        Burst_Terminate_Pipeline;
1320 
        Dq_Dqs_Drivers;
1321 
        Write_FIFO_DM_Mask_Logic;
1322 
        Burst_Decode;
1323 
        check_pos_dqs;
1324 
    end
1325 
 
1326 
    // Dqs Receiver
1327 
    always @ (posedge Dqs_in[0]) begin
1328 
        // Latch data at posedge Dqs
1329 
        dq_rise[7 : 0] = Dq_in[7 : 0];
1330 
        dm_rise[0] = Dm_in[0];
1331 
        expect_pos_dqs[0] = 0;
1332 
    end
1333 
 
1334 
    always @ (posedge Dqs_in[1]) begin
1335 
        // Latch data at posedge Dqs
1336 
        dq_rise[15 : 8] = Dq_in[15 : 8];
1337 
        dm_rise[1] = Dm_in [1];
1338 
        expect_pos_dqs[1] = 0;
1339 
    end
1340 
 
1341 
    always @ (posedge Dqs_in[2]) begin
1342 
        // Latch data at posedge Dqs
1343 
        dq_rise[23 : 16] = Dq_in[23 : 16];
1344 
        dm_rise[2] = Dm_in [2];
1345 
        expect_pos_dqs[2] = 0;
1346 
    end
1347 
 
1348 
    always @ (posedge Dqs_in[3]) begin
1349 
        // Latch data at posedge Dqs
1350 
        dq_rise[31 : 24] = Dq_in[31 : 24];
1351 
        dm_rise[3] = Dm_in [3];
1352 
        expect_pos_dqs[3] = 0;
1353 
    end
1354 
 
1355 
    always @ (negedge Dqs_in[0]) begin
1356 
        // Latch data at negedge Dqs
1357 
        dq_fall[7 : 0] = Dq_in[7 : 0];
1358 
        dm_fall[0] = Dm_in[0];
1359 
        dm_pair[1:0]  = {dm_rise[0], dm_fall[0]};
1360 
        expect_neg_dqs[0] = 0;
1361 
    end
1362 
 
1363 
    always @ (negedge Dqs_in[1]) begin
1364 
        // Latch data at negedge Dqs
1365 
        dq_fall[15: 8] = Dq_in[15 : 8];
1366 
        dm_fall[1] = Dm_in[1];
1367 
        dm_pair[3:2]  = {dm_rise[1], dm_fall[1]};
1368 
        expect_neg_dqs[1] = 0;
1369 
    end
1370 
 
1371 
    always @ (negedge Dqs_in[2]) begin
1372 
        // Latch data at negedge Dqs
1373 
        dq_fall[23: 16] = Dq_in[23 : 16];
1374 
        dm_fall[2] = Dm_in[2];
1375 
        dm_pair[5:4]  = {dm_rise[2], dm_fall[2]};
1376 
        expect_neg_dqs[2] = 0;
1377 
    end
1378 
 
1379 
    always @ (negedge Dqs_in[3]) begin
1380 
        // Latch data at negedge Dqs
1381 
        dq_fall[31: 24] = Dq_in[31 : 24];
1382 
        dm_fall[3] = Dm_in[3];
1383 
        dm_pair[7:6]  = {dm_rise[3], dm_fall[3]};
1384 
        expect_neg_dqs[3] = 0;
1385 
    end
1386 
 
1387 
    specify
1388 
                                              // SYMBOL UNITS DESCRIPTION
1389 
                                              // ------ ----- -----------
1390 
`ifdef sg5B                                   //              specparams for -5B (CL = 3)
1391 
        specparam tDSS             =     1.0; // tDSS   ns    DQS falling edge to CLK rising (setup time) = 0.2*tCK
1392 
        specparam tDSH             =     1.0; // tDSH   ns    DQS falling edge from CLK rising (hold time) = 0.2*tCK
1393 
        specparam tIH              =   0.750; // tIH    ns    Input Hold Time
1394 
        specparam tIS              =   0.750; // tIS    ns    Input Setup Time
1395 
        specparam tDQSH            =    1.75; // tDQSH  ns    DQS input High Pulse Width = 0.35*tCK
1396 
        specparam tDQSL            =    1.75; // tDQSL  ns    DQS input Low Pulse Width = 0.35*tCK
1397 
`endif
1398 
`ifdef sg6                              //              specparams for -6 (CL = 2.5)
1399 
        specparam tDSS             =     1.2; // tDSS   ns    DQS falling edge to CLK rising (setup time) = 0.2*tCK
1400 
        specparam tDSH             =     1.2; // tDSH   ns    DQS falling edge from CLK rising (hold time) = 0.2*tCK
1401 
        specparam tIH              =   0.750; // tIH    ns    Input Hold Time
1402 
        specparam tIS              =   0.750; // tIS    ns    Input Setup Time
1403 
        specparam tDQSH            =     2.1; // tDQSH  ns    DQS input High Pulse Width = 0.35*tCK
1404 
        specparam tDQSL            =     2.1; // tDQSL  ns    DQS input Low Pulse Width = 0.35*tCK
1405 
`endif
1406 
`ifdef sg6T                             //              specparams for -6 (CL = 2.5)
1407 
        specparam tDSS             =     1.2; // tDSS   ns    DQS falling edge to CLK rising (setup time) = 0.2*tCK
1408 
        specparam tDSH             =     1.2; // tDSH   ns    DQS falling edge from CLK rising (hold time) = 0.2*tCK
1409 
        specparam tIH              =   0.750; // tIH    ns    Input Hold Time
1410 
        specparam tIS              =   0.750; // tIS    ns    Input Setup Time
1411 
        specparam tDQSH            =     2.1; // tDQSH  ns    DQS input High Pulse Width = 0.35*tCK
1412 
        specparam tDQSL            =     2.1; // tDQSL  ns    DQS input Low Pulse Width = 0.35*tCK
1413 
`endif
1414 
`ifdef sg75                             //              specparams for -75E (CL = 2)
1415 
        specparam tDSS             =     1.5; // tDSS   ns    DQS falling edge to CLK rising (setup time) = 0.2*tCK
1416 
        specparam tDSH             =     1.5; // tDSH   ns    DQS falling edge from CLK rising (hold time) = 0.2*tCK
1417 
        specparam tIH              =   0.900; // tIH    ns    Input Hold Time
1418 
        specparam tIS              =   0.900; // tIS    ns    Input Setup Time
1419 
        specparam tDQSH            =   2.625; // tDQSH  ns    DQS input High Pulse Width = 0.35*tCK
1420 
        specparam tDQSL            =   2.625; // tDQSL  ns    DQS input Low Pulse Width = 0.35*tCK
1421 
`endif
1422 
`ifdef sg75E                            //              specparams for -75E (CL = 2)
1423 
        specparam tDSS             =     1.5; // tDSS   ns    DQS falling edge to CLK rising (setup time) = 0.2*tCK
1424 
        specparam tDSH             =     1.5; // tDSH   ns    DQS falling edge from CLK rising (hold time) = 0.2*tCK
1425 
        specparam tIH              =   0.900; // tIH    ns    Input Hold Time
1426 
        specparam tIS              =   0.900; // tIS    ns    Input Setup Time
1427 
        specparam tDQSH            =   2.625; // tDQSH  ns    DQS input High Pulse Width = 0.35*tCK
1428 
        specparam tDQSL            =   2.625; // tDQSL  ns    DQS input Low Pulse Width = 0.35*tCK
1429 
`endif
1430 
`ifdef sg75Z                            //              specparams for -75Z (CL = 2)
1431 
        specparam tDSS             =     1.5; // tDSS   ns    DQS falling edge to CLK rising (setup time) = 0.2*tCK
1432 
        specparam tDSH             =     1.5; // tDSH   ns    DQS falling edge from CLK rising (hold time) = 0.2*tCK
1433 
        specparam tIH              =   0.900; // tIH    ns    Input Hold Time
1434 
        specparam tIS              =   0.900; // tIS    ns    Input Setup Time
1435 
        specparam tDQSH            =   2.625; // tDQSH  ns    DQS input High Pulse Width = 0.35*tCK
1436 
        specparam tDQSL            =   2.625; // tDQSL  ns    DQS input Low Pulse Width = 0.35*tCK
1437 
`endif
1438 
        $width    (posedge Dqs_in[0] &&& wdqs_valid, tDQSH);
1439 
        $width    (posedge Dqs_in[1] &&& wdqs_valid, tDQSH);
1440 
        $width    (negedge Dqs_in[0] &&& wdqs_valid, tDQSL);
1441 
        $width    (negedge Dqs_in[1] &&& wdqs_valid, tDQSL);
1442 
        $setuphold(posedge Clk,   Cke,   tIS, tIH);
1443 
        $setuphold(posedge Clk,   Cs_n,  tIS, tIH);
1444 
        $setuphold(posedge Clk,   Cas_n, tIS, tIH);
1445 
        $setuphold(posedge Clk,   Ras_n, tIS, tIH);
1446 
        $setuphold(posedge Clk,   We_n,  tIS, tIH);
1447 
        $setuphold(posedge Clk,   Addr,  tIS, tIH);
1448 
        $setuphold(posedge Clk,   Ba,    tIS, tIH);
1449 
        $setuphold(posedge Clk, negedge Dqs &&& wdqs_valid, tDSS, tDSH);
1450 
    endspecify
1451 
 
1452 
endmodule

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