OpenCores
URL https://opencores.org/ocsvn/hpdmc/hpdmc/trunk

Subversion Repositories hpdmc

[/] [hpdmc/] [trunk/] [hpdmc_ddr32/] [test/] [ddr_parameters.vh] - Blame information for rev 21

Details | Compare with Previous | View Log

Line No. Rev Author Line
1 21 lekernel 
/****************************************************************************************
2 
*
3 
*   Disclaimer   This software code and all associated documentation, comments or other
4 
*  of Warranty:  information (collectively "Software") is provided "AS IS" without
5 
*                warranty of any kind. MICRON TECHNOLOGY, INC. ("MTI") EXPRESSLY
6 
*                DISCLAIMS ALL WARRANTIES EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED
7 
*                TO, NONINFRINGEMENT OF THIRD PARTY RIGHTS, AND ANY IMPLIED WARRANTIES
8 
*                OF MERCHANTABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE. MTI DOES NOT
9 
*                WARRANT THAT THE SOFTWARE WILL MEET YOUR REQUIREMENTS, OR THAT THE
10 
*                OPERATION OF THE SOFTWARE WILL BE UNINTERRUPTED OR ERROR-FREE.
11 
*                FURTHERMORE, MTI DOES NOT MAKE ANY REPRESENTATIONS REGARDING THE USE OR
12 
*                THE RESULTS OF THE USE OF THE SOFTWARE IN TERMS OF ITS CORRECTNESS,
13 
*                ACCURACY, RELIABILITY, OR OTHERWISE. THE ENTIRE RISK ARISING OUT OF USE
14 
*                OR PERFORMANCE OF THE SOFTWARE REMAINS WITH YOU. IN NO EVENT SHALL MTI,
15 
*                ITS AFFILIATED COMPANIES OR THEIR SUPPLIERS BE LIABLE FOR ANY DIRECT,
16 
*                INDIRECT, CONSEQUENTIAL, INCIDENTAL, OR SPECIAL DAMAGES (INCLUDING,
17 
*                WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS INTERRUPTION,
18 
*                OR LOSS OF INFORMATION) ARISING OUT OF YOUR USE OF OR INABILITY TO USE
19 
*                THE SOFTWARE, EVEN IF MTI HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH
20 
*                DAMAGES. Because some jurisdictions prohibit the exclusion or
21 
*                limitation of liability for consequential or incidental damages, the
22 
*                above limitation may not apply to you.
23 
*
24 
*                Copyright 2003 Micron Technology, Inc. All rights reserved.
25 
*
26 
****************************************************************************************/
27 
 
28 
`define sg75E
29 
`define x16
30 
 
31 
    // Timing parameters based on Speed Grade 04/07
32 
                                          // SYMBOL UNITS DESCRIPTION
33 
                                          // ------ ----- -----------
34 
`ifdef sg5B                               //              Timing Parameters for -5B (CL = 3)
35 
    parameter tCK              =     5.0; // tCK    ns    Nominal Clock Cycle Time
36 
    parameter tDQSQ            =     0.4; // tDQSQ  ns    DQS-DQ skew, DQS to last DQ valid, per group, per access
37 
    parameter tMRD             =    10.0; // tMRD   ns    Load Mode Register command cycle time
38 
    parameter tRAP             =    15.0; // tRAP   ns    ACTIVE to READ with Auto precharge command
39 
    parameter tRAS             =    40.0; // tRAS   ns    Active to Precharge command time
40 
    parameter tRC              =    55.0; // tRC    ns    Active to Active/Auto Refresh command time
41 
    parameter tRFC             =    70.0; // tRFC   ns    Refresh to Refresh Command interval time
42 
    parameter tRCD             =    15.0; // tRCD   ns    Active to Read/Write command time
43 
    parameter tRP              =    15.0; // tRP    ns    Precharge command period
44 
    parameter tRRD             =    10.0; // tRRD   ns    Active bank a to Active bank b command time
45 
    parameter tWR              =    15.0; // tWR    ns    Write recovery time
46 
`endif
47 
`ifdef sg6T                         //              Timing Parameters for -6T (CL = 2.5)
48 
    parameter tCK              =     6.0; // tCK    ns    Nominal Clock Cycle Time
49 
    parameter tDQSQ            =    0.45; // tDQSQ  ns    DQS-DQ skew, DQS to last DQ valid, per group, per access
50 
    parameter tMRD             =    12.0; // tMRD   ns    Load Mode Register command cycle time
51 
    parameter tRAP             =    15.0; // tRAP   ns    ACTIVE to READ with Auto precharge command
52 
    parameter tRAS             =    42.0; // tRAS   ns    Active to Precharge command time
53 
    parameter tRC              =    60.0; // tRC    ns    Active to Active/Auto Refresh command time
54 
    parameter tRFC             =    72.0; // tRFC   ns    Refresh to Refresh Command interval time
55 
    parameter tRCD             =    15.0; // tRCD   ns    Active to Read/Write command time
56 
    parameter tRP              =    15.0; // tRP    ns    Precharge command period
57 
    parameter tRRD             =    12.0; // tRRD   ns    Active bank a to Active bank b command time
58 
    parameter tWR              =    15.0; // tWR    ns    Write recovery time
59 
`endif
60 
`ifdef sg6                          //              Timing Parameters for -6 (CL = 2.5)
61 
    parameter tCK              =     6.0; // tCK    ns    Nominal Clock Cycle Time
62 
    parameter tDQSQ            =     0.4; // tDQSQ  ns    DQS-DQ skew, DQS to last DQ valid, per group, per access
63 
    parameter tMRD             =    12.0; // tMRD   ns    Load Mode Register command cycle time
64 
    parameter tRAP             =    15.0; // tRAP   ns    ACTIVE to READ with Auto precharge command
65 
    parameter tRAS             =    42.0; // tRAS   ns    Active to Precharge command time
66 
    parameter tRC              =    60.0; // tRC    ns    Active to Active/Auto Refresh command time
67 
    parameter tRFC             =    72.0; // tRFC   ns    Refresh to Refresh Command interval time
68 
    parameter tRCD             =    15.0; // tRCD   ns    Active to Read/Write command time
69 
    parameter tRP              =    15.0; // tRP    ns    Precharge command period
70 
    parameter tRRD             =    12.0; // tRRD   ns    Active bank a to Active bank b command time
71 
    parameter tWR              =    15.0; // tWR    ns    Write recovery time
72 
`endif
73 
`ifdef sg75E                        //              Timing Parameters for -75E (CL = 2)
74 
    parameter tCK              =     7.5; // tCK    ns    Nominal Clock Cycle Time
75 
    parameter tDQSQ            =     0.5; // tDQSQ  ns    DQS-DQ skew, DQS to last DQ valid, per group, per access
76 
    parameter tMRD             =    15.0; // tMRD   ns    Load Mode Register command cycle time
77 
    parameter tRAP             =    15.0; // tRAP   ns    ACTIVE to READ with Auto precharge command
78 
    parameter tRAS             =    40.0; // tRAS   ns    Active to Precharge command time
79 
    parameter tRC              =    60.0; // tRC    ns    Active to Active/Auto Refresh command time
80 
    parameter tRFC             =    75.0; // tRFC   ns    Refresh to Refresh Command interval time
81 
    parameter tRCD             =    15.0; // tRCD   ns    Active to Read/Write command time
82 
    parameter tRP              =    15.0; // tRP    ns    Precharge command period
83 
    parameter tRRD             =    15.0; // tRRD   ns    Active bank a to Active bank b command time
84 
    parameter tWR              =    15.0; // tWR    ns    Write recovery time
85 
`endif
86 
`ifdef sg75Z                        //              Timing Parameters for -75Z (CL = 2)
87 
    parameter tCK              =     7.5; // tCK    ns    Nominal Clock Cycle Time
88 
    parameter tDQSQ            =     0.5; // tDQSQ  ns    DQS-DQ skew, DQS to last DQ valid, per group, per access
89 
    parameter tMRD             =    15.0; // tMRD   ns    Load Mode Register command cycle time
90 
    parameter tRAP             =    20.0; // tRAP   ns    ACTIVE to READ with Auto precharge command
91 
    parameter tRAS             =    40.0; // tRAS   ns    Active to Precharge command time
92 
    parameter tRC              =    65.0; // tRC    ns    Active to Active/Auto Refresh command time
93 
    parameter tRFC             =    75.0; // tRFC   ns    Refresh to Refresh Command interval time
94 
    parameter tRCD             =    20.0; // tRCD   ns    Active to Read/Write command time
95 
    parameter tRP              =    20.0; // tRP    ns    Precharge command period
96 
    parameter tRRD             =    15.0; // tRRD   ns    Active bank a to Active bank b command time
97 
    parameter tWR              =    15.0; // tWR    ns    Write recovery time
98 
`endif
99 
`ifdef sg75                        //              Timing Parameters for -75 (CL = 2.5)
100 
    parameter tCK              =     7.5; // tCK    ns    Nominal Clock Cycle Time
101 
    parameter tDQSQ            =     0.5; // tDQSQ  ns    DQS-DQ skew, DQS to last DQ valid, per group, per access
102 
    parameter tMRD             =    15.0; // tMRD   ns    Load Mode Register command cycle time
103 
    parameter tRAP             =    20.0; // tRAP   ns    ACTIVE to READ with Auto precharge command
104 
    parameter tRAS             =    40.0; // tRAS   ns    Active to Precharge command time
105 
    parameter tRC              =    65.0; // tRC    ns    Active to Active/Auto Refresh command time
106 
    parameter tRFC             =    75.0; // tRFC   ns    Refresh to Refresh Command interval time
107 
    parameter tRCD             =    20.0; // tRCD   ns    Active to Read/Write command time
108 
    parameter tRP              =    20.0; // tRP    ns    Precharge command period
109 
    parameter tRRD             =    15.0; // tRRD   ns    Active bank a to Active bank b command time
110 
    parameter tWR              =    15.0; // tWR    ns    Write recovery time
111 
`endif
112 
 
113 
    // Size Parameters based on Part Width
114 
 
115 
`ifdef x4
116 
    parameter ADDR_BITS        =      13; // Set this parameter to control how many Address bits are used
117 
    parameter DQ_BITS          =       4; // Set this parameter to control how many Data bits are used
118 
    parameter DQS_BITS         =       1; // Set this parameter to control how many DQS bits are used
119 
    parameter DM_BITS          =       1; // Set this parameter to control how many DM bits are used
120 
    parameter COL_BITS         =      11; // Set this parameter to control how many Column bits are used
121 
`endif
122 
`ifdef x8
123 
    parameter ADDR_BITS        =      13; // Set this parameter to control how many Address bits are used
124 
    parameter DQ_BITS          =       8; // Set this parameter to control how many Data bits are used
125 
    parameter DQS_BITS         =       1; // Set this parameter to control how many DQS bits are used
126 
    parameter DM_BITS          =       1; // Set this parameter to control how many DM bits are used
127 
    parameter COL_BITS         =      10; // Set this parameter to control how many Column bits are used
128 
`endif
129 
`ifdef x16
130 
    parameter ADDR_BITS        =      13; // Set this parameter to control how many Address bits are used
131 
    parameter DQ_BITS          =      16; // Set this parameter to control how many Data bits are used
132 
    parameter DQS_BITS         =       2; // Set this parameter to control how many DQS bits are used
133 
    parameter DM_BITS          =       2; // Set this parameter to control how many DM bits are used
134 
    parameter COL_BITS         =       9; // Set this parameter to control how many Column bits are used
135 
`endif
136 
 
137 
    parameter BA_BITS          =       2; // Set this parmaeter to control how many Bank Address bits are used
138 
    parameter full_mem_bits    = BA_BITS+ADDR_BITS+COL_BITS; // Set this parameter to control how many unique addresses are used
139 
    parameter part_mem_bits    = 10;                   // Set this parameter to control how many unique addresses are used
140 
 
141 
    parameter no_halt          =       0; // If set to 1, the model won't halt on command sequence/major errors
142 
    parameter DEBUG            =       1; // Turn on DEBUG message
143 
`define FULL_MEM

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.