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[/] [hpdmc/] [trunk/] [hpdmc_ddr32/] [test/] [iddr.v] - Blame information for rev 21

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1 21 lekernel 
///////////////////////////////////////////////////////////////////////////////
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// Copyright (c) 1995/2005 Xilinx, Inc.
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// All Right Reserved.
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///////////////////////////////////////////////////////////////////////////////
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// Modified for HPDMC simulation, based on Xilinx 05/29/07 revision
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///////////////////////////////////////////////////////////////////////////////
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module IDDR #(
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        parameter DDR_CLK_EDGE = "OPPOSITE_EDGE",
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        parameter INIT_Q1 = 1'b0,
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        parameter INIT_Q2 = 1'b0,
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        parameter SRTYPE = "SYNC"
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) (
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        output Q1,
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        output Q2,
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        input C,
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        input CE,
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        input D,
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        input R,
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        input S
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);
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reg q1_out = INIT_Q1, q2_out = INIT_Q2;
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reg q1_out_int, q2_out_int;
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reg q1_out_pipelined, q2_out_same_edge_int;
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wire c_in;
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wire ce_in;
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wire d_in;
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wire gsr_in;
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wire r_in;
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wire s_in;
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buf buf_c(c_in, C);
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buf buf_ce(ce_in, CE);
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buf buf_d(d_in, D);
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buf buf_q1(Q1, q1_out);
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buf buf_q2(Q2, q2_out);
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buf buf_r(r_in, R);
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buf buf_s(s_in, S);
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initial begin
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        if((INIT_Q1 != 0) && (INIT_Q1 != 1)) begin
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                $display("Attribute Syntax Error : The attribute INIT_Q1 on IDDR instance %m is set to %d.  Legal values for this attribute are 0 or 1.", INIT_Q1);
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                $finish;
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        end
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        if((INIT_Q2 != 0) && (INIT_Q2 != 1)) begin
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                $display("Attribute Syntax Error : The attribute INIT_Q1 on IDDR instance %m is set to %d.  Legal values for this attribute are 0 or 1.", INIT_Q2);
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                $finish;
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        end
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        if((DDR_CLK_EDGE != "OPPOSITE_EDGE") && (DDR_CLK_EDGE != "SAME_EDGE") && (DDR_CLK_EDGE != "SAME_EDGE_PIPELINED")) begin
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                $display("Attribute Syntax Error : The attribute DDR_CLK_EDGE on IDDR instance %m is set to %s.  Legal values for this attribute are OPPOSITE_EDGE, SAME_EDGE or SAME_EDGE_PIPELINED.", DDR_CLK_EDGE);
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                $finish;
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        end
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        if((SRTYPE != "ASYNC") && (SRTYPE != "SYNC")) begin
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                $display("Attribute Syntax Error : The attribute SRTYPE on IDDR instance %m is set to %s.  Legal values for this attribute are ASYNC or SYNC.", SRTYPE);
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                $finish;
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        end
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end
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always @(r_in, s_in) begin
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        if(r_in == 1'b1 && SRTYPE == "ASYNC") begin
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                assign q1_out_int = 1'b0;
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                assign q1_out_pipelined = 1'b0;
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                assign q2_out_same_edge_int = 1'b0;
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                assign q2_out_int = 1'b0;
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        end else if(r_in == 1'b0 && s_in == 1'b1 && SRTYPE == "ASYNC") begin
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                assign q1_out_int = 1'b1;
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                assign q1_out_pipelined = 1'b1;
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                assign q2_out_same_edge_int = 1'b1;
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                assign q2_out_int = 1'b1;
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        end else if((r_in == 1'b1 || s_in == 1'b1) && SRTYPE == "SYNC") begin
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                deassign q1_out_int;
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                deassign q1_out_pipelined;
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                deassign q2_out_same_edge_int;
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                deassign q2_out_int;
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        end else if(r_in == 1'b0 && s_in == 1'b0) begin
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                deassign q1_out_int;
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                deassign q1_out_pipelined;
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                deassign q2_out_same_edge_int;
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                deassign q2_out_int;
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        end
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end
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always @(posedge c_in) begin
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        if(r_in == 1'b1) begin
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                q1_out_int <= 1'b0;
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                q1_out_pipelined <= 1'b0;
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                q2_out_same_edge_int <= 1'b0;
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        end else if(r_in == 1'b0 && s_in == 1'b1) begin
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                q1_out_int <= 1'b1;
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                q1_out_pipelined <= 1'b1;
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                q2_out_same_edge_int <= 1'b1;
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        end else if(ce_in == 1'b1 && r_in == 1'b0 && s_in == 1'b0) begin
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                q1_out_int <= d_in;
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                q1_out_pipelined <= q1_out_int;
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                q2_out_same_edge_int <= q2_out_int;
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        end
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end
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always @(negedge c_in) begin
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        if(r_in == 1'b1)
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                q2_out_int <= 1'b0;
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        else if(r_in == 1'b0 && s_in == 1'b1)
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                q2_out_int <= 1'b1;
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        else if(ce_in == 1'b1 && r_in == 1'b0 && s_in == 1'b0)
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                q2_out_int <= d_in;
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end
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always @(c_in, q1_out_int, q2_out_int, q2_out_same_edge_int, q1_out_pipelined) begin
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        case(DDR_CLK_EDGE)
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                "OPPOSITE_EDGE" : begin
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                        q1_out <= q1_out_int;
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                        q2_out <= q2_out_int;
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                end
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                "SAME_EDGE" : begin
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                        q1_out <= q1_out_int;
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                        q2_out <= q2_out_same_edge_int;
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                end
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                "SAME_EDGE_PIPELINED" : begin
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                        q1_out <= q1_out_pipelined;
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                        q2_out <= q2_out_same_edge_int;
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                end
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                default: begin
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                        $display("Attribute Syntax Error : The attribute DDR_CLK_EDGE on IDDR instance %m is set to %s.  Legal values for this attribute are OPPOSITE_EDGE, SAME_EDGE or SAME_EDGE_PIPELINED.", DDR_CLK_EDGE);
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                        $finish;
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                end
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        endcase
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end
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endmodule

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