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[/] [hpdmc/] [trunk/] [hpdmc_ddr32/] [test/] [iddr2.v] - Blame information for rev 21

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1 21 lekernel 
///////////////////////////////////////////////////////////////////////////////
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// Copyright (c) 1995/2004 Xilinx, Inc.
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// All Right Reserved.
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///////////////////////////////////////////////////////////////////////////////
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// Modified for HPDMC simulation, based on Xilinx 04/08/09 revision
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///////////////////////////////////////////////////////////////////////////////
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`timescale  1 ps / 1 ps
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module IDDR2 (Q0, Q1, C0, C1, CE, D, R, S);
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    output Q0;
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    output Q1;
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    input C0;
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    input C1;
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    input CE;
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    input D;
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    input R;
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    input S;
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    parameter DDR_ALIGNMENT = "NONE";
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    parameter INIT_Q0 = 1'b0;
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    parameter INIT_Q1 = 1'b0;
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    parameter SRTYPE = "SYNC";
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    pullup   P1 (CE);
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    pulldown P2 (R);
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    pulldown P3 (S);
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    reg q0_out, q1_out;
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    reg q0_out_int, q1_out_int;
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    reg q0_c0_out_int, q1_c0_out_int;
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    wire PC0, PC1;
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    buf buf_q0 (Q0, q0_out);
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    buf buf_q1 (Q1, q1_out);
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    initial begin
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        if ((INIT_Q0 != 1'b0) && (INIT_Q0 != 1'b1)) begin
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            $display("Attribute Syntax Error : The attribute INIT_Q0 on IDDR2 instance %m is set to %d.  Legal values for this attribute are 0 or 1.", INIT_Q0);
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            $finish;
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        end
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        if ((INIT_Q1 != 1'b0) && (INIT_Q1 != 1'b1)) begin
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            $display("Attribute Syntax Error : The attribute INIT_Q0 on IDDR2 instance %m is set to %d.  Legal values for this attribute are 0 or 1.", INIT_Q1);
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            $finish;
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        end
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        if ((DDR_ALIGNMENT != "C1") && (DDR_ALIGNMENT != "C0") && (DDR_ALIGNMENT != "NONE")) begin
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            $display("Attribute Syntax Error : The attribute DDR_ALIGNMENT on IDDR2 instance %m is set to %s.  Legal values for this attribute are C0, C1 or NONE.", DDR_ALIGNMENT);
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            $finish;
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        end
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        if ((SRTYPE != "ASYNC") && (SRTYPE != "SYNC")) begin
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            $display("Attribute Syntax Error : The attribute SRTYPE on IDDR2 instance %m is set to %s.  Legal values for this attribute are ASYNC or SYNC.", SRTYPE);
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            $finish;
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        end
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    end // initial begin
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    assign PC0 = ((DDR_ALIGNMENT== "C0") || (DDR_ALIGNMENT== "NONE"))?  C0 : C1;
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    assign PC1 = ((DDR_ALIGNMENT== "C0") || (DDR_ALIGNMENT== "NONE"))?  C1 : C0;
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    initial begin
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        assign q0_out_int = INIT_Q0;
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        assign q1_out_int = INIT_Q1;
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        assign q0_c0_out_int = INIT_Q0;
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        assign q1_c0_out_int = INIT_Q1;
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    end
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    always @(R or S) begin
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            deassign q0_out_int;
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            deassign q1_out_int;
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            deassign q0_c0_out_int;
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            deassign q1_c0_out_int;
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            if (SRTYPE == "ASYNC") begin
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                if (R == 1) begin
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                    assign q0_out_int = 0;
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                    assign q1_out_int = 0;
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                    assign q0_c0_out_int = 0;
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                    assign q1_c0_out_int = 0;
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                end
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                else if (R == 0 && S == 1) begin
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                    assign q0_out_int = 1;
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                    assign q1_out_int = 1;
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                end
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            end // if (SRTYPE == "ASYNC")
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    end // always @ (GSR or R or S)
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    always @(posedge PC0) begin
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        if (R == 1 && SRTYPE == "SYNC") begin
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            q0_out_int <= 0;
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            q0_c0_out_int <= 0;
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            q1_c0_out_int <= 0;
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        end
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        else if (R == 0 && S == 1 && SRTYPE == "SYNC") begin
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            q0_out_int <= 1;
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        end
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        else if (CE == 1 && R == 0 && S == 0) begin
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            q0_out_int <= D;
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            q0_c0_out_int <= q0_out_int;
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            q1_c0_out_int <= q1_out_int;
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        end
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    end // always @ (posedge PC0)
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    always @(posedge PC1) begin
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        if (R == 1 && SRTYPE == "SYNC") begin
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            q1_out_int <= 0;
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        end
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        else if (R == 0 && S == 1 && SRTYPE == "SYNC") begin
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            q1_out_int <= 1;
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        end
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        else if (CE == 1 && R == 0 && S == 0) begin
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            q1_out_int <= D;
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        end
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    end // always @ (posedge PC1)
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    always @(q0_out_int or q1_out_int or q1_c0_out_int or q0_c0_out_int) begin
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        case (DDR_ALIGNMENT)
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            "NONE" : begin
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                       q0_out <= q0_out_int;
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                       q1_out <= q1_out_int;
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                     end
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            "C0" : begin
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                       q0_out <= q0_out_int;
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                       q1_out <= q1_c0_out_int;
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                   end
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            "C1" : begin
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                       q0_out <= q0_out_int;
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                       q1_out <= q1_c0_out_int;
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                   end
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        endcase // case(DDR_ALIGNMENT)
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    end // always @ (q0_out_int or q1_out_int or q1_c0_out_int or q0_c0_out_int)
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    specify
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        if (C0) (C0 => Q0) = (100, 100);
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        if (C0) (C0 => Q1) = (100, 100);
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        if (C1) (C1 => Q1) = (100, 100);
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        if (C1) (C1 => Q0) = (100, 100);
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        specparam PATHPULSE$ = 0;
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    endspecify
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endmodule // IDDR2
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