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lekernel |
///////////////////////////////////////////////////////////////////////////////
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// Copyright (c) 1995/2005 Xilinx, Inc.
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// All Right Reserved.
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///////////////////////////////////////////////////////////////////////////////
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// Modified for HPDMC simulation, based on Xilinx 05/29/07 revision
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///////////////////////////////////////////////////////////////////////////////
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module ODDR #(
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parameter DDR_CLK_EDGE = "OPPOSITE_EDGE",
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parameter INIT = 1'b0,
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parameter SRTYPE = "SYNC"
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) (
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output Q,
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input C,
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input CE,
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input D1,
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input D2,
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input R,
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input S
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);
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reg q_out = INIT, qd2_posedge_int;
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wire c_in;
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wire ce_in;
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wire d1_in;
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wire d2_in;
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wire gsr_in;
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wire r_in;
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wire s_in;
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buf buf_c(c_in, C);
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buf buf_ce(ce_in, CE);
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buf buf_d1(d1_in, D1);
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buf buf_d2(d2_in, D2);
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buf buf_q(Q, q_out);
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buf buf_r(r_in, R);
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buf buf_s(s_in, S);
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initial begin
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if((INIT != 0) && (INIT != 1)) begin
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$display("Attribute Syntax Error : The attribute INIT on ODDR instance %m is set to %d. Legal values for this attribute are 0 or 1.", INIT);
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$finish;
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end
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if((DDR_CLK_EDGE != "OPPOSITE_EDGE") && (DDR_CLK_EDGE != "SAME_EDGE")) begin
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$display("Attribute Syntax Error : The attribute DDR_CLK_EDGE on ODDR instance %m is set to %s. Legal values for this attribute are OPPOSITE_EDGE or SAME_EDGE.", DDR_CLK_EDGE);
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$finish;
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end
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if((SRTYPE != "ASYNC") && (SRTYPE != "SYNC")) begin
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$display("Attribute Syntax Error : The attribute SRTYPE on ODDR instance %m is set to %s. Legal values for this attribute are ASYNC or SYNC.", SRTYPE);
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$finish;
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end
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end
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always @(r_in, s_in) begin
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if(r_in == 1'b1 && SRTYPE == "ASYNC") begin
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assign q_out = 1'b0;
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assign qd2_posedge_int = 1'b0;
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end else if(r_in == 1'b0 && s_in == 1'b1 && SRTYPE == "ASYNC") begin
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assign q_out = 1'b1;
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assign qd2_posedge_int = 1'b1;
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end else if((r_in == 1'b1 || s_in == 1'b1) && SRTYPE == "SYNC") begin
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deassign q_out;
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deassign qd2_posedge_int;
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end else if(r_in == 1'b0 && s_in == 1'b0) begin
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deassign q_out;
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deassign qd2_posedge_int;
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end
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end
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always @(posedge c_in) begin
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if(r_in == 1'b1) begin
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q_out <= 1'b0;
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qd2_posedge_int <= 1'b0;
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end else if(r_in == 1'b0 && s_in == 1'b1) begin
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q_out <= 1'b1;
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qd2_posedge_int <= 1'b1;
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end else if(ce_in == 1'b1 && r_in == 1'b0 && s_in == 1'b0) begin
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q_out <= d1_in;
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qd2_posedge_int <= d2_in;
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end
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end
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always @(negedge c_in) begin
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if(r_in == 1'b1)
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q_out <= 1'b0;
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else if(r_in == 1'b0 && s_in == 1'b1)
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q_out <= 1'b1;
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else if(ce_in == 1'b1 && r_in == 1'b0 && s_in == 1'b0) begin
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if(DDR_CLK_EDGE == "SAME_EDGE")
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q_out <= qd2_posedge_int;
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else if(DDR_CLK_EDGE == "OPPOSITE_EDGE")
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q_out <= d2_in;
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end
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end
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endmodule
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