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lekernel |
/****************************************************************************************
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*
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* File Name: tb.v
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* Version: 5.7
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* Model: BUS Functional
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*
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* Dependencies: ddr.v, ddr_parameters.v
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*
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* Description: Micron SDRAM DDR (Double Data Rate) test bench
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*
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* Note: - Set simulator resolution to "ps" accuracy
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* - Set Debug = 0 to disable $display messages
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*
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* Disclaimer This software code and all associated documentation, comments or other
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* of Warranty: information (collectively "Software") is provided "AS IS" without
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* warranty of any kind. MICRON TECHNOLOGY, INC. ("MTI") EXPRESSLY
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* DISCLAIMS ALL WARRANTIES EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED
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* TO, NONINFRINGEMENT OF THIRD PARTY RIGHTS, AND ANY IMPLIED WARRANTIES
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* OF MERCHANTABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE. MTI DOES NOT
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* WARRANT THAT THE SOFTWARE WILL MEET YOUR REQUIREMENTS, OR THAT THE
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* OPERATION OF THE SOFTWARE WILL BE UNINTERRUPTED OR ERROR-FREE.
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* FURTHERMORE, MTI DOES NOT MAKE ANY REPRESENTATIONS REGARDING THE USE OR
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* THE RESULTS OF THE USE OF THE SOFTWARE IN TERMS OF ITS CORRECTNESS,
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* ACCURACY, RELIABILITY, OR OTHERWISE. THE ENTIRE RISK ARISING OUT OF USE
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* OR PERFORMANCE OF THE SOFTWARE REMAINS WITH YOU. IN NO EVENT SHALL MTI,
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* ITS AFFILIATED COMPANIES OR THEIR SUPPLIERS BE LIABLE FOR ANY DIRECT,
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* INDIRECT, CONSEQUENTIAL, INCIDENTAL, OR SPECIAL DAMAGES (INCLUDING,
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* WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS INTERRUPTION,
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* OR LOSS OF INFORMATION) ARISING OUT OF YOUR USE OF OR INABILITY TO USE
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* THE SOFTWARE, EVEN IF MTI HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH
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* DAMAGES. Because some jurisdictions prohibit the exclusion or
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* limitation of liability for consequential or incidental damages, the
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* above limitation may not apply to you.
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*
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* Copyright 2003 Micron Technology, Inc. All rights reserved.
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*
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* Rev Author Date Changes
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* --------------------------------------------------------------------------------
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* 2.1 SPH 03/19/2002 - Second Release
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* - Fix tWR and several incompatability
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* between different simulators
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* 3.0 TFK 02/18/2003 - Added tDSS and tDSH timing checks.
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* - Added tDQSH and tDQSL timing checks.
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* 3.1 CAH 05/28/2003 - update all models to release version 3.1
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* (no changes to this model)
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* 3.2 JMK 06/16/2003 - updated all DDR400 models to support CAS Latency 3
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* 3.3 JMK 09/11/2003 - Added initialization sequence checks.
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* 4.0 JMK 12/01/2003 - Grouped parameters into "ddr_parameters.v"
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* - Fixed tWTR check
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* 4.1 JMK 01/14/2001 - Grouped specify parameters by speed grade
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* - Fixed mem_sizes parameter
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* 4.2 JMK 03/19/2004 - Fixed pulse width checking on Dqs
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* 4.3 JMK 04/27/2004 - Changed BL wire size in tb module
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* - Changed Dq_buf size to [15:0]
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* 5.0 JMK 06/16/2004 - Added read to write checking.
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* - Added read with precharge truncation to write checking.
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* - Added associative memory array to reduce memory consumption.
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* - Added checking for required DQS edges during write.
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* 5.1 JMK 08/16/2004 - Fixed checking for required DQS edges during write.
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* - Fixed wdqs_valid window.
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* 5.2 JMK 09/24/2004 - Read or Write without activate will be ignored.
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* 5.3 JMK 10/27/2004 - Added tMRD checking during Auto Refresh and Activate.
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* - Added tRFC checking during Load Mode and Precharge.
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* 5.4 JMK 12/13/2004 - The model will not respond to illegal command sequences.
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* 5.5 SPH 01/13/2005 - The model will issue a halt on illegal command sequences.
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* JMK 02/11/2005 - Changed the display format for numbers to hex.
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* 5.6 JMK 04/22/2005 - Fixed Write with auto precharge calculation.
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* 5.7 JMK 08/05/2005 - Changed conditions for read with precharge truncation error.
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* - Renamed parameters file with .vh extension.
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* 5.8 BAS 12/26/2006 - Added parameters for T46A part - 256Mb
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* - Added x32 functionality
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* 6.0 BAS 05/31/2007 - Added read_verify command
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****************************************************************************************/
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`timescale 1ns / 1ps
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module tb;
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`include "ddr_parameters.vh"
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reg clk ;
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reg clk_n ;
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reg cke ;
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reg cs_n ;
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reg ras_n ;
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reg cas_n ;
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reg we_n ;
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reg [BA_BITS - 1 : 0] ba ;
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reg [ADDR_BITS - 1 : 0] a ;
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reg dq_en ;
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reg [DM_BITS - 1 : 0] dm_out ;
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reg [DQ_BITS - 1 : 0] dq_out ;
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reg [DM_BITS-1 : 0] dm_fifo [0 : 13];
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reg [DQ_BITS-1 : 0] dq_fifo [0 : 13];
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reg [DQ_BITS-1 : 0] dq_in_pos ;
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reg [DQ_BITS-1 : 0] dq_in_neg ;
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reg dqs_en ;
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reg [DQS_BITS - 1 : 0] dqs_out ;
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reg [12 : 0] mode_reg ; //Mode Register
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reg [12 : 0] ext_mode_reg; //Extended Mode Register
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wire BO = mode_reg[3]; //Burst Order
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wire [7 : 0] BL = (1<<mode_reg[2:0]); //Burst Length
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// XXX modification by lekernel - removed CL2.5 support which crashes free simulators
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// can be rewritten to make it work, but as CL2.5 is not used by Milkymist I'm lazy :)
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// was wire [2 : 0] CL = (mode_reg[6:4] == 3'b110) ? 2.5 : mode_reg[6:4]; //CAS Latency
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wire [2 : 0] CL = mode_reg[6:4]; //CAS Latency
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wire dqs_n_en = ~ext_mode_reg[10]; //dqs# Enable
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wire [2 : 0] AL = ext_mode_reg[5:3]; //Additive Latency
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wire [3 : 0] RL = CL ; //Read Latency
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wire [3 : 0] WL = 1 ; //Write Latency
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wire [DM_BITS - 1 : 0] dm = dq_en ? dm_out : {DM_BITS{1'bz}};
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wire [DQ_BITS - 1 : 0] dq = dq_en ? dq_out : {DQ_BITS{1'bz}};
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wire [DQS_BITS - 1 : 0] dqs = dqs_en ? dqs_out : {DQS_BITS{1'bz}};
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wire [DQS_BITS - 1 : 0] dqs_n = (dqs_en & dqs_n_en) ? ~dqs_out : {DQS_BITS{1'bz}};
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wire [DQS_BITS - 1 : 0] rdqs_n = {DM_BITS{1'bz}};
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wire [15 : 0] dqs_in = dqs;
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wire [63 : 0] dq_in = dq;
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ddr sdramddr (
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clk ,
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clk_n ,
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cke ,
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cs_n ,
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ras_n ,
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cas_n ,
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we_n ,
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ba ,
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a ,
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dm ,
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dq ,
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dqs
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);
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// timing definition in tCK units
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real tck ;
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integer tmrd ;
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integer trap ;
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integer tras ;
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integer trc ;
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integer trfc ;
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integer trcd ;
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integer trp ;
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integer trrd ;
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integer twr ;
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initial begin
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`ifdef period
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tck = `period ;
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`else
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tck = tCK;
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`endif
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tmrd = ciel(tMRD/tck);
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trap = ciel(tRAP/tck);
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tras = ciel(tRAS/tck);
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trc = ciel(tRC/tck);
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trfc = ciel(tRFC/tck);
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trcd = ciel(tRCD/tck);
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trp = ciel(tRP/tck);
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trrd = ciel(tRRD/tck);
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twr = ciel(tWR/tck);
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end
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initial clk <= 1'b1;
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initial clk_n <= 1'b0;
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always @(posedge clk) begin
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clk <= #(tck/2) 1'b0;
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clk_n <= #(tck/2) 1'b1;
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clk <= #(tck) 1'b1;
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clk_n <= #(tck) 1'b0;
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end
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function integer ciel;
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input number;
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real number;
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if (number > $rtoi(number))
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ciel = $rtoi(number) + 1;
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else
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ciel = number;
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endfunction
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task power_up;
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begin
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cke <= 1'b0;
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repeat(10) @(negedge clk);
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$display ("%m at time %t TB: A 200 us delay is required before CKE can be brought high.", $time);
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@ (negedge clk) cke = 1'b1;
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nop (400/tck+1);
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end
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endtask
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task load_mode;
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input [BA_BITS - 1 : 0] bank;
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input [ADDR_BITS - 1 : 0] addr;
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begin
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case (bank)
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0: mode_reg = addr;
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1: ext_mode_reg = addr;
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endcase
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cke = 1'b1;
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cs_n = 1'b0;
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ras_n = 1'b0;
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cas_n = 1'b0;
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we_n = 1'b0;
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ba = bank;
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a = addr;
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@(negedge clk);
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end
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endtask
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task refresh;
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begin
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cke = 1'b1;
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cs_n = 1'b0;
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ras_n = 1'b0;
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cas_n = 1'b0;
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we_n = 1'b1;
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@(negedge clk);
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end
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endtask
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task burst_term;
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integer i;
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begin
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cke = 1'b1;
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cs_n = 1'b0;
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ras_n = 1'b1;
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cas_n = 1'b1;
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we_n = 1'b0;
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@(negedge clk);
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for (i=0; i<BL; i=i+1) begin
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dm_fifo[2*RL + i] = {DM_BITS{1'bz}} ;
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dq_fifo[2*RL + i] = {DQ_BITS{1'bz}} ;
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end
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end
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endtask
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task self_refresh;
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input count;
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integer count;
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begin
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cke = 1'b0;
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cs_n = 1'b0;
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ras_n = 1'b0;
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cas_n = 1'b0;
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we_n = 1'b1;
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repeat(count) @(negedge clk);
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end
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endtask
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task precharge;
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input [BA_BITS - 1 : 0] bank;
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input ap; //precharge all
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begin
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cke = 1'b1;
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cs_n = 1'b0;
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ras_n = 1'b0;
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cas_n = 1'b1;
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we_n = 1'b0;
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ba = bank;
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a = (ap<<10);
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@(negedge clk);
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end
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endtask
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task activate;
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input [BA_BITS - 1 : 0] bank;
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input [ADDR_BITS - 1 : 0] row;
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begin
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cke = 1'b1;
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cs_n = 1'b0;
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ras_n = 1'b0;
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cas_n = 1'b1;
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we_n = 1'b1;
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ba = bank;
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a = row;
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@(negedge clk);
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end
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endtask
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//write task supports burst lengths <= 16
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task write;
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input [BA_BITS - 1 : 0] bank;
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input [COL_BITS - 1 : 0] col;
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input ap; //Auto Precharge
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input [16*DM_BITS - 1 : 0] dm;
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input [16*DQ_BITS - 1 : 0] dq;
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reg [ADDR_BITS - 1 : 0] atemp [1:0];
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reg [DQ_BITS/DM_BITS - 1 : 0] dm_temp;
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integer i,j;
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begin
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cke = 1'b1;
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cs_n = 1'b0;
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ras_n = 1'b1;
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cas_n = 1'b0;
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we_n = 1'b0;
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ba = bank;
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atemp[0] = col & 10'h3ff; //ADDR[ 9: 0] = COL[ 9: 0]
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atemp[1] = (col>>10)<<11; //ADDR[ N:11] = COL[ N:10]
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a = atemp[0] | atemp[1] | (ap<<10);
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for (i=0; i<=BL; i=i+1) begin
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dqs_en <= #(WL*tck + i*tck/2) 1'b1;
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if (i%2 === 0) begin
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dqs_out <= #(WL*tck + i*tck/2) {DQS_BITS{1'b0}};
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end else begin
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dqs_out <= #(WL*tck + i*tck/2) {DQS_BITS{1'b1}};
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end
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dq_en <= #(WL*tck + i*tck/2 + tck/4) 1'b1;
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for (j=0; j<DM_BITS; j=j+1) begin
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dm_temp = dm>>((i*DM_BITS + j)*DQ_BITS/DM_BITS);
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dm_out[j] <= #(WL*tck + i*tck/2 + tck/4) &dm_temp;
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end
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dq_out <= #(WL*tck + i*tck/2 + tck/4) dq>>i*DQ_BITS;
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case (i)
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15: dm_out <= #(WL*tck + i*tck/2 + tck/4) dm[16*DM_BITS-1 : 15*DM_BITS];
|
| 320 |
|
|
14: dm_out <= #(WL*tck + i*tck/2 + tck/4) dm[15*DM_BITS-1 : 14*DM_BITS];
|
| 321 |
|
|
13: dm_out <= #(WL*tck + i*tck/2 + tck/4) dm[14*DM_BITS-1 : 13*DM_BITS];
|
| 322 |
|
|
12: dm_out <= #(WL*tck + i*tck/2 + tck/4) dm[13*DM_BITS-1 : 12*DM_BITS];
|
| 323 |
|
|
11: dm_out <= #(WL*tck + i*tck/2 + tck/4) dm[12*DM_BITS-1 : 11*DM_BITS];
|
| 324 |
|
|
10: dm_out <= #(WL*tck + i*tck/2 + tck/4) dm[11*DM_BITS-1 : 10*DM_BITS];
|
| 325 |
|
|
9: dm_out <= #(WL*tck + i*tck/2 + tck/4) dm[10*DM_BITS-1 : 9*DM_BITS];
|
| 326 |
|
|
8: dm_out <= #(WL*tck + i*tck/2 + tck/4) dm[ 9*DM_BITS-1 : 8*DM_BITS];
|
| 327 |
|
|
7: dm_out <= #(WL*tck + i*tck/2 + tck/4) dm[ 8*DM_BITS-1 : 7*DM_BITS];
|
| 328 |
|
|
6: dm_out <= #(WL*tck + i*tck/2 + tck/4) dm[ 7*DM_BITS-1 : 6*DM_BITS];
|
| 329 |
|
|
5: dm_out <= #(WL*tck + i*tck/2 + tck/4) dm[ 6*DM_BITS-1 : 5*DM_BITS];
|
| 330 |
|
|
4: dm_out <= #(WL*tck + i*tck/2 + tck/4) dm[ 5*DM_BITS-1 : 4*DM_BITS];
|
| 331 |
|
|
3: dm_out <= #(WL*tck + i*tck/2 + tck/4) dm[ 4*DM_BITS-1 : 3*DM_BITS];
|
| 332 |
|
|
2: dm_out <= #(WL*tck + i*tck/2 + tck/4) dm[ 3*DM_BITS-1 : 2*DM_BITS];
|
| 333 |
|
|
1: dm_out <= #(WL*tck + i*tck/2 + tck/4) dm[ 2*DM_BITS-1 : 1*DM_BITS];
|
| 334 |
|
|
0: dm_out <= #(WL*tck + i*tck/2 + tck/4) dm[ 1*DM_BITS-1 : 0*DM_BITS];
|
| 335 |
|
|
endcase
|
| 336 |
|
|
case (i)
|
| 337 |
|
|
15: dq_out <= #(WL*tck + i*tck/2 + tck/4) dq[16*DQ_BITS-1 : 15*DQ_BITS];
|
| 338 |
|
|
14: dq_out <= #(WL*tck + i*tck/2 + tck/4) dq[15*DQ_BITS-1 : 14*DQ_BITS];
|
| 339 |
|
|
13: dq_out <= #(WL*tck + i*tck/2 + tck/4) dq[14*DQ_BITS-1 : 13*DQ_BITS];
|
| 340 |
|
|
12: dq_out <= #(WL*tck + i*tck/2 + tck/4) dq[13*DQ_BITS-1 : 12*DQ_BITS];
|
| 341 |
|
|
11: dq_out <= #(WL*tck + i*tck/2 + tck/4) dq[12*DQ_BITS-1 : 11*DQ_BITS];
|
| 342 |
|
|
10: dq_out <= #(WL*tck + i*tck/2 + tck/4) dq[11*DQ_BITS-1 : 10*DQ_BITS];
|
| 343 |
|
|
9: dq_out <= #(WL*tck + i*tck/2 + tck/4) dq[10*DQ_BITS-1 : 9*DQ_BITS];
|
| 344 |
|
|
8: dq_out <= #(WL*tck + i*tck/2 + tck/4) dq[ 9*DQ_BITS-1 : 8*DQ_BITS];
|
| 345 |
|
|
7: dq_out <= #(WL*tck + i*tck/2 + tck/4) dq[ 8*DQ_BITS-1 : 7*DQ_BITS];
|
| 346 |
|
|
6: dq_out <= #(WL*tck + i*tck/2 + tck/4) dq[ 7*DQ_BITS-1 : 6*DQ_BITS];
|
| 347 |
|
|
5: dq_out <= #(WL*tck + i*tck/2 + tck/4) dq[ 6*DQ_BITS-1 : 5*DQ_BITS];
|
| 348 |
|
|
4: dq_out <= #(WL*tck + i*tck/2 + tck/4) dq[ 5*DQ_BITS-1 : 4*DQ_BITS];
|
| 349 |
|
|
3: dq_out <= #(WL*tck + i*tck/2 + tck/4) dq[ 4*DQ_BITS-1 : 3*DQ_BITS];
|
| 350 |
|
|
2: dq_out <= #(WL*tck + i*tck/2 + tck/4) dq[ 3*DQ_BITS-1 : 2*DQ_BITS];
|
| 351 |
|
|
1: dq_out <= #(WL*tck + i*tck/2 + tck/4) dq[ 2*DQ_BITS-1 : 1*DQ_BITS];
|
| 352 |
|
|
0: dq_out <= #(WL*tck + i*tck/2 + tck/4) dq[ 1*DQ_BITS-1 : 0*DQ_BITS];
|
| 353 |
|
|
endcase
|
| 354 |
|
|
dq_en <= #(WL*tck + i*tck/2 + tck/4) 1'b1;
|
| 355 |
|
|
end
|
| 356 |
|
|
dqs_en <= #(WL*tck + BL*tck/2 + tck/2) 1'b0;
|
| 357 |
|
|
dq_en <= #(WL*tck + BL*tck/2 + tck/4) 1'b0;
|
| 358 |
|
|
@(negedge clk);
|
| 359 |
|
|
end
|
| 360 |
|
|
endtask
|
| 361 |
|
|
|
| 362 |
|
|
task read;
|
| 363 |
|
|
input [BA_BITS - 1 : 0]bank;
|
| 364 |
|
|
input [COL_BITS - 1 : 0] col;
|
| 365 |
|
|
input ap; //Auto Precharge
|
| 366 |
|
|
reg [ADDR_BITS - 1 : 0] atemp [1:0];
|
| 367 |
|
|
begin
|
| 368 |
|
|
cke = 1'b1;
|
| 369 |
|
|
cs_n = 1'b0;
|
| 370 |
|
|
ras_n = 1'b1;
|
| 371 |
|
|
cas_n = 1'b0;
|
| 372 |
|
|
we_n = 1'b1;
|
| 373 |
|
|
ba = bank;
|
| 374 |
|
|
atemp[0] = col & 10'h3ff; //ADDR[ 9: 0] = COL[ 9: 0]
|
| 375 |
|
|
atemp[1] = (col>>10)<<11; //ADDR[ N:11] = COL[ N:10]
|
| 376 |
|
|
a = atemp[0] | atemp[1] | (ap<<10);
|
| 377 |
|
|
@(negedge clk);
|
| 378 |
|
|
end
|
| 379 |
|
|
endtask
|
| 380 |
|
|
|
| 381 |
|
|
// read with data verification
|
| 382 |
|
|
task read_verify;
|
| 383 |
|
|
input [BA_BITS - 1 : 0] bank;
|
| 384 |
|
|
input [COL_BITS - 1 : 0] col;
|
| 385 |
|
|
input ap; //Auto Precharge
|
| 386 |
|
|
input [16*DM_BITS - 1 : 0] dm; //Expected Data Mask
|
| 387 |
|
|
input [16*DQ_BITS - 1 : 0] dq; //Expected Data
|
| 388 |
|
|
integer i;
|
| 389 |
|
|
reg [2:0] brst_col;
|
| 390 |
|
|
begin
|
| 391 |
|
|
read (bank, col, ap);
|
| 392 |
|
|
for (i=0; i<BL; i=i+1) begin
|
| 393 |
|
|
// perform burst ordering
|
| 394 |
|
|
brst_col = col ^ i;
|
| 395 |
|
|
if (!BO) begin
|
| 396 |
|
|
brst_col = col + i;
|
| 397 |
|
|
end
|
| 398 |
|
|
if (BL == 4) begin
|
| 399 |
|
|
brst_col[2] = 1'b0 ;
|
| 400 |
|
|
end else if (BL == 2) begin
|
| 401 |
|
|
brst_col[2:1] = 2'b00 ;
|
| 402 |
|
|
end
|
| 403 |
|
|
dm_fifo[2*RL + i] = dm >> (i*DM_BITS);
|
| 404 |
|
|
dq_fifo[2*RL + i] = dq >> (i*DQ_BITS);
|
| 405 |
|
|
end
|
| 406 |
|
|
end
|
| 407 |
|
|
endtask
|
| 408 |
|
|
|
| 409 |
|
|
task nop;
|
| 410 |
|
|
input count;
|
| 411 |
|
|
integer count;
|
| 412 |
|
|
begin
|
| 413 |
|
|
cke = 1'b1;
|
| 414 |
|
|
cs_n = 1'b0;
|
| 415 |
|
|
ras_n = 1'b1;
|
| 416 |
|
|
cas_n = 1'b1;
|
| 417 |
|
|
we_n = 1'b1;
|
| 418 |
|
|
repeat(count) @(negedge clk);
|
| 419 |
|
|
end
|
| 420 |
|
|
endtask
|
| 421 |
|
|
|
| 422 |
|
|
task deselect;
|
| 423 |
|
|
input count;
|
| 424 |
|
|
integer count;
|
| 425 |
|
|
begin
|
| 426 |
|
|
cke = 1'b1;
|
| 427 |
|
|
cs_n = 1'b1;
|
| 428 |
|
|
ras_n = 1'b1;
|
| 429 |
|
|
cas_n = 1'b1;
|
| 430 |
|
|
we_n = 1'b1;
|
| 431 |
|
|
repeat(count) @(negedge clk);
|
| 432 |
|
|
end
|
| 433 |
|
|
endtask
|
| 434 |
|
|
|
| 435 |
|
|
task power_down;
|
| 436 |
|
|
input count;
|
| 437 |
|
|
integer count;
|
| 438 |
|
|
begin
|
| 439 |
|
|
cke = 1'b0;
|
| 440 |
|
|
cs_n = 1'b1;
|
| 441 |
|
|
ras_n = 1'b1;
|
| 442 |
|
|
cas_n = 1'b1;
|
| 443 |
|
|
we_n = 1'b1;
|
| 444 |
|
|
repeat(count) @(negedge clk);
|
| 445 |
|
|
end
|
| 446 |
|
|
endtask
|
| 447 |
|
|
|
| 448 |
|
|
function [16*DQ_BITS - 1 : 0] sort_data;
|
| 449 |
|
|
input [16*DQ_BITS - 1 : 0] dq;
|
| 450 |
|
|
input [2:0] col;
|
| 451 |
|
|
integer i;
|
| 452 |
|
|
reg [2:0] brst_col;
|
| 453 |
|
|
reg [DQ_BITS - 1 :0] burst;
|
| 454 |
|
|
begin
|
| 455 |
|
|
sort_data = 0;
|
| 456 |
|
|
for (i=0; i<BL; i=i+1) begin
|
| 457 |
|
|
// perform burst ordering
|
| 458 |
|
|
brst_col = col ^ i;
|
| 459 |
|
|
if (!BO) begin
|
| 460 |
|
|
brst_col[1:0] = col + i;
|
| 461 |
|
|
end
|
| 462 |
|
|
burst = dq >> (brst_col*DQ_BITS);
|
| 463 |
|
|
sort_data = sort_data | burst<<(i*DQ_BITS);
|
| 464 |
|
|
end
|
| 465 |
|
|
end
|
| 466 |
|
|
endfunction
|
| 467 |
|
|
|
| 468 |
|
|
// receiver(s) for data_verify process
|
| 469 |
|
|
always @(dqs_in[0]) begin #(tDQSQ); dqs_receiver(0); end
|
| 470 |
|
|
always @(dqs_in[1]) begin #(tDQSQ); dqs_receiver(1); end
|
| 471 |
|
|
always @(dqs_in[2]) begin #(tDQSQ); dqs_receiver(2); end
|
| 472 |
|
|
always @(dqs_in[3]) begin #(tDQSQ); dqs_receiver(3); end
|
| 473 |
|
|
always @(dqs_in[4]) begin #(tDQSQ); dqs_receiver(4); end
|
| 474 |
|
|
always @(dqs_in[5]) begin #(tDQSQ); dqs_receiver(5); end
|
| 475 |
|
|
always @(dqs_in[6]) begin #(tDQSQ); dqs_receiver(6); end
|
| 476 |
|
|
always @(dqs_in[7]) begin #(tDQSQ); dqs_receiver(7); end
|
| 477 |
|
|
|
| 478 |
|
|
task dqs_receiver;
|
| 479 |
|
|
input i;
|
| 480 |
|
|
integer i;
|
| 481 |
|
|
begin
|
| 482 |
|
|
if (dqs_in[i]) begin
|
| 483 |
|
|
case (i)
|
| 484 |
|
|
0: dq_in_pos[ 7: 0] <= dq_in[ 7: 0];
|
| 485 |
|
|
1: dq_in_pos[15: 8] <= dq_in[15: 8];
|
| 486 |
|
|
/* 2: dq_in_pos[23:16] <= dq_in[23:16];
|
| 487 |
|
|
3: dq_in_pos[31:24] <= dq_in[31:24];
|
| 488 |
|
|
4: dq_in_pos[39:32] <= dq_in[39:32];
|
| 489 |
|
|
5: dq_in_pos[47:40] <= dq_in[47:40];
|
| 490 |
|
|
6: dq_in_pos[55:48] <= dq_in[55:48];
|
| 491 |
|
|
7: dq_in_pos[63:56] <= dq_in[63:56];*/
|
| 492 |
|
|
endcase
|
| 493 |
|
|
end else if (!dqs_in[i]) begin
|
| 494 |
|
|
case (i)
|
| 495 |
|
|
0: dq_in_neg[ 7: 0] <= dq_in[ 7: 0];
|
| 496 |
|
|
1: dq_in_neg[15: 8] <= dq_in[15: 8];
|
| 497 |
|
|
/* 2: dq_in_neg[23:16] <= dq_in[23:16];
|
| 498 |
|
|
3: dq_in_neg[31:24] <= dq_in[31:24];
|
| 499 |
|
|
4: dq_in_pos[39:32] <= dq_in[39:32];
|
| 500 |
|
|
5: dq_in_pos[47:40] <= dq_in[47:40];
|
| 501 |
|
|
6: dq_in_pos[55:48] <= dq_in[55:48];
|
| 502 |
|
|
7: dq_in_pos[63:56] <= dq_in[63:56];*/
|
| 503 |
|
|
endcase
|
| 504 |
|
|
end
|
| 505 |
|
|
end
|
| 506 |
|
|
endtask
|
| 507 |
|
|
|
| 508 |
|
|
|
| 509 |
|
|
// perform data verification as a result of read_verify task call
|
| 510 |
|
|
always @(clk) begin : data_verify
|
| 511 |
|
|
integer i;
|
| 512 |
|
|
reg [DM_BITS-1 : 0] data_mask;
|
| 513 |
|
|
reg [8*DM_BITS-1 : 0] bit_mask;
|
| 514 |
|
|
|
| 515 |
|
|
for (i=0; i<=14; i=i+1) begin
|
| 516 |
|
|
dm_fifo[i] = dm_fifo[i+1];
|
| 517 |
|
|
dq_fifo[i] = dq_fifo[i+1];
|
| 518 |
|
|
end
|
| 519 |
|
|
dm_fifo[13] = 'bz;
|
| 520 |
|
|
dq_fifo[13] = 'bz;
|
| 521 |
|
|
// dm_fifo[30] = 0;
|
| 522 |
|
|
// dq_fifo[30] = 0;
|
| 523 |
|
|
data_mask = dm_fifo[0];
|
| 524 |
|
|
|
| 525 |
|
|
data_mask = dm_fifo[0];
|
| 526 |
|
|
for (i=0; i<DM_BITS; i=i+1) begin
|
| 527 |
|
|
bit_mask = {bit_mask, {8{~data_mask[i]}}};
|
| 528 |
|
|
end
|
| 529 |
|
|
if (clk) begin
|
| 530 |
|
|
if ((dq_in_neg & bit_mask) != (dq_fifo[0] & bit_mask))
|
| 531 |
|
|
$display ("%m at time %t: ERROR: Read data miscompare: Expected = %h, Actual = %h, Mask = %h", $time, dq_fifo[0], dq_in_neg, bit_mask);
|
| 532 |
|
|
end else begin
|
| 533 |
|
|
if ((dq_in_pos & bit_mask) != (dq_fifo[0] & bit_mask))
|
| 534 |
|
|
$display ("%m at time %t: ERROR: Read data miscompare: Expected = %h, Actual = %h, Mask = %h", $time, dq_fifo[0], dq_in_pos, bit_mask);
|
| 535 |
|
|
end
|
| 536 |
|
|
end
|
| 537 |
|
|
|
| 538 |
|
|
|
| 539 |
|
|
|
| 540 |
|
|
reg test_done;
|
| 541 |
|
|
initial test_done = 0;
|
| 542 |
|
|
|
| 543 |
|
|
// End-of-test triggered in 'subtest.vh'
|
| 544 |
|
|
always @(test_done) begin : all_done
|
| 545 |
|
|
if (test_done == 1) begin
|
| 546 |
|
|
#5000
|
| 547 |
|
|
$display ("Simulation is Complete");
|
| 548 |
|
|
$stop(0);
|
| 549 |
|
|
$finish;
|
| 550 |
|
|
end
|
| 551 |
|
|
end
|
| 552 |
|
|
|
| 553 |
|
|
// Test included from external file
|
| 554 |
|
|
`include "subtest.vh"
|
| 555 |
|
|
|
| 556 |
|
|
endmodule
|
