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[/] [hssdrc/] [trunk/] [core/] [test.v] - Blame information for rev 3

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// Testbench for Micron SDR SDRAM Verilog models
 
`timescale 1ns / 1ps
 
module test;
 
reg         [31 : 0] dq;                            // SDRAM I/O
reg         [10 : 0] addr;                          // SDRAM Address
reg          [1 : 0] ba;                            // Bank Address
reg                  clk;                           // Clock
reg                  cke;                           // Synchronous Clock Enable
reg                  cs_n;                          // CS#
reg                  ras_n;                         // RAS#
reg                  cas_n;                         // CAS#
reg                  we_n;                          // WE#
reg          [3 : 0] dqm;                           // I/O Mask
 
wire        [31 : 0] DQ = dq;
 
parameter            hi_z = 32'bz;                  // Hi-Z
 
parameter            tCK = 10;                      // Clock Period
 
mt48lc2m32b2 sdram0 (DQ, addr, ba, clk, cke, cs_n, ras_n, cas_n, we_n, dqm);
 
initial begin
    clk = 1'b0;
    cke = 1'b0;
    cs_n = 1'b1;
    dq  = hi_z;
end
 
always #5 clk = ~clk;
 
/*
always @ (posedge clk) begin
    $strobe("at time %t clk=%b cke=%b CS#=%b RAS#=%b CAS#=%b WE#=%b dqm=%b addr=%b ba=%b DQ=%d",
            $time, clk, cke, cs_n, ras_n, cas_n, we_n, dqm, addr, ba, DQ);
end
*/
 
task active;
    input  [1 : 0] bank;
    input [10 : 0] row;
    input [31 : 0] dq_in;
    begin
        cke   = 1;
        cs_n  = 0;
        ras_n = 0;
        cas_n = 1;
        we_n  = 1;
        dqm   = 0;
        ba    = bank;
        addr  = row;
        dq    = dq_in;
    end
endtask
 
task auto_refresh;
    begin
        cke   = 1;
        cs_n  = 0;
        ras_n = 0;
        cas_n = 0;
        we_n  = 1;
        dqm   = 0;
        //ba    = 0;
        //addr  = 0;
        dq    = hi_z;
    end
endtask
 
task burst_term;
    input [31 : 0] dq_in;
    begin
        cke   = 1;
        cs_n  = 0;
        ras_n = 1;
        cas_n = 1;
        we_n  = 0;
        dqm   = 0;
        //ba    = 0;
        //addr  = 0;
        dq    = dq_in;
    end
endtask
 
task load_mode_reg;
    input [10 : 0] op_code;
    begin
        cke   = 1;
        cs_n  = 0;
        ras_n = 0;
        cas_n = 0;
        we_n  = 0;
        dqm   = 0;
        ba    = 0;
        addr  = op_code;
        dq    = hi_z;
    end
endtask
 
task nop;
    input  [3 : 0] dqm_in;
    input [31 : 0] dq_in;
    begin
        cke   = 1;
        cs_n  = 0;
        ras_n = 1;
        cas_n = 1;
        we_n  = 1;
        dqm   = dqm_in;
        //ba    = 0;
        //addr  = 0;
        dq    = dq_in;
    end
endtask
 
task precharge_bank_0;
    input  [3 : 0] dqm_in;
    input [31 : 0] dq_in;
    begin
        cke   = 1;
        cs_n  = 0;
        ras_n = 0;
        cas_n = 1;
        we_n  = 0;
        dqm   = dqm_in;
        ba    = 0;
        addr  = 0;
        dq    = dq_in;
    end
endtask
 
task precharge_bank_1;
    input  [3 : 0] dqm_in;
    input [31 : 0] dq_in;
    begin
        cke   = 1;
        cs_n  = 0;
        ras_n = 0;
        cas_n = 1;
        we_n  = 0;
        dqm   = dqm_in;
        ba    = 1;
        addr  = 0;
        dq    = dq_in;
    end
endtask
 
task precharge_bank_2;
    input  [3 : 0] dqm_in;
    input [31 : 0] dq_in;
    begin
        cke   = 1;
        cs_n  = 0;
        ras_n = 0;
        cas_n = 1;
        we_n  = 0;
        dqm   = dqm_in;
        ba    = 2;
        addr  = 0;
        dq    = dq_in;
    end
endtask
 
task precharge_bank_3;
    input  [3 : 0] dqm_in;
    input [31 : 0] dq_in;
    begin
        cke   = 1;
        cs_n  = 0;
        ras_n = 0;
        cas_n = 1;
        we_n  = 0;
        dqm   = dqm_in;
        ba    = 3;
        addr  = 0;
        dq    = dq_in;
    end
endtask
 
task precharge_all_bank;
    input  [3 : 0] dqm_in;
    input [31 : 0] dq_in;
    begin
        cke   = 1;
        cs_n  = 0;
        ras_n = 0;
        cas_n = 1;
        we_n  = 0;
        dqm   = dqm_in;
        ba    = 0;
        addr  = 1024;            // A10 = 1
        dq    = dq_in;
    end
endtask
 
task read;
    input  [1 : 0] bank;
    input [10 : 0] column;
    input [31 : 0] dq_in;
    input  [3 : 0] dqm_in;
    begin
        cke   = 1;
        cs_n  = 0;
        ras_n = 1;
        cas_n = 0;
        we_n  = 1;
        dqm   = dqm_in;
        ba    = bank;
        addr  = column;
        dq    = dq_in;
    end
endtask
 
task write;
    input  [1 : 0] bank;
    input [10 : 0] column;
    input [31 : 0] dq_in;
    input  [3 : 0] dqm_in;
    begin
        cke   = 1;
        cs_n  = 0;
        ras_n = 1;
        cas_n = 0;
        we_n  = 0;
        dqm   = dqm_in;
        ba    = bank;
        addr  = column;
        dq    = dq_in;
    end
endtask
 
initial begin
    begin
        // Initialize
        #tCK; nop    (0, hi_z);                 // Nop
        #tCK; nop    (0, hi_z);                 // Nop
        #tCK; nop    (0, hi_z);                 // Nop
        #tCK; nop    (0, hi_z);                 // Nop
        #tCK; nop    (0, hi_z);                 // Nop
        #tCK; nop    (0, hi_z);                 // Nop
        #tCK; nop    (0, hi_z);                 // Nop
        #tCK; nop    (0, hi_z);                 // Nop
        #tCK; nop    (0, hi_z);                 // Nop
        #tCK; nop    (0, hi_z);                 // Nop
        #tCK; precharge_all_bank(0, hi_z);      // Precharge ALL Bank
        #tCK; nop    (0, hi_z);                 // Nop
        #tCK; nop    (0, hi_z);                 // Nop
        #tCK; nop    (0, hi_z);                 // Nop
        #tCK; nop    (0, hi_z);                 // Nop
        #tCK; auto_refresh;                     // Auto Refresh
        #tCK; nop    (0, hi_z);                 // Nop
        #tCK; nop    (0, hi_z);                 // Nop
        #tCK; nop    (0, hi_z);                 // Nop
        #tCK; nop    (0, hi_z);                 // Nop
        #tCK; nop    (0, hi_z);                 // Nop
        #tCK; nop    (0, hi_z);                 // Nop
        #tCK; nop    (0, hi_z);                 // Nop
        #tCK; nop    (0, hi_z);                 // Nop
        #tCK; nop    (0, hi_z);                 // Nop
        #tCK; auto_refresh;                     // Auto Refresh
        #tCK; nop    (0, hi_z);                 // Nop
        #tCK; nop    (0, hi_z);                 // Nop
        #tCK; nop    (0, hi_z);                 // Nop
        #tCK; nop    (0, hi_z);                 // Nop
        #tCK; nop    (0, hi_z);                 // Nop
        #tCK; nop    (0, hi_z);                 // Nop
        #tCK; nop    (0, hi_z);                 // Nop
        #tCK; nop    (0, hi_z);                 // Nop
        #tCK; nop    (0, hi_z);                 // Nop
        #tCK; load_mode_reg (50);               // Load Mode: Lat = 3, BL = 4, Seq
        #tCK; nop    (0, hi_z);                 // Nop
 
        // Write with auto precharge to bank 0 (non-interrupt)
        #tCK; active (0, 0, hi_z);              // Active: Bank = 0, Row = 0
        #tCK; nop    (0, hi_z);                 // Nop
        #tCK; nop    (0, hi_z);                 // Nop
        #tCK; write  (0, 1024, 100, 0);         // Write : Bank = 0, Col = 0, Dqm = 0, Auto Precharge
        #tCK; nop    (0, 101);                  // Nop
        #tCK; nop    (0, 102);                  // Nop
        #tCK; nop    (0, 103);                  // Nop
        #tCK; nop    (0, hi_z);                 // Nop
 
        // Write with auto precharge to bank 1 (non-interrupt)
        #tCK; active (1, 0, hi_z);              // Active: Bank = 1, Row = 0
        #tCK; nop    (0, hi_z);                 // Nop
        #tCK; nop    (0, hi_z);                 // Nop
        #tCK; write  (1, 1024, 200, 0);         // Write : Bank = 1, Col = 0, Dqm = 0, Auto precharge
        #tCK; nop    (0, 201);                  // Nop
        #tCK; nop    (0, 202);                  // Nop
        #tCK; nop    (0, 203);                  // Nop
        #tCK; nop    (0, hi_z);                 // Nop
 
        // Write with auto precharge to bank 2 (non-interrupt)
        #tCK; active (2, 0, hi_z);              // Active: Bank = 2, Row = 0
        #tCK; nop    (0, hi_z);                 // Nop
        #tCK; nop    (0, hi_z);                 // Nop
        #tCK; write  (2, 1024, 300, 0);         // Write : Bank = 2, Col = 0, Dqm = 0, Auto Precharge
        #tCK; nop    (0, 301);                  // Nop
        #tCK; nop    (0, 302);                  // Nop
        #tCK; nop    (0, 303);                  // Nop
        #tCK; nop    (0, hi_z);                 // Nop
 
        // Write with auto precharge to bank 3 (non-interrupt)
        #tCK; active (3, 0, hi_z);              // Active: Bank = 3, Row = 0
        #tCK; nop    (0, hi_z);                 // Nop
        #tCK; nop    (0, hi_z);                 // Nop
        #tCK; write  (3, 1024, 400, 0);         // Write : Bank = 3, Col = 0, Dqm = 0, Auto precharge
        #tCK; nop    (0, 401);                  // Nop
        #tCK; nop    (0, 402);                  // Nop
        #tCK; nop    (0, 403);                  // Nop
        #tCK; nop    (0, hi_z);                 // Nop
 
        // Read with auto precharge to bank 0 (non-interrupt)
        #tCK; active (0, 0, hi_z);              // Active: Bank = 0, Row = 0
        #tCK; nop    (0, hi_z);                 // Nop
        #tCK; nop    (0, hi_z);                 // Nop
        #tCK; read   (0, 1024, hi_z, 0);        // Read  : Bank = 0, Col = 0, Dqm = 0, Auto precharge
        #tCK; nop    (0, hi_z);                 // Nop
        #tCK; nop    (0, hi_z);                 // Nop
        #tCK; nop    (0, hi_z);                 // Nop
        #tCK; nop    (0, hi_z);                 // Nop
 
        // Read with auto precharge to bank 1 (non-interrupt)
        #tCK; active (1, 0, hi_z);              // Active: Bank = 1, Row = 0
        #tCK; nop    (0, hi_z);                 // Nop
        #tCK; nop    (0, hi_z);                 // Nop
        #tCK; read   (1, 1024, hi_z, 0);        // Read  : Bank = 1, Col = 0, Dqm = 0, Auto precharge
        #tCK; nop    (0, hi_z);                 // Nop
        #tCK; nop    (0, hi_z);                 // Nop
        #tCK; nop    (0, hi_z);                 // Nop
        #tCK; nop    (0, hi_z);                 // Nop
 
        // Read with auto precharge to bank 2 (non-interrupt)
        #tCK; active (2, 0, hi_z);              // Active: Bank = 2, Row = 0
        #tCK; nop    (0, hi_z);                 // Nop
        #tCK; nop    (0, hi_z);                 // Nop
        #tCK; read   (2, 1024, hi_z, 0);        // Read  : Bank = 2, Col = 0, Dqm = 0, Auto precharge
        #tCK; nop    (0, hi_z);                 // Nop
        #tCK; nop    (0, hi_z);                 // Nop
        #tCK; nop    (0, hi_z);                 // Nop
        #tCK; nop    (0, hi_z);                 // Nop
 
        // Read with auto precharge to bank 3 (non-interrupt)
        #tCK; active (3, 0, hi_z);              // Active: Bank = 3, Row = 0
        #tCK; nop    (0, hi_z);                 // Nop
        #tCK; nop    (0, hi_z);                 // Nop
        #tCK; read   (3, 1024, hi_z, 0);        // Read  : Bank = 3, Col = 0, Dqm = 0, Auto precharge
        #tCK; nop    (0, hi_z);                 // Nop
        #tCK; nop    (0, hi_z);                 // Nop
        #tCK; nop    (0, hi_z);                 // Nop
        #tCK; nop    (0, hi_z);                 // Nop
 
        #tCK; nop    (0, hi_z);                 // Nop
        #tCK; nop    (0, hi_z);                 // Nop
        #tCK; nop    (0, hi_z);                 // Nop
        #tCK;
    end
$stop;
$finish;
end
 
endmodule
 
 

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[/] [hssdrc/] [trunk/] [core/] [test.v] - Blame information for rev 3

Line No.	Rev	Author	Line
1	2	des00	`// Testbench for Micron SDR SDRAM Verilog models`
2
3			`timescale 1ns / 1ps
4
5			`module test;`
6
7			`reg [31 : 0] dq; // SDRAM I/O`
8			`reg [10 : 0] addr; // SDRAM Address`
9			`reg [1 : 0] ba; // Bank Address`
10			`reg clk; // Clock`
11			`reg cke; // Synchronous Clock Enable`
12			`reg cs_n; // CS#`
13			`reg ras_n; // RAS#`
14			`reg cas_n; // CAS#`
15			`reg we_n; // WE#`
16			`reg [3 : 0] dqm; // I/O Mask`
17
18			`wire [31 : 0] DQ = dq;`
19
20			`parameter hi_z = 32'bz; // Hi-Z`
21
22			`parameter tCK = 10; // Clock Period`
23
24			`mt48lc2m32b2 sdram0 (DQ, addr, ba, clk, cke, cs_n, ras_n, cas_n, we_n, dqm);`
25
26			`initial begin`
27			`clk = 1'b0;`
28			`cke = 1'b0;`
29			`cs_n = 1'b1;`
30			`dq = hi_z;`
31			`end`
32
33			`always #5 clk = ~clk;`
34
35			`/*`
36			`always @ (posedge clk) begin`
37			`$strobe("at time %t clk=%b cke=%b CS#=%b RAS#=%b CAS#=%b WE#=%b dqm=%b addr=%b ba=%b DQ=%d",`
38			`$time, clk, cke, cs_n, ras_n, cas_n, we_n, dqm, addr, ba, DQ);`
39			`end`
40			`*/`
41
42			`task active;`
43			`input [1 : 0] bank;`
44			`input [10 : 0] row;`
45			`input [31 : 0] dq_in;`
46			`begin`
47			`cke = 1;`
48			`cs_n = 0;`
49			`ras_n = 0;`
50			`cas_n = 1;`
51			`we_n = 1;`
52			`dqm = 0;`
53			`ba = bank;`
54			`addr = row;`
55			`dq = dq_in;`
56			`end`
57			`endtask`
58
59			`task auto_refresh;`
60			`begin`
61			`cke = 1;`
62			`cs_n = 0;`
63			`ras_n = 0;`
64			`cas_n = 0;`
65			`we_n = 1;`
66			`dqm = 0;`
67			`//ba = 0;`
68			`//addr = 0;`
69			`dq = hi_z;`
70			`end`
71			`endtask`
72
73			`task burst_term;`
74			`input [31 : 0] dq_in;`
75			`begin`
76			`cke = 1;`
77			`cs_n = 0;`
78			`ras_n = 1;`
79			`cas_n = 1;`
80			`we_n = 0;`
81			`dqm = 0;`
82			`//ba = 0;`
83			`//addr = 0;`
84			`dq = dq_in;`
85			`end`
86			`endtask`
87
88			`task load_mode_reg;`
89			`input [10 : 0] op_code;`
90			`begin`
91			`cke = 1;`
92			`cs_n = 0;`
93			`ras_n = 0;`
94			`cas_n = 0;`
95			`we_n = 0;`
96			`dqm = 0;`
97			`ba = 0;`
98			`addr = op_code;`
99			`dq = hi_z;`
100			`end`
101			`endtask`
102
103			`task nop;`
104			`input [3 : 0] dqm_in;`
105			`input [31 : 0] dq_in;`
106			`begin`
107			`cke = 1;`
108			`cs_n = 0;`
109			`ras_n = 1;`
110			`cas_n = 1;`
111			`we_n = 1;`
112			`dqm = dqm_in;`
113			`//ba = 0;`
114			`//addr = 0;`
115			`dq = dq_in;`
116			`end`
117			`endtask`
118
119			`task precharge_bank_0;`
120			`input [3 : 0] dqm_in;`
121			`input [31 : 0] dq_in;`
122			`begin`
123			`cke = 1;`
124			`cs_n = 0;`
125			`ras_n = 0;`
126			`cas_n = 1;`
127			`we_n = 0;`
128			`dqm = dqm_in;`
129			`ba = 0;`
130			`addr = 0;`
131			`dq = dq_in;`
132			`end`
133			`endtask`
134
135			`task precharge_bank_1;`
136			`input [3 : 0] dqm_in;`
137			`input [31 : 0] dq_in;`
138			`begin`
139			`cke = 1;`
140			`cs_n = 0;`
141			`ras_n = 0;`
142			`cas_n = 1;`
143			`we_n = 0;`
144			`dqm = dqm_in;`
145			`ba = 1;`
146			`addr = 0;`
147			`dq = dq_in;`
148			`end`
149			`endtask`
150
151			`task precharge_bank_2;`
152			`input [3 : 0] dqm_in;`
153			`input [31 : 0] dq_in;`
154			`begin`
155			`cke = 1;`
156			`cs_n = 0;`
157			`ras_n = 0;`
158			`cas_n = 1;`
159			`we_n = 0;`
160			`dqm = dqm_in;`
161			`ba = 2;`
162			`addr = 0;`
163			`dq = dq_in;`
164			`end`
165			`endtask`
166
167			`task precharge_bank_3;`
168			`input [3 : 0] dqm_in;`
169			`input [31 : 0] dq_in;`
170			`begin`
171			`cke = 1;`
172			`cs_n = 0;`
173			`ras_n = 0;`
174			`cas_n = 1;`
175			`we_n = 0;`
176			`dqm = dqm_in;`
177			`ba = 3;`
178			`addr = 0;`
179			`dq = dq_in;`
180			`end`
181			`endtask`
182
183			`task precharge_all_bank;`
184			`input [3 : 0] dqm_in;`
185			`input [31 : 0] dq_in;`
186			`begin`
187			`cke = 1;`
188			`cs_n = 0;`
189			`ras_n = 0;`
190			`cas_n = 1;`
191			`we_n = 0;`
192			`dqm = dqm_in;`
193			`ba = 0;`
194			`addr = 1024; // A10 = 1`
195			`dq = dq_in;`
196			`end`
197			`endtask`
198
199			`task read;`
200			`input [1 : 0] bank;`
201			`input [10 : 0] column;`
202			`input [31 : 0] dq_in;`
203			`input [3 : 0] dqm_in;`
204			`begin`
205			`cke = 1;`
206			`cs_n = 0;`
207			`ras_n = 1;`
208			`cas_n = 0;`
209			`we_n = 1;`
210			`dqm = dqm_in;`
211			`ba = bank;`
212			`addr = column;`
213			`dq = dq_in;`
214			`end`
215			`endtask`
216
217			`task write;`
218			`input [1 : 0] bank;`
219			`input [10 : 0] column;`
220			`input [31 : 0] dq_in;`
221			`input [3 : 0] dqm_in;`
222			`begin`
223			`cke = 1;`
224			`cs_n = 0;`
225			`ras_n = 1;`
226			`cas_n = 0;`
227			`we_n = 0;`
228			`dqm = dqm_in;`
229			`ba = bank;`
230			`addr = column;`
231			`dq = dq_in;`
232			`end`
233			`endtask`
234
235			`initial begin`
236			`begin`
237			`// Initialize`
238			`#tCK; nop (0, hi_z); // Nop`
239			`#tCK; nop (0, hi_z); // Nop`
240			`#tCK; nop (0, hi_z); // Nop`
241			`#tCK; nop (0, hi_z); // Nop`
242			`#tCK; nop (0, hi_z); // Nop`
243			`#tCK; nop (0, hi_z); // Nop`
244			`#tCK; nop (0, hi_z); // Nop`
245			`#tCK; nop (0, hi_z); // Nop`
246			`#tCK; nop (0, hi_z); // Nop`
247			`#tCK; nop (0, hi_z); // Nop`
248			`#tCK; precharge_all_bank(0, hi_z); // Precharge ALL Bank`
249			`#tCK; nop (0, hi_z); // Nop`
250			`#tCK; nop (0, hi_z); // Nop`
251			`#tCK; nop (0, hi_z); // Nop`
252			`#tCK; nop (0, hi_z); // Nop`
253			`#tCK; auto_refresh; // Auto Refresh`
254			`#tCK; nop (0, hi_z); // Nop`
255			`#tCK; nop (0, hi_z); // Nop`
256			`#tCK; nop (0, hi_z); // Nop`
257			`#tCK; nop (0, hi_z); // Nop`
258			`#tCK; nop (0, hi_z); // Nop`
259			`#tCK; nop (0, hi_z); // Nop`
260			`#tCK; nop (0, hi_z); // Nop`
261			`#tCK; nop (0, hi_z); // Nop`
262			`#tCK; nop (0, hi_z); // Nop`
263			`#tCK; auto_refresh; // Auto Refresh`
264			`#tCK; nop (0, hi_z); // Nop`
265			`#tCK; nop (0, hi_z); // Nop`
266			`#tCK; nop (0, hi_z); // Nop`
267			`#tCK; nop (0, hi_z); // Nop`
268			`#tCK; nop (0, hi_z); // Nop`
269			`#tCK; nop (0, hi_z); // Nop`
270			`#tCK; nop (0, hi_z); // Nop`
271			`#tCK; nop (0, hi_z); // Nop`
272			`#tCK; nop (0, hi_z); // Nop`
273			`#tCK; load_mode_reg (50); // Load Mode: Lat = 3, BL = 4, Seq`
274			`#tCK; nop (0, hi_z); // Nop`
275
276			`// Write with auto precharge to bank 0 (non-interrupt)`
277			`#tCK; active (0, 0, hi_z); // Active: Bank = 0, Row = 0`
278			`#tCK; nop (0, hi_z); // Nop`
279			`#tCK; nop (0, hi_z); // Nop`
280			`#tCK; write (0, 1024, 100, 0); // Write : Bank = 0, Col = 0, Dqm = 0, Auto Precharge`
281			`#tCK; nop (0, 101); // Nop`
282			`#tCK; nop (0, 102); // Nop`
283			`#tCK; nop (0, 103); // Nop`
284			`#tCK; nop (0, hi_z); // Nop`
285
286			`// Write with auto precharge to bank 1 (non-interrupt)`
287			`#tCK; active (1, 0, hi_z); // Active: Bank = 1, Row = 0`
288			`#tCK; nop (0, hi_z); // Nop`
289			`#tCK; nop (0, hi_z); // Nop`
290			`#tCK; write (1, 1024, 200, 0); // Write : Bank = 1, Col = 0, Dqm = 0, Auto precharge`
291			`#tCK; nop (0, 201); // Nop`
292			`#tCK; nop (0, 202); // Nop`
293			`#tCK; nop (0, 203); // Nop`
294			`#tCK; nop (0, hi_z); // Nop`
295
296			`// Write with auto precharge to bank 2 (non-interrupt)`
297			`#tCK; active (2, 0, hi_z); // Active: Bank = 2, Row = 0`
298			`#tCK; nop (0, hi_z); // Nop`
299			`#tCK; nop (0, hi_z); // Nop`
300			`#tCK; write (2, 1024, 300, 0); // Write : Bank = 2, Col = 0, Dqm = 0, Auto Precharge`
301			`#tCK; nop (0, 301); // Nop`
302			`#tCK; nop (0, 302); // Nop`
303			`#tCK; nop (0, 303); // Nop`
304			`#tCK; nop (0, hi_z); // Nop`
305
306			`// Write with auto precharge to bank 3 (non-interrupt)`
307			`#tCK; active (3, 0, hi_z); // Active: Bank = 3, Row = 0`
308			`#tCK; nop (0, hi_z); // Nop`
309			`#tCK; nop (0, hi_z); // Nop`
310			`#tCK; write (3, 1024, 400, 0); // Write : Bank = 3, Col = 0, Dqm = 0, Auto precharge`
311			`#tCK; nop (0, 401); // Nop`
312			`#tCK; nop (0, 402); // Nop`
313			`#tCK; nop (0, 403); // Nop`
314			`#tCK; nop (0, hi_z); // Nop`
315
316			`// Read with auto precharge to bank 0 (non-interrupt)`
317			`#tCK; active (0, 0, hi_z); // Active: Bank = 0, Row = 0`
318			`#tCK; nop (0, hi_z); // Nop`
319			`#tCK; nop (0, hi_z); // Nop`
320			`#tCK; read (0, 1024, hi_z, 0); // Read : Bank = 0, Col = 0, Dqm = 0, Auto precharge`
321			`#tCK; nop (0, hi_z); // Nop`
322			`#tCK; nop (0, hi_z); // Nop`
323			`#tCK; nop (0, hi_z); // Nop`
324			`#tCK; nop (0, hi_z); // Nop`
325
326			`// Read with auto precharge to bank 1 (non-interrupt)`
327			`#tCK; active (1, 0, hi_z); // Active: Bank = 1, Row = 0`
328			`#tCK; nop (0, hi_z); // Nop`
329			`#tCK; nop (0, hi_z); // Nop`
330			`#tCK; read (1, 1024, hi_z, 0); // Read : Bank = 1, Col = 0, Dqm = 0, Auto precharge`
331			`#tCK; nop (0, hi_z); // Nop`
332			`#tCK; nop (0, hi_z); // Nop`
333			`#tCK; nop (0, hi_z); // Nop`
334			`#tCK; nop (0, hi_z); // Nop`
335
336			`// Read with auto precharge to bank 2 (non-interrupt)`
337			`#tCK; active (2, 0, hi_z); // Active: Bank = 2, Row = 0`
338			`#tCK; nop (0, hi_z); // Nop`
339			`#tCK; nop (0, hi_z); // Nop`
340			`#tCK; read (2, 1024, hi_z, 0); // Read : Bank = 2, Col = 0, Dqm = 0, Auto precharge`
341			`#tCK; nop (0, hi_z); // Nop`
342			`#tCK; nop (0, hi_z); // Nop`
343			`#tCK; nop (0, hi_z); // Nop`
344			`#tCK; nop (0, hi_z); // Nop`
345
346			`// Read with auto precharge to bank 3 (non-interrupt)`
347			`#tCK; active (3, 0, hi_z); // Active: Bank = 3, Row = 0`
348			`#tCK; nop (0, hi_z); // Nop`
349			`#tCK; nop (0, hi_z); // Nop`
350			`#tCK; read (3, 1024, hi_z, 0); // Read : Bank = 3, Col = 0, Dqm = 0, Auto precharge`
351			`#tCK; nop (0, hi_z); // Nop`
352			`#tCK; nop (0, hi_z); // Nop`
353			`#tCK; nop (0, hi_z); // Nop`
354			`#tCK; nop (0, hi_z); // Nop`
355
356			`#tCK; nop (0, hi_z); // Nop`
357			`#tCK; nop (0, hi_z); // Nop`
358			`#tCK; nop (0, hi_z); // Nop`
359			`#tCK;`
360			`end`
361			`$stop;`
362			`$finish;`
363			`end`
364
365			`endmodule`
366
367