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des00 |
//
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// Project : High-Speed SDRAM Controller with adaptive bank management and command pipeline
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//
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// Project Nick : HSSDRC
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//
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// Version : 1.0-beta
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//
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// Revision : $Revision: 1.1 $
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//
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// Date : $Date: 2008-03-06 13:52:43 $
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//
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// Workfile : hssdrc_access_manager.v
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//
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// Description : sdram bank access manager
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//
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// HSSDRC is licensed under MIT License
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//
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// Copyright (c) 2007-2008, Denis V.Shekhalev (des00@opencores.org)
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//
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// Permission is hereby granted, free of charge, to any person obtaining a copy of
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// this software and associated documentation files (the "Software"), to deal in
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// the Software without restriction, including without limitation the rights to
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// use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
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// the Software, and to permit persons to whom the Software is furnished to do so,
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// subject to the following conditions:
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//
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// The above copyright notice and this permission notice shall be included in all
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// copies or substantial portions of the Software.
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//
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// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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// IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
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// FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
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// COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
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// IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
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// CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
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//
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// used command sequenceces
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// 1. {pre a -> act a -> rw a} -> {pre a -> act a -> rw a }
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// -> {rw a }
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// -> {pre_all -> refr}
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// 2. {pre a -> act a -> rw a} -> {pre b -> act b -> rw b }
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// -> {act b -> rw b}
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// -> {rw b }
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// -> {pre_all -> refr}
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// 3. {pre_all -> refr} -> refr
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// -> act
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//
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// just need to control :
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// +-------------------+-------------------------+--------------------------+
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// | command | sequental decoder part | concurent/pipeline part |
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// +===================+=========================+==========================+
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// | pre [0] -> | act [0] | act [1,2,3] |
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// | pre [0] -> | | pre [1,2,3] |
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// +-------------------+-------------------------+--------------------------+
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// | pre [1] -> | act [1] | act [0,2,3] |
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// | pre [1] -> | | pre [0,2,3] |
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// +-------------------+-------------------------+--------------------------+
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// | pre [2] -> | act [2] | act [0,1,3] |
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// | pre [2] -> | | pre [0,1,3] |
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// +-------------------+-------------------------+--------------------------+
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// | pre [3] -> | act [3] | act [0,1,2] |
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// | pre [3] -> | | pre [0,1,2] |
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// +-------------------+-------------------------+--------------------------+
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// | act [0] -> | write [0] | |
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// | act [0] -> | | act [1,2,3] |
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// | act [0] -> | | pre [0,1,2,3] |
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// | act [0] -> | read [0] | |
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// +-------------------+-------------------------+--------------------------+
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// | act [1] -> | write [1] | |
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// | act [1] -> | | act [0,2,3] |
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// | act [1] -> | | pre [0,1,2,3] |
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// | act [1] -> | read [1] | |
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// +-------------------+-------------------------+--------------------------+
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// | act [2] -> | write [2] | |
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// | act [2] -> | | act [0,1,3] |
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// | act [2] -> | | pre [0,1,2,3] |
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// | act [2] -> | read [2] | |
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// +-------------------+-------------------------+--------------------------+
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// | act [3] -> | write [3] | |
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// | act [3] -> | | act [0,1,2] |
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// | act [3] -> | | pre [0,1,2,3] |
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// | act [3] -> | read [3] | |
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// +-------------------+-------------------------+--------------------------+
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// | write/read [0] -> | | pre [0,1,2,3] |
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// | write/read [0] -> | | act [1,2,3] |
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// | write/read [0] -> | | write[0,1,2,3] |
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// | write/read [0] -> | | read [0,1,2,3] |
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// +-------------------+-------------------------+--------------------------+
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// | write/read [1] -> | | pre [0,1,2,3] |
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// | write/read [1] -> | | act [0,2,3] |
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// | write/read [1] -> | | write[0,1,2,3] |
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// | write/read [1] -> | | read [0,1,2,3] |
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// +-------------------+-------------------------+--------------------------+
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// | write/read [2] -> | | pre [0,1,2,3] |
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// | write/read [2] -> | | act [0,1,3] |
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// | write/read [2] -> | | write[0,1,2,3] |
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// | write/read [2] -> | | read [0,1,2,3] |
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// +-------------------+-------------------------+--------------------------+
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// | write/read [3] -> | | pre [0,1,2,3] |
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// | write/read [3] -> | | act [0,1,2] |
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// | write/read [3] -> | | write[0,1,2,3] |
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// | write/read [3] -> | | read [0,1,2,3] |
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// +-------------------+-------------------------+--------------------------+
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// | pre_all -> | refr | |
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// | | | |
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// +-------------------+-------------------------+--------------------------+
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// | refr -> | | refr |
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// | refr -> | | act[0,1,2,3] |
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// +-------------------+-------------------------+--------------------------+
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//
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//
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//
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// +-----------------+---------------+-----------------+---------------------+-----------+
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// | past command | control tread | current command | contol time value | note |
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// +=================+===============+=================+=====================+===========+
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// | act [0] | 0 | pre [0] | Tras | |
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// | write [0] | 1 | | Twr + Burst | 1,2,3 |
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// | read [0] | 2 | | Burst | bank |
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// | pre [1,2,3] | | | 0 | is |
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// | act [1,2,3] | | | 0 | same |
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// | write [1,2,3] | | | 0 | |
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// | read [1,2,3] | | | 0 | |
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// +-----------------+---------------+-----------------+---------------------+-----------+
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// | pre [0] | 3 [1]_ | act [0] | Trp | |
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// | refr | 4 | | Trfc | 1,2,3 |
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// | act [0] | 5 | | Trc | |
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// | act [1,2,3] | 6 | | Trrd | bank |
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// | pre [1,2,3] | | | 0 | is |
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// | write [1,2,3] | | | 0 | same |
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// | read [1,2,3] | | | 0 | |
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// +-----------------+---------------+-----------------+---------------------+-----------+
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// | act [0] | 7 [1]_ | write [0] | Trcd | 1,2,3 |
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// | write [0,1,2,3] | 8 | | Burst | bank |
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// | read [0,1,2,3] | 9 | | Burst + CL + 1(?bta)| is |
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// | | | | | same |
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// +-----------------+---------------+-----------------+---------------------+-----------+
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// | act [0] | 10 [1]_ | read [0] | Trcd | 1,2,3 |
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// | write [0,1,2,3] | 11 | | Burst + 1(?bta) | bank |
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// | read [0,1,2,3] | 12 | | Burst | is |
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// | | | | | same |
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// +-----------------+---------------+-----------------+---------------------+-----------+
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// | pre_all | 13 | refr | Trp | |
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// | refr | 14 | | Trfc | |
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// +-----------------+---------------+-----------------+---------------------+-----------+
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//
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// ..[1] Trp (pre -> act) & Trcd (act -> read/write) contolled internal in decoder FSM
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//
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`include "hssdrc_timescale.vh"
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`include "hssdrc_define.vh"
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`include "hssdrc_timing.vh"
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module hssdrc_access_manager (
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clk ,
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reset ,
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sclr ,
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//
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arb_pre_all ,
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arb_refr ,
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arb_pre ,
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arb_act ,
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arb_read ,
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arb_write ,
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arb_ba ,
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arb_burst ,
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//
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am_pre_all_enable ,
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am_refr_enable ,
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am_pre_enable ,
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am_act_enable ,
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am_read_enable ,
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am_write_enable
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);
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input wire clk;
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input wire reset;
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input wire sclr;
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//--------------------------------------------------------------------------------------------------
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// interface from output arbiter
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//--------------------------------------------------------------------------------------------------
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input logic arb_pre_all ;
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input logic arb_refr ;
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input logic arb_pre ;
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input logic arb_act ;
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input logic arb_read ;
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input logic arb_write ;
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input ba_t arb_ba ;
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input sdram_burst_t arb_burst ;
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//--------------------------------------------------------------------------------------------------
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// outputs
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//--------------------------------------------------------------------------------------------------
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output logic am_pre_all_enable ;
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output logic am_refr_enable ;
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output logic [0:3] am_pre_enable ;
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output logic [0:3] am_act_enable ;
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output logic [0:3] am_read_enable ;
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output logic [0:3] am_write_enable ;
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//--------------------------------------------------------------------------------------------------
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// all timings is select using shift register techique.
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// enable is 1'b1 level on output.
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// all shift is shift rigth.
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// shift register command load pattern is 'b{{x{1'b0}}, {y{1'b1}}}
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//--------------------------------------------------------------------------------------------------
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//--------------------------------------------------------------------------------------------------
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// take into acount load shift register cycle
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//--------------------------------------------------------------------------------------------------
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localparam int cTras_m1 = cTras - 1;
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localparam int cTrfc_m1 = cTrfc - 1;
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// localparam int cTrc_m1 = cTrc - 1; tras + trp contolled
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// localparam int cTrcd_m1 = cTrcd - 1; fsm contolled
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localparam int cTwr_m1 = cTwr - 1;
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localparam int cTrp_m1 = cTrp - 1;
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localparam int cTrrd_m1 = cTrrd - 1;
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localparam int cSdramBL_m1 = cSdramBL - 1;
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//--------------------------------------------------------------------------------------------------
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// tread 0/1/2 : Tras (act -> pre) & Twr + Burst (write -> pre) & Burst (read -> write)
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// Twr + Burst & Burst control via one register becouse write/read has atomic access
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//--------------------------------------------------------------------------------------------------
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localparam int cPreActEnableLength = max(cTwr_m1 + cSdramBL_m1, cTras_m1);
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localparam int cPreRwEnableLength = max(cTwr_m1 + cSdramBL_m1, cTras_m1);
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typedef logic [cPreActEnableLength-1:0] pre_act_enable_srl_t;
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typedef logic [cPreRwEnableLength-1 :0] pre_rw_enable_srl_t;
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// to pre load patterns
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localparam pre_act_enable_srl_t cPreActEnableInitValue = {cPreActEnableLength{1'b1}};
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localparam pre_act_enable_srl_t cPreActEnableActValue = PercentRelation(cTras_m1, cPreActEnableLength);
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// to pre load patterns
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localparam pre_rw_enable_srl_t cPreRwEnableInitValue = {cPreRwEnableLength{1'b1}};
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// Remember : burst already has -1 offset (!!!!)
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function automatic pre_rw_enable_srl_t PreRwEnableWriteValue (input sdram_burst_t burst);
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PreRwEnableWriteValue = PercentRelation (cTwr_m1 + burst, cPreRwEnableLength);
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endfunction
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function automatic pre_rw_enable_srl_t PreRwEnableReadValue (input sdram_burst_t burst);
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PreRwEnableReadValue = PercentRelation (burst, cPreRwEnableLength);
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endfunction
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// each bank has own control registers
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pre_act_enable_srl_t pre_act_enable_srl [0:3];
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pre_rw_enable_srl_t pre_rw_enable_srl [0:3];
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wire [0:3] pre_enable ;
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genvar p;
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generate
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for (p = 0; p < 4; p++) begin : pre_enable_generate
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always_ff @(posedge clk or posedge reset) begin : pre_enable_shift_register
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if (reset)
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pre_act_enable_srl [p] <= cPreActEnableInitValue;
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else if (sclr)
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pre_act_enable_srl [p] <= cPreActEnableInitValue;
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else begin
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if (arb_act && (arb_ba == p))
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pre_act_enable_srl [p] <= cPreActEnableActValue;
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else
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pre_act_enable_srl [p] <= (pre_act_enable_srl [p] << 1) | 1'b1;
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end
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if (reset)
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pre_rw_enable_srl [p] <= cPreRwEnableInitValue;
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else if (sclr)
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pre_rw_enable_srl [p] <= cPreRwEnableInitValue;
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else begin
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if (arb_write && (arb_ba == p))
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pre_rw_enable_srl [p] <= PreRwEnableWriteValue (arb_burst) & ((pre_act_enable_srl [p] << 1) | 1'b1);
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else if (arb_read && (arb_ba == p))
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pre_rw_enable_srl [p] <= PreRwEnableReadValue (arb_burst) & ((pre_act_enable_srl [p] << 1) | 1'b1);
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else
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pre_rw_enable_srl [p] <= (pre_rw_enable_srl [p] << 1) | 1'b1;
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end
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end
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assign pre_enable [p] = pre_rw_enable_srl [p] [cPreRwEnableLength-1] ;
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end
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endgenerate
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//--------------------------------------------------------------------------------------------------
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// pre_all_enable has same logic as pre enable.
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// pre_all_enable == &(pre_enable), but for increase performance it have own control registers
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//--------------------------------------------------------------------------------------------------
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pre_act_enable_srl_t pre_all_act_enable_srl ;
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pre_rw_enable_srl_t pre_all_rw_enable_srl ;
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wire pre_all_enable;
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always_ff @(posedge clk or posedge reset) begin : pre_all_enable_shift_register
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if (reset)
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pre_all_act_enable_srl <= cPreActEnableInitValue;
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else if (sclr)
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pre_all_act_enable_srl <= cPreActEnableInitValue;
|
317 |
|
|
else begin
|
318 |
|
|
if (arb_act)
|
319 |
|
|
pre_all_act_enable_srl <= cPreActEnableActValue;
|
320 |
|
|
else
|
321 |
|
|
pre_all_act_enable_srl <= (pre_all_act_enable_srl << 1) | 1'b1;
|
322 |
|
|
end
|
323 |
|
|
|
324 |
|
|
|
325 |
|
|
if (reset)
|
326 |
|
|
pre_all_rw_enable_srl <= cPreRwEnableInitValue;
|
327 |
|
|
else if (sclr)
|
328 |
|
|
pre_all_rw_enable_srl <= cPreRwEnableInitValue;
|
329 |
|
|
else begin
|
330 |
|
|
if (arb_write)
|
331 |
|
|
pre_all_rw_enable_srl <= PreRwEnableWriteValue (arb_burst) & ((pre_all_act_enable_srl << 1) | 1'b1);
|
332 |
|
|
else if (arb_read)
|
333 |
|
|
pre_all_rw_enable_srl <= PreRwEnableReadValue (arb_burst) & ((pre_all_act_enable_srl << 1) | 1'b1);
|
334 |
|
|
else
|
335 |
|
|
pre_all_rw_enable_srl <= (pre_all_rw_enable_srl << 1) | 1'b1;
|
336 |
|
|
end
|
337 |
|
|
|
338 |
|
|
end
|
339 |
|
|
|
340 |
|
|
assign pre_all_enable = pre_all_rw_enable_srl [cPreRwEnableLength-1];
|
341 |
|
|
|
342 |
|
|
//--------------------------------------------------------------------------------------------------
|
343 |
|
|
// tread 4/5/6 : Trfc (refr -> act) & Trc (act -> act) & Trrd (act a -> act b)
|
344 |
|
|
// Trc don't need to be contolled, becouse Trc = Tras + Trcd
|
345 |
|
|
// Trfc & Trrd control via one register becouse refr -> any act has locked & sequental access.
|
346 |
|
|
// for Trc we can use 1 register, becouse act a -> act a is imposible sequence
|
347 |
|
|
//--------------------------------------------------------------------------------------------------
|
348 |
|
|
|
349 |
|
|
localparam int cActEnableLength = max (cTrfc_m1, cTrrd_m1);
|
350 |
|
|
|
351 |
|
|
typedef logic [cActEnableLength-1:0] act_enable_srl_t;
|
352 |
|
|
|
353 |
|
|
// to act load patterns
|
354 |
|
|
localparam act_enable_srl_t cActEnableInitValue = {cActEnableLength{1'b1}};
|
355 |
|
|
localparam act_enable_srl_t cActEnableRefrValue = PercentRelation(cTrfc_m1, cActEnableLength);
|
356 |
|
|
localparam act_enable_srl_t cActEnableActValue = PercentRelation(cTrrd_m1, cActEnableLength);
|
357 |
|
|
|
358 |
|
|
act_enable_srl_t act_enable_srl ;
|
359 |
|
|
|
360 |
|
|
wire [0:3] act_enable ;
|
361 |
|
|
|
362 |
|
|
always_ff @(posedge clk or posedge reset) begin : act_enable_shift_register
|
363 |
|
|
|
364 |
|
|
if (reset)
|
365 |
|
|
act_enable_srl <= cActEnableInitValue;
|
366 |
|
|
else if (sclr)
|
367 |
|
|
act_enable_srl <= cActEnableInitValue;
|
368 |
|
|
else begin
|
369 |
|
|
|
370 |
|
|
if (arb_refr)
|
371 |
|
|
act_enable_srl <= cActEnableRefrValue;
|
372 |
|
|
else if (arb_act)
|
373 |
|
|
act_enable_srl <= cActEnableActValue;
|
374 |
|
|
else
|
375 |
|
|
act_enable_srl <= (act_enable_srl << 1) | 1'b1;
|
376 |
|
|
|
377 |
|
|
end
|
378 |
|
|
end
|
379 |
|
|
|
380 |
|
|
assign act_enable = {4{act_enable_srl [cActEnableLength-1]}} ;
|
381 |
|
|
|
382 |
|
|
//--------------------------------------------------------------------------------------------------
|
383 |
|
|
// tread 8/9 : Burst (write -> write) & Burst + CL + BTA (read -> write).
|
384 |
|
|
// control via one register becouse write/read -> write is atomic sequental access.
|
385 |
|
|
//--------------------------------------------------------------------------------------------------
|
386 |
|
|
|
387 |
|
|
localparam int cWriteEnableLength = max (cSdramBL_m1, cSdramBL_m1 + pCL + pBTA);
|
388 |
|
|
|
389 |
|
|
typedef logic [cWriteEnableLength-1:0] write_enable_srl_t;
|
390 |
|
|
|
391 |
|
|
// to write load patterns
|
392 |
|
|
localparam write_enable_srl_t cWriteEnableInitValue = {cWriteEnableLength{1'b1}};
|
393 |
|
|
|
394 |
|
|
// Remember : burst already has -1 offset (!!!!)
|
395 |
|
|
function automatic write_enable_srl_t WriteEnableWriteValue (input sdram_burst_t burst);
|
396 |
|
|
WriteEnableWriteValue = PercentRelation(burst, cWriteEnableLength);
|
397 |
|
|
endfunction
|
398 |
|
|
|
399 |
|
|
function automatic write_enable_srl_t WriteEnableReadValue (input sdram_burst_t burst);
|
400 |
|
|
WriteEnableReadValue = PercentRelation(burst + pCL + pBTA, cWriteEnableLength);
|
401 |
|
|
endfunction
|
402 |
|
|
|
403 |
|
|
write_enable_srl_t write_enable_srl;
|
404 |
|
|
|
405 |
|
|
wire [0:3] write_enable ;
|
406 |
|
|
|
407 |
|
|
always_ff @(posedge clk or posedge reset) begin : write_enable_shift_register
|
408 |
|
|
|
409 |
|
|
if (reset)
|
410 |
|
|
write_enable_srl <= cWriteEnableInitValue;
|
411 |
|
|
else if (sclr)
|
412 |
|
|
write_enable_srl <= cWriteEnableInitValue;
|
413 |
|
|
else begin
|
414 |
|
|
if (arb_write)
|
415 |
|
|
write_enable_srl <= WriteEnableWriteValue (arb_burst);
|
416 |
|
|
else if (arb_read)
|
417 |
|
|
write_enable_srl <= WriteEnableReadValue (arb_burst);
|
418 |
|
|
else
|
419 |
|
|
write_enable_srl <= (write_enable_srl << 1) | 1'b1;
|
420 |
|
|
end
|
421 |
|
|
end
|
422 |
|
|
|
423 |
|
|
assign write_enable = {4{write_enable_srl [cWriteEnableLength-1]}};
|
424 |
|
|
|
425 |
|
|
//--------------------------------------------------------------------------------------------------
|
426 |
|
|
// tread 11/12 : Burst + BTA (write -> read) & Burst (read -> read).
|
427 |
|
|
// contorl via one register becouse write/read -> read is atomic sequental access
|
428 |
|
|
// BTA from write -> read is not need !!! becouse read have read latency !!!!
|
429 |
|
|
//--------------------------------------------------------------------------------------------------
|
430 |
|
|
|
431 |
|
|
localparam int cReadEnableLength = max(cSdramBL_m1, cSdramBL_m1);
|
432 |
|
|
|
433 |
|
|
typedef logic [cReadEnableLength-1:0] read_enable_srl_t;
|
434 |
|
|
|
435 |
|
|
// to read load patterns
|
436 |
|
|
localparam read_enable_srl_t cReadEnableInitValue = {cReadEnableLength{1'b1}};
|
437 |
|
|
// Remember : burst already has -1 offset (!!!!)
|
438 |
|
|
function automatic read_enable_srl_t ReadEnableWriteValue (input sdram_burst_t burst);
|
439 |
|
|
ReadEnableWriteValue = PercentRelation(burst, cReadEnableLength);
|
440 |
|
|
endfunction
|
441 |
|
|
|
442 |
|
|
function automatic read_enable_srl_t ReadEnableReadValue (input sdram_burst_t burst);
|
443 |
|
|
ReadEnableReadValue = PercentRelation(burst, cReadEnableLength);
|
444 |
|
|
endfunction
|
445 |
|
|
|
446 |
|
|
read_enable_srl_t read_enable_srl;
|
447 |
|
|
|
448 |
|
|
wire [0:3] read_enable ;
|
449 |
|
|
|
450 |
|
|
always_ff @(posedge clk or posedge reset) begin : read_enable_shift_register
|
451 |
|
|
|
452 |
|
|
if (reset)
|
453 |
|
|
read_enable_srl <= cReadEnableInitValue;
|
454 |
|
|
else if (sclr)
|
455 |
|
|
read_enable_srl <= cReadEnableInitValue;
|
456 |
|
|
else begin
|
457 |
|
|
if (arb_write)
|
458 |
|
|
read_enable_srl <= ReadEnableWriteValue (arb_burst);
|
459 |
|
|
else if (arb_read)
|
460 |
|
|
read_enable_srl <= ReadEnableReadValue (arb_burst);
|
461 |
|
|
else
|
462 |
|
|
read_enable_srl <= (read_enable_srl << 1) | 1'b1;
|
463 |
|
|
end
|
464 |
|
|
|
465 |
|
|
end
|
466 |
|
|
|
467 |
|
|
assign read_enable = {4{read_enable_srl [cReadEnableLength-1]}};
|
468 |
|
|
|
469 |
|
|
//--------------------------------------------------------------------------------------------------
|
470 |
|
|
// tread 13/14 : Trp (pre_all -> refr) & Trfc (refr -> refr).
|
471 |
|
|
// contol via one register becouse pre_all/refr has locked access & (pre_all -> refr) has sequental access
|
472 |
|
|
//--------------------------------------------------------------------------------------------------
|
473 |
|
|
|
474 |
|
|
localparam int cRefrEnableLength = max (cTrp_m1, cTrfc_m1);
|
475 |
|
|
|
476 |
|
|
typedef logic [cRefrEnableLength-1:0] refr_enable_srl_t;
|
477 |
|
|
|
478 |
|
|
// to refr load patterns
|
479 |
|
|
localparam refr_enable_srl_t cRefrEnableInitValue = {cRefrEnableLength{1'b1}};
|
480 |
|
|
localparam refr_enable_srl_t cRefrEnablePreAllValue = PercentRelation( cTrp_m1, cRefrEnableLength);
|
481 |
|
|
localparam refr_enable_srl_t cRefrEnableRefrValue = PercentRelation(cTrfc_m1, cRefrEnableLength);
|
482 |
|
|
|
483 |
|
|
refr_enable_srl_t refr_enable_srl;
|
484 |
|
|
|
485 |
|
|
wire refr_enable;
|
486 |
|
|
|
487 |
|
|
always_ff @(posedge clk or posedge reset) begin : refr_enable_shift_register
|
488 |
|
|
|
489 |
|
|
if (reset)
|
490 |
|
|
refr_enable_srl <= cRefrEnableInitValue;
|
491 |
|
|
else if (sclr)
|
492 |
|
|
refr_enable_srl <= cRefrEnableInitValue;
|
493 |
|
|
else begin
|
494 |
|
|
if (arb_pre_all)
|
495 |
|
|
refr_enable_srl <= cRefrEnablePreAllValue;
|
496 |
|
|
else if (arb_refr)
|
497 |
|
|
refr_enable_srl <= cRefrEnableRefrValue;
|
498 |
|
|
else
|
499 |
|
|
refr_enable_srl <= (refr_enable_srl << 1) | 1'b1;
|
500 |
|
|
end
|
501 |
|
|
|
502 |
|
|
end
|
503 |
|
|
|
504 |
|
|
assign refr_enable = refr_enable_srl [cRefrEnableLength-1];
|
505 |
|
|
|
506 |
|
|
//--------------------------------------------------------------------------------------------------
|
507 |
|
|
// output mapping
|
508 |
|
|
//--------------------------------------------------------------------------------------------------
|
509 |
|
|
|
510 |
|
|
assign am_pre_all_enable = pre_all_enable;
|
511 |
|
|
assign am_refr_enable = refr_enable;
|
512 |
|
|
assign am_act_enable = act_enable;
|
513 |
|
|
assign am_pre_enable = pre_enable;
|
514 |
|
|
assign am_write_enable = write_enable;
|
515 |
|
|
assign am_read_enable = read_enable;
|
516 |
|
|
|
517 |
|
|
//--------------------------------------------------------------------------------------------------
|
518 |
|
|
// function to generate 'b{{{data}1'b0}, {{length-data}{1'b1}}} shift register load pattern
|
519 |
|
|
//--------------------------------------------------------------------------------------------------
|
520 |
|
|
|
521 |
|
|
function automatic int unsigned PercentRelation (input int unsigned data, length);
|
522 |
|
|
int unsigned value;
|
523 |
|
|
int i;
|
524 |
|
|
int ones_num;
|
525 |
|
|
|
526 |
|
|
value = 0;
|
527 |
|
|
ones_num = length - data; // number of ones from lsb in constant vector
|
528 |
|
|
for ( i = 0; i < length; i++) begin
|
529 |
|
|
if (i < ones_num) value[i] = 1'b1;
|
530 |
|
|
else value[i] = 1'b0;
|
531 |
|
|
end
|
532 |
|
|
|
533 |
|
|
return value;
|
534 |
|
|
endfunction
|
535 |
|
|
|
536 |
|
|
|
537 |
|
|
endmodule
|
538 |
|
|
|