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des00 |
//
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// Project : High-Speed SDRAM Controller with adaptive bank management and command pipeline
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//
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// Project Nick : HSSDRC
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//
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// Version : 1.0-beta
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//
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// Revision : $Revision: 1.1 $
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//
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// Date : $Date: 2008-03-06 13:52:43 $
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//
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// Workfile : hssdrc_top.v
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//
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// Description : top level of memory controller
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//
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// HSSDRC is licensed under MIT License
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//
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// Copyright (c) 2007-2008, Denis V.Shekhalev (des00@opencores.org)
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//
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// Permission is hereby granted, free of charge, to any person obtaining a copy of
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// this software and associated documentation files (the "Software"), to deal in
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// the Software without restriction, including without limitation the rights to
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// use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
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// the Software, and to permit persons to whom the Software is furnished to do so,
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// subject to the following conditions:
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//
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// The above copyright notice and this permission notice shall be included in all
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// copies or substantial portions of the Software.
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//
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// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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// IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
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// FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
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// COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
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// IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
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// CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
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//
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`include "hssdrc_timescale.vh"
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`include "hssdrc_define.vh"
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module hssdrc_top (
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clk ,
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reset ,
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sclr ,
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sys_write ,
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sys_read ,
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sys_refr ,
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sys_rowa ,
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sys_cola ,
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sys_ba ,
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sys_burst ,
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sys_chid_i ,
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sys_wdata ,
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sys_wdatam ,
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sys_ready ,
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sys_use_wdata ,
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sys_vld_rdata ,
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sys_chid_o ,
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sys_rdata ,
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dq ,
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dqm ,
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addr ,
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ba ,
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cke ,
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cs_n ,
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ras_n ,
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cas_n ,
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we_n
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);
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input wire clk ;
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input wire reset;
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input wire sclr ;
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//--------------------------------------------------------------------------------------------------
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// system interface
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//--------------------------------------------------------------------------------------------------
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input wire sys_write ;
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input wire sys_read ;
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input wire sys_refr ;
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input rowa_t sys_rowa ;
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input cola_t sys_cola ;
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input ba_t sys_ba ;
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input burst_t sys_burst ;
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input chid_t sys_chid_i ;
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input data_t sys_wdata ;
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input datam_t sys_wdatam ;
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output logic sys_ready ;
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output logic sys_use_wdata ;
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output logic sys_vld_rdata ;
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output chid_t sys_chid_o ;
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output data_t sys_rdata ;
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//--------------------------------------------------------------------------------------------------
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// sdram interface
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//--------------------------------------------------------------------------------------------------
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inout wire [pDataBits-1:0] dq;
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output datam_t dqm;
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output sdram_addr_t addr;
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output ba_t ba;
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output logic cke;
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output logic cs_n;
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output logic ras_n;
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output logic cas_n;
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output logic we_n;
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//--------------------------------------------------------------------------------------------------
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// internal signals
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//--------------------------------------------------------------------------------------------------
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wire init_done;
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wire hssdrc_sclr;
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//--------------------------------------------------------------------------------------------------
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// refr_cnt <-> arbiter_in
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//--------------------------------------------------------------------------------------------------
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wire refr_cnt___ack ;
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wire refr_cnt___hi_req ;
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wire refr_cnt___low_req ;
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//--------------------------------------------------------------------------------------------------
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// arbiter_in <-> decoder's
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//--------------------------------------------------------------------------------------------------
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wire arbiter_in0___write ;
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wire arbiter_in0___read ;
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wire arbiter_in0___refr ;
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rowa_t arbiter_in0___rowa ;
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cola_t arbiter_in0___cola ;
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ba_t arbiter_in0___ba ;
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burst_t arbiter_in0___burst ;
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chid_t arbiter_in0___chid ;
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wire arbiter_in0___ready ;
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//
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wire arbiter_in1___write ;
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wire arbiter_in1___read ;
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wire arbiter_in1___refr ;
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rowa_t arbiter_in1___rowa ;
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cola_t arbiter_in1___cola ;
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ba_t arbiter_in1___ba ;
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burst_t arbiter_in1___burst ;
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chid_t arbiter_in1___chid ;
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wire arbiter_in1___ready ;
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//
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wire arbiter_in2___write ;
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wire arbiter_in2___read ;
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wire arbiter_in2___refr ;
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rowa_t arbiter_in2___rowa ;
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cola_t arbiter_in2___cola ;
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ba_t arbiter_in2___ba ;
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burst_t arbiter_in2___burst ;
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chid_t arbiter_in2___chid ;
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wire arbiter_in2___ready ;
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//--------------------------------------------------------------------------------------------------
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// ba_map <-> decoder's
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//--------------------------------------------------------------------------------------------------
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wire ba_map___update ;
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wire ba_map___clear ;
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ba_t ba_map___ba ;
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rowa_t ba_map___rowa ;
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wire ba_map___pre_act_rw ;
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wire ba_map___act_rw ;
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wire ba_map___rw ;
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wire ba_map___all_close ;
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//--------------------------------------------------------------------------------------------------
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// decoder's <-> arbiter_out
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//--------------------------------------------------------------------------------------------------
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wire dec0___pre_all ;
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wire dec0___refr ;
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wire dec0___pre ;
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wire dec0___act ;
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wire dec0___read ;
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wire dec0___write ;
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wire dec0___pre_all_enable ;
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wire dec0___refr_enable ;
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wire dec0___pre_enable ;
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wire dec0___act_enable ;
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wire dec0___read_enable ;
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wire dec0___write_enable ;
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wire dec0___locked ;
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wire dec0___last ;
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rowa_t dec0___rowa ;
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cola_t dec0___cola ;
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ba_t dec0___ba ;
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chid_t dec0___chid ;
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sdram_burst_t dec0___burst ;
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//
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wire dec1___pre_all ;
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wire dec1___refr ;
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wire dec1___pre ;
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wire dec1___act ;
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wire dec1___read ;
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wire dec1___write ;
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wire dec1___pre_all_enable ;
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wire dec1___refr_enable ;
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wire dec1___pre_enable ;
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wire dec1___act_enable ;
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wire dec1___read_enable ;
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wire dec1___write_enable ;
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wire dec1___locked ;
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wire dec1___last ;
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rowa_t dec1___rowa ;
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cola_t dec1___cola ;
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ba_t dec1___ba ;
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chid_t dec1___chid ;
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sdram_burst_t dec1___burst ;
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//
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wire dec2___pre_all ;
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wire dec2___refr ;
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wire dec2___pre ;
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wire dec2___act ;
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wire dec2___read ;
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wire dec2___write ;
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wire dec2___pre_all_enable ;
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wire dec2___refr_enable ;
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wire dec2___pre_enable ;
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wire dec2___act_enable ;
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wire dec2___read_enable ;
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wire dec2___write_enable ;
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wire dec2___locked ;
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wire dec2___last ;
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rowa_t dec2___rowa ;
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cola_t dec2___cola ;
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ba_t dec2___ba ;
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chid_t dec2___chid ;
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sdram_burst_t dec2___burst ;
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//--------------------------------------------------------------------------------------------------
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// access_manager -> arbiter_out
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//--------------------------------------------------------------------------------------------------
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wire access_manager___pre_all_enable ;
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wire access_manager___refr_enable ;
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wire [0:3] access_manager___pre_enable ;
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wire [0:3] access_manager___act_enable ;
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wire [0:3] access_manager___read_enable ;
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wire [0:3] access_manager___write_enable ;
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//--------------------------------------------------------------------------------------------------
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// arbiter_out -> multiplexer/access_manager
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//--------------------------------------------------------------------------------------------------
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wire arbiter_out___pre_all ;
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wire arbiter_out___refr ;
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wire arbiter_out___pre ;
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wire arbiter_out___act ;
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wire arbiter_out___read ;
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wire arbiter_out___write ;
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rowa_t arbiter_out___rowa ;
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cola_t arbiter_out___cola ;
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ba_t arbiter_out___ba ;
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chid_t arbiter_out___chid ;
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sdram_burst_t arbiter_out___burst ;
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//--------------------------------------------------------------------------------------------------
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// init_state -> multiplexer
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//--------------------------------------------------------------------------------------------------
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wire init_state___pre_all ;
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wire init_state___refr ;
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wire init_state___lmr ;
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rowa_t init_state___rowa ;
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//--------------------------------------------------------------------------------------------------
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// multiplexer -> sdram_addr_path/sdram_data_path
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//--------------------------------------------------------------------------------------------------
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wire mux___pre_all ;
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wire mux___refr ;
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wire mux___pre ;
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wire mux___act ;
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wire mux___read ;
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wire mux___write ;
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wire mux___lmr ;
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rowa_t mux___rowa ;
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cola_t mux___cola ;
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ba_t mux___ba ;
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chid_t mux___chid ;
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sdram_burst_t mux___burst ;
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//
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// this clear use to disable fsm that must be off when sdram chip is not configured
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//
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assign hssdrc_sclr = sclr | ~init_done;
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//--------------------------------------------------------------------------------------------------
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//
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//--------------------------------------------------------------------------------------------------
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hssdrc_refr_counter refr_cnt(
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.clk (clk ),
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.reset (reset),
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.sclr (hssdrc_sclr ), // use internal sclr becouse there is refresh "fsm"
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.ack (refr_cnt___ack ),
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.hi_req (refr_cnt___hi_req ),
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.low_req (refr_cnt___low_req)
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);
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//--------------------------------------------------------------------------------------------------
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| 310 |
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//
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//--------------------------------------------------------------------------------------------------
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hssdrc_arbiter_in arbiter_in (
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| 313 |
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.clk (clk ),
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| 314 |
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.reset (reset),
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| 315 |
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.sclr (hssdrc_sclr ), // use internal sclr becouse there is arbiter fsm
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| 316 |
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//
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| 317 |
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.sys_write (sys_write ) ,
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| 318 |
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.sys_read (sys_read ) ,
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| 319 |
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.sys_refr (sys_refr ) ,
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| 320 |
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.sys_rowa (sys_rowa ) ,
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| 321 |
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.sys_cola (sys_cola ) ,
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| 322 |
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.sys_ba (sys_ba ) ,
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| 323 |
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.sys_burst (sys_burst ) ,
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| 324 |
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.sys_chid_i (sys_chid_i) ,
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| 325 |
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.sys_ready (sys_ready ) ,
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| 326 |
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//
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| 327 |
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.refr_cnt_ack (refr_cnt___ack ),
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| 328 |
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.refr_cnt_hi_req (refr_cnt___hi_req ),
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| 329 |
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.refr_cnt_low_req (refr_cnt___low_req),
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| 330 |
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//
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| 331 |
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.dec0_write (arbiter_in0___write),
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| 332 |
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.dec0_read (arbiter_in0___read ),
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| 333 |
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.dec0_refr (arbiter_in0___refr ),
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| 334 |
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.dec0_rowa (arbiter_in0___rowa ),
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| 335 |
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.dec0_cola (arbiter_in0___cola ),
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| 336 |
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.dec0_ba (arbiter_in0___ba ),
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| 337 |
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.dec0_burst (arbiter_in0___burst),
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| 338 |
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.dec0_chid (arbiter_in0___chid ),
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| 339 |
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.dec0_ready (arbiter_in0___ready),
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| 340 |
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//
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| 341 |
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.dec1_write (arbiter_in1___write),
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| 342 |
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.dec1_read (arbiter_in1___read ),
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| 343 |
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.dec1_refr (arbiter_in1___refr ),
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| 344 |
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.dec1_rowa (arbiter_in1___rowa ),
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| 345 |
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.dec1_cola (arbiter_in1___cola ),
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| 346 |
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.dec1_ba (arbiter_in1___ba ),
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| 347 |
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.dec1_burst (arbiter_in1___burst),
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| 348 |
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.dec1_chid (arbiter_in1___chid ),
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| 349 |
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.dec1_ready (arbiter_in1___ready),
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| 350 |
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//
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| 351 |
|
|
.dec2_write (arbiter_in2___write),
|
| 352 |
|
|
.dec2_read (arbiter_in2___read ),
|
| 353 |
|
|
.dec2_refr (arbiter_in2___refr ),
|
| 354 |
|
|
.dec2_rowa (arbiter_in2___rowa ),
|
| 355 |
|
|
.dec2_cola (arbiter_in2___cola ),
|
| 356 |
|
|
.dec2_ba (arbiter_in2___ba ),
|
| 357 |
|
|
.dec2_burst (arbiter_in2___burst),
|
| 358 |
|
|
.dec2_chid (arbiter_in2___chid ),
|
| 359 |
|
|
.dec2_ready (arbiter_in2___ready)
|
| 360 |
|
|
);
|
| 361 |
|
|
//--------------------------------------------------------------------------------------------------
|
| 362 |
|
|
//
|
| 363 |
|
|
//--------------------------------------------------------------------------------------------------
|
| 364 |
|
|
hssdrc_ba_map ba_map (
|
| 365 |
|
|
.clk (clk ),
|
| 366 |
|
|
.reset (reset),
|
| 367 |
|
|
.sclr (hssdrc_sclr), // use internal sclr becouse there is bank access map
|
| 368 |
|
|
//
|
| 369 |
|
|
.update (ba_map___update),
|
| 370 |
|
|
.clear (ba_map___clear ),
|
| 371 |
|
|
.ba (ba_map___ba ),
|
| 372 |
|
|
.rowa (ba_map___rowa ),
|
| 373 |
|
|
//
|
| 374 |
|
|
.pre_act_rw (ba_map___pre_act_rw),
|
| 375 |
|
|
.act_rw (ba_map___act_rw ),
|
| 376 |
|
|
.rw (ba_map___rw ),
|
| 377 |
|
|
.all_close (ba_map___all_close )
|
| 378 |
|
|
);
|
| 379 |
|
|
//--------------------------------------------------------------------------------------------------
|
| 380 |
|
|
//
|
| 381 |
|
|
//--------------------------------------------------------------------------------------------------
|
| 382 |
|
|
hssdrc_decoder decoder (
|
| 383 |
|
|
.clk (clk ),
|
| 384 |
|
|
.reset (reset),
|
| 385 |
|
|
.sclr (hssdrc_sclr), // use internal sclr becouse there is decoders fsm
|
| 386 |
|
|
//
|
| 387 |
|
|
.ba_map_update (ba_map___update ),
|
| 388 |
|
|
.ba_map_clear (ba_map___clear ),
|
| 389 |
|
|
.ba_map_ba (ba_map___ba ),
|
| 390 |
|
|
.ba_map_rowa (ba_map___rowa ),
|
| 391 |
|
|
//
|
| 392 |
|
|
.ba_map_pre_act_rw (ba_map___pre_act_rw),
|
| 393 |
|
|
.ba_map_act_rw (ba_map___act_rw ),
|
| 394 |
|
|
.ba_map_rw (ba_map___rw ),
|
| 395 |
|
|
.ba_map_all_close (ba_map___all_close ),
|
| 396 |
|
|
//
|
| 397 |
|
|
.arb0_write (arbiter_in0___write),
|
| 398 |
|
|
.arb0_read (arbiter_in0___read ),
|
| 399 |
|
|
.arb0_refr (arbiter_in0___refr ),
|
| 400 |
|
|
.arb0_rowa (arbiter_in0___rowa ),
|
| 401 |
|
|
.arb0_cola (arbiter_in0___cola ),
|
| 402 |
|
|
.arb0_ba (arbiter_in0___ba ),
|
| 403 |
|
|
.arb0_burst (arbiter_in0___burst),
|
| 404 |
|
|
.arb0_chid (arbiter_in0___chid ),
|
| 405 |
|
|
.arb0_ready (arbiter_in0___ready),
|
| 406 |
|
|
//
|
| 407 |
|
|
.arb1_write (arbiter_in1___write),
|
| 408 |
|
|
.arb1_read (arbiter_in1___read ),
|
| 409 |
|
|
.arb1_refr (arbiter_in1___refr ),
|
| 410 |
|
|
.arb1_rowa (arbiter_in1___rowa ),
|
| 411 |
|
|
.arb1_cola (arbiter_in1___cola ),
|
| 412 |
|
|
.arb1_ba (arbiter_in1___ba ),
|
| 413 |
|
|
.arb1_burst (arbiter_in1___burst),
|
| 414 |
|
|
.arb1_chid (arbiter_in1___chid ),
|
| 415 |
|
|
.arb1_ready (arbiter_in1___ready),
|
| 416 |
|
|
//
|
| 417 |
|
|
.arb2_write (arbiter_in2___write),
|
| 418 |
|
|
.arb2_read (arbiter_in2___read ),
|
| 419 |
|
|
.arb2_refr (arbiter_in2___refr ),
|
| 420 |
|
|
.arb2_rowa (arbiter_in2___rowa ),
|
| 421 |
|
|
.arb2_cola (arbiter_in2___cola ),
|
| 422 |
|
|
.arb2_ba (arbiter_in2___ba ),
|
| 423 |
|
|
.arb2_burst (arbiter_in2___burst),
|
| 424 |
|
|
.arb2_chid (arbiter_in2___chid ),
|
| 425 |
|
|
.arb2_ready (arbiter_in2___ready),
|
| 426 |
|
|
//
|
| 427 |
|
|
.dec0_pre_all (dec0___pre_all ),
|
| 428 |
|
|
.dec0_refr (dec0___refr ),
|
| 429 |
|
|
.dec0_pre (dec0___pre ),
|
| 430 |
|
|
.dec0_act (dec0___act ),
|
| 431 |
|
|
.dec0_read (dec0___read ),
|
| 432 |
|
|
.dec0_write (dec0___write ),
|
| 433 |
|
|
.dec0_pre_all_enable(dec0___pre_all_enable),
|
| 434 |
|
|
.dec0_refr_enable (dec0___refr_enable ),
|
| 435 |
|
|
.dec0_pre_enable (dec0___pre_enable ),
|
| 436 |
|
|
.dec0_act_enable (dec0___act_enable ),
|
| 437 |
|
|
.dec0_read_enable (dec0___read_enable ),
|
| 438 |
|
|
.dec0_write_enable (dec0___write_enable ),
|
| 439 |
|
|
.dec0_locked (dec0___locked ),
|
| 440 |
|
|
.dec0_last (dec0___last ),
|
| 441 |
|
|
.dec0_rowa (dec0___rowa ),
|
| 442 |
|
|
.dec0_cola (dec0___cola ),
|
| 443 |
|
|
.dec0_ba (dec0___ba ),
|
| 444 |
|
|
.dec0_chid (dec0___chid ),
|
| 445 |
|
|
.dec0_burst (dec0___burst ),
|
| 446 |
|
|
//
|
| 447 |
|
|
.dec1_pre_all (dec1___pre_all ),
|
| 448 |
|
|
.dec1_refr (dec1___refr ),
|
| 449 |
|
|
.dec1_pre (dec1___pre ),
|
| 450 |
|
|
.dec1_act (dec1___act ),
|
| 451 |
|
|
.dec1_read (dec1___read ),
|
| 452 |
|
|
.dec1_write (dec1___write ),
|
| 453 |
|
|
.dec1_pre_all_enable(dec1___pre_all_enable),
|
| 454 |
|
|
.dec1_refr_enable (dec1___refr_enable ),
|
| 455 |
|
|
.dec1_pre_enable (dec1___pre_enable ),
|
| 456 |
|
|
.dec1_act_enable (dec1___act_enable ),
|
| 457 |
|
|
.dec1_read_enable (dec1___read_enable ),
|
| 458 |
|
|
.dec1_write_enable (dec1___write_enable ),
|
| 459 |
|
|
.dec1_locked (dec1___locked ),
|
| 460 |
|
|
.dec1_last (dec1___last ),
|
| 461 |
|
|
.dec1_rowa (dec1___rowa ),
|
| 462 |
|
|
.dec1_cola (dec1___cola ),
|
| 463 |
|
|
.dec1_ba (dec1___ba ),
|
| 464 |
|
|
.dec1_chid (dec1___chid ),
|
| 465 |
|
|
.dec1_burst (dec1___burst ),
|
| 466 |
|
|
//
|
| 467 |
|
|
.dec2_pre_all (dec2___pre_all ),
|
| 468 |
|
|
.dec2_refr (dec2___refr ),
|
| 469 |
|
|
.dec2_pre (dec2___pre ),
|
| 470 |
|
|
.dec2_act (dec2___act ),
|
| 471 |
|
|
.dec2_read (dec2___read ),
|
| 472 |
|
|
.dec2_write (dec2___write ),
|
| 473 |
|
|
.dec2_pre_all_enable(dec2___pre_all_enable),
|
| 474 |
|
|
.dec2_refr_enable (dec2___refr_enable ),
|
| 475 |
|
|
.dec2_pre_enable (dec2___pre_enable ),
|
| 476 |
|
|
.dec2_act_enable (dec2___act_enable ),
|
| 477 |
|
|
.dec2_read_enable (dec2___read_enable ),
|
| 478 |
|
|
.dec2_write_enable (dec2___write_enable ),
|
| 479 |
|
|
.dec2_locked (dec2___locked ),
|
| 480 |
|
|
.dec2_last (dec2___last ),
|
| 481 |
|
|
.dec2_rowa (dec2___rowa ),
|
| 482 |
|
|
.dec2_cola (dec2___cola ),
|
| 483 |
|
|
.dec2_ba (dec2___ba ),
|
| 484 |
|
|
.dec2_chid (dec2___chid ),
|
| 485 |
|
|
.dec2_burst (dec2___burst )
|
| 486 |
|
|
);
|
| 487 |
|
|
//--------------------------------------------------------------------------------------------------
|
| 488 |
|
|
//
|
| 489 |
|
|
//--------------------------------------------------------------------------------------------------
|
| 490 |
|
|
hssdrc_arbiter_out arbiter_out(
|
| 491 |
|
|
.clk (clk),
|
| 492 |
|
|
.reset (reset),
|
| 493 |
|
|
.sclr (hssdrc_sclr), // use internal sclr becouse there is arbiter fsm
|
| 494 |
|
|
//
|
| 495 |
|
|
.dec0_pre_all (dec0___pre_all ),
|
| 496 |
|
|
.dec0_refr (dec0___refr ),
|
| 497 |
|
|
.dec0_pre (dec0___pre ),
|
| 498 |
|
|
.dec0_act (dec0___act ),
|
| 499 |
|
|
.dec0_read (dec0___read ),
|
| 500 |
|
|
.dec0_write (dec0___write ),
|
| 501 |
|
|
.dec0_pre_all_enable(dec0___pre_all_enable),
|
| 502 |
|
|
.dec0_refr_enable (dec0___refr_enable ),
|
| 503 |
|
|
.dec0_pre_enable (dec0___pre_enable ),
|
| 504 |
|
|
.dec0_act_enable (dec0___act_enable ),
|
| 505 |
|
|
.dec0_read_enable (dec0___read_enable ),
|
| 506 |
|
|
.dec0_write_enable (dec0___write_enable ),
|
| 507 |
|
|
.dec0_locked (dec0___locked ),
|
| 508 |
|
|
.dec0_last (dec0___last ),
|
| 509 |
|
|
.dec0_rowa (dec0___rowa ),
|
| 510 |
|
|
.dec0_cola (dec0___cola ),
|
| 511 |
|
|
.dec0_ba (dec0___ba ),
|
| 512 |
|
|
.dec0_chid (dec0___chid ),
|
| 513 |
|
|
.dec0_burst (dec0___burst ),
|
| 514 |
|
|
//
|
| 515 |
|
|
.dec1_pre_all (dec1___pre_all ),
|
| 516 |
|
|
.dec1_refr (dec1___refr ),
|
| 517 |
|
|
.dec1_pre (dec1___pre ),
|
| 518 |
|
|
.dec1_act (dec1___act ),
|
| 519 |
|
|
.dec1_read (dec1___read ),
|
| 520 |
|
|
.dec1_write (dec1___write ),
|
| 521 |
|
|
.dec1_pre_all_enable(dec1___pre_all_enable),
|
| 522 |
|
|
.dec1_refr_enable (dec1___refr_enable ),
|
| 523 |
|
|
.dec1_pre_enable (dec1___pre_enable ),
|
| 524 |
|
|
.dec1_act_enable (dec1___act_enable ),
|
| 525 |
|
|
.dec1_read_enable (dec1___read_enable ),
|
| 526 |
|
|
.dec1_write_enable (dec1___write_enable ),
|
| 527 |
|
|
.dec1_locked (dec1___locked ),
|
| 528 |
|
|
.dec1_last (dec1___last ),
|
| 529 |
|
|
.dec1_rowa (dec1___rowa ),
|
| 530 |
|
|
.dec1_cola (dec1___cola ),
|
| 531 |
|
|
.dec1_ba (dec1___ba ),
|
| 532 |
|
|
.dec1_chid (dec1___chid ),
|
| 533 |
|
|
.dec1_burst (dec1___burst ),
|
| 534 |
|
|
//
|
| 535 |
|
|
.dec2_pre_all (dec2___pre_all ),
|
| 536 |
|
|
.dec2_refr (dec2___refr ),
|
| 537 |
|
|
.dec2_pre (dec2___pre ),
|
| 538 |
|
|
.dec2_act (dec2___act ),
|
| 539 |
|
|
.dec2_read (dec2___read ),
|
| 540 |
|
|
.dec2_write (dec2___write ),
|
| 541 |
|
|
.dec2_pre_all_enable(dec2___pre_all_enable),
|
| 542 |
|
|
.dec2_refr_enable (dec2___refr_enable ),
|
| 543 |
|
|
.dec2_pre_enable (dec2___pre_enable ),
|
| 544 |
|
|
.dec2_act_enable (dec2___act_enable ),
|
| 545 |
|
|
.dec2_read_enable (dec2___read_enable ),
|
| 546 |
|
|
.dec2_write_enable (dec2___write_enable ),
|
| 547 |
|
|
.dec2_locked (dec2___locked ),
|
| 548 |
|
|
.dec2_last (dec2___last ),
|
| 549 |
|
|
.dec2_rowa (dec2___rowa ),
|
| 550 |
|
|
.dec2_cola (dec2___cola ),
|
| 551 |
|
|
.dec2_ba (dec2___ba ),
|
| 552 |
|
|
.dec2_chid (dec2___chid ),
|
| 553 |
|
|
.dec2_burst (dec2___burst ),
|
| 554 |
|
|
//
|
| 555 |
|
|
.am_pre_all_enable (access_manager___pre_all_enable),
|
| 556 |
|
|
.am_refr_enable (access_manager___refr_enable ),
|
| 557 |
|
|
.am_pre_enable (access_manager___pre_enable ),
|
| 558 |
|
|
.am_act_enable (access_manager___act_enable ),
|
| 559 |
|
|
.am_read_enable (access_manager___read_enable ),
|
| 560 |
|
|
.am_write_enable (access_manager___write_enable ),
|
| 561 |
|
|
//
|
| 562 |
|
|
.arb_pre_all (arbiter_out___pre_all),
|
| 563 |
|
|
.arb_refr (arbiter_out___refr ),
|
| 564 |
|
|
.arb_pre (arbiter_out___pre ),
|
| 565 |
|
|
.arb_act (arbiter_out___act ),
|
| 566 |
|
|
.arb_read (arbiter_out___read ),
|
| 567 |
|
|
.arb_write (arbiter_out___write ),
|
| 568 |
|
|
.arb_rowa (arbiter_out___rowa ),
|
| 569 |
|
|
.arb_cola (arbiter_out___cola ),
|
| 570 |
|
|
.arb_ba (arbiter_out___ba ),
|
| 571 |
|
|
.arb_chid (arbiter_out___chid ),
|
| 572 |
|
|
.arb_burst (arbiter_out___burst )
|
| 573 |
|
|
);
|
| 574 |
|
|
//--------------------------------------------------------------------------------------------------
|
| 575 |
|
|
//
|
| 576 |
|
|
//--------------------------------------------------------------------------------------------------
|
| 577 |
|
|
hssdrc_access_manager access_manager (
|
| 578 |
|
|
.clk (clk ),
|
| 579 |
|
|
.reset (reset),
|
| 580 |
|
|
.sclr (hssdrc_sclr), // use internal sclr becouse there is access "fsm's"
|
| 581 |
|
|
//
|
| 582 |
|
|
.arb_pre_all (arbiter_out___pre_all),
|
| 583 |
|
|
.arb_refr (arbiter_out___refr ),
|
| 584 |
|
|
.arb_pre (arbiter_out___pre ),
|
| 585 |
|
|
.arb_act (arbiter_out___act ),
|
| 586 |
|
|
.arb_read (arbiter_out___read ),
|
| 587 |
|
|
.arb_write (arbiter_out___write ),
|
| 588 |
|
|
.arb_ba (arbiter_out___ba ),
|
| 589 |
|
|
.arb_burst (arbiter_out___burst ),
|
| 590 |
|
|
//
|
| 591 |
|
|
.am_pre_all_enable (access_manager___pre_all_enable),
|
| 592 |
|
|
.am_refr_enable (access_manager___refr_enable ),
|
| 593 |
|
|
.am_pre_enable (access_manager___pre_enable ),
|
| 594 |
|
|
.am_act_enable (access_manager___act_enable ),
|
| 595 |
|
|
.am_read_enable (access_manager___read_enable ),
|
| 596 |
|
|
.am_write_enable (access_manager___write_enable )
|
| 597 |
|
|
);
|
| 598 |
|
|
//--------------------------------------------------------------------------------------------------
|
| 599 |
|
|
//
|
| 600 |
|
|
//--------------------------------------------------------------------------------------------------
|
| 601 |
|
|
hssdrc_init_state init_state(
|
| 602 |
|
|
.clk (clk ),
|
| 603 |
|
|
.reset (reset),
|
| 604 |
|
|
.sclr (sclr ), // use external sclr becouse this is initial start fsm
|
| 605 |
|
|
.init_done (init_done),
|
| 606 |
|
|
.pre_all (init_state___pre_all),
|
| 607 |
|
|
.refr (init_state___refr ),
|
| 608 |
|
|
.lmr (init_state___lmr ),
|
| 609 |
|
|
.rowa (init_state___rowa )
|
| 610 |
|
|
);
|
| 611 |
|
|
//--------------------------------------------------------------------------------------------------
|
| 612 |
|
|
//
|
| 613 |
|
|
//--------------------------------------------------------------------------------------------------
|
| 614 |
|
|
hssdrc_mux mux (
|
| 615 |
|
|
.init_done (init_done),
|
| 616 |
|
|
//
|
| 617 |
|
|
.init_state_pre_all (init_state___pre_all),
|
| 618 |
|
|
.init_state_refr (init_state___refr ),
|
| 619 |
|
|
.init_state_lmr (init_state___lmr ),
|
| 620 |
|
|
.init_state_rowa (init_state___rowa ),
|
| 621 |
|
|
//
|
| 622 |
|
|
.arb_pre_all (arbiter_out___pre_all),
|
| 623 |
|
|
.arb_refr (arbiter_out___refr ),
|
| 624 |
|
|
.arb_pre (arbiter_out___pre ),
|
| 625 |
|
|
.arb_act (arbiter_out___act ),
|
| 626 |
|
|
.arb_read (arbiter_out___read ),
|
| 627 |
|
|
.arb_write (arbiter_out___write ),
|
| 628 |
|
|
.arb_rowa (arbiter_out___rowa ),
|
| 629 |
|
|
.arb_cola (arbiter_out___cola ),
|
| 630 |
|
|
.arb_ba (arbiter_out___ba ),
|
| 631 |
|
|
.arb_chid (arbiter_out___chid ),
|
| 632 |
|
|
.arb_burst (arbiter_out___burst ),
|
| 633 |
|
|
//
|
| 634 |
|
|
.mux_pre_all (mux___pre_all),
|
| 635 |
|
|
.mux_refr (mux___refr ),
|
| 636 |
|
|
.mux_pre (mux___pre ),
|
| 637 |
|
|
.mux_act (mux___act ),
|
| 638 |
|
|
.mux_read (mux___read ),
|
| 639 |
|
|
.mux_write (mux___write ),
|
| 640 |
|
|
.mux_lmr (mux___lmr ),
|
| 641 |
|
|
.mux_rowa (mux___rowa ),
|
| 642 |
|
|
.mux_cola (mux___cola ),
|
| 643 |
|
|
.mux_ba (mux___ba ),
|
| 644 |
|
|
.mux_chid (mux___chid ),
|
| 645 |
|
|
.mux_burst (mux___burst )
|
| 646 |
|
|
);
|
| 647 |
|
|
//--------------------------------------------------------------------------------------------------
|
| 648 |
|
|
//
|
| 649 |
|
|
//--------------------------------------------------------------------------------------------------
|
| 650 |
|
|
`ifndef HSSDRC_DQ_PIPELINE
|
| 651 |
|
|
|
| 652 |
|
|
hssdrc_data_path data_path (
|
| 653 |
|
|
.clk (clk ),
|
| 654 |
|
|
.reset (reset),
|
| 655 |
|
|
.sclr (sclr ), // use external sclr becouse there is no any fsm
|
| 656 |
|
|
//
|
| 657 |
|
|
.sys_wdata (sys_wdata ),
|
| 658 |
|
|
.sys_wdatam (sys_wdatam ),
|
| 659 |
|
|
.sys_use_wdata (sys_use_wdata),
|
| 660 |
|
|
.sys_vld_rdata (sys_vld_rdata),
|
| 661 |
|
|
.sys_chid_o (sys_chid_o ),
|
| 662 |
|
|
.sys_rdata (sys_rdata ),
|
| 663 |
|
|
//
|
| 664 |
|
|
.arb_read (mux___read ),
|
| 665 |
|
|
.arb_write (mux___write ),
|
| 666 |
|
|
.arb_chid (mux___chid ),
|
| 667 |
|
|
.arb_burst (mux___burst ),
|
| 668 |
|
|
//
|
| 669 |
|
|
.dq (dq ),
|
| 670 |
|
|
.dqm (dqm )
|
| 671 |
|
|
);
|
| 672 |
|
|
|
| 673 |
|
|
`else
|
| 674 |
|
|
|
| 675 |
|
|
hssdrc_data_path_p1 data_path_p1 (
|
| 676 |
|
|
.clk (clk ),
|
| 677 |
|
|
.reset (reset),
|
| 678 |
|
|
.sclr (sclr ), // use external sclr becouse there is no any fsm
|
| 679 |
|
|
//
|
| 680 |
|
|
.sys_wdata (sys_wdata ),
|
| 681 |
|
|
.sys_wdatam (sys_wdatam ),
|
| 682 |
|
|
.sys_use_wdata (sys_use_wdata),
|
| 683 |
|
|
.sys_vld_rdata (sys_vld_rdata),
|
| 684 |
|
|
.sys_chid_o (sys_chid_o ),
|
| 685 |
|
|
.sys_rdata (sys_rdata ),
|
| 686 |
|
|
//
|
| 687 |
|
|
.arb_read (mux___read ),
|
| 688 |
|
|
.arb_write (mux___write ),
|
| 689 |
|
|
.arb_chid (mux___chid ),
|
| 690 |
|
|
.arb_burst (mux___burst ),
|
| 691 |
|
|
//
|
| 692 |
|
|
.dq (dq ),
|
| 693 |
|
|
.dqm (dqm )
|
| 694 |
|
|
);
|
| 695 |
|
|
|
| 696 |
|
|
`endif
|
| 697 |
|
|
//--------------------------------------------------------------------------------------------------
|
| 698 |
|
|
//
|
| 699 |
|
|
//--------------------------------------------------------------------------------------------------
|
| 700 |
|
|
`ifndef HSSDRC_DQ_PIPELINE
|
| 701 |
|
|
|
| 702 |
|
|
hssdrc_addr_path addr_path(
|
| 703 |
|
|
.clk (clk ),
|
| 704 |
|
|
.reset (reset),
|
| 705 |
|
|
.sclr (sclr ), // use external sclr becouse there is no any fsm
|
| 706 |
|
|
//
|
| 707 |
|
|
.arb_pre_all (mux___pre_all),
|
| 708 |
|
|
.arb_refr (mux___refr ),
|
| 709 |
|
|
.arb_pre (mux___pre ),
|
| 710 |
|
|
.arb_act (mux___act ),
|
| 711 |
|
|
.arb_read (mux___read ),
|
| 712 |
|
|
.arb_write (mux___write ),
|
| 713 |
|
|
.arb_lmr (mux___lmr ),
|
| 714 |
|
|
.arb_rowa (mux___rowa ),
|
| 715 |
|
|
.arb_cola (mux___cola ),
|
| 716 |
|
|
.arb_ba (mux___ba ),
|
| 717 |
|
|
//
|
| 718 |
|
|
.addr (addr ),
|
| 719 |
|
|
.ba (ba ),
|
| 720 |
|
|
.cke (cke ),
|
| 721 |
|
|
.cs_n (cs_n ),
|
| 722 |
|
|
.ras_n (ras_n),
|
| 723 |
|
|
.cas_n (cas_n),
|
| 724 |
|
|
.we_n (we_n )
|
| 725 |
|
|
);
|
| 726 |
|
|
|
| 727 |
|
|
`else
|
| 728 |
|
|
|
| 729 |
|
|
hssdrc_addr_path_p1 addr_path_p1(
|
| 730 |
|
|
.clk (clk ),
|
| 731 |
|
|
.reset (reset),
|
| 732 |
|
|
.sclr (sclr ), // use external sclr becouse there is no any fsm
|
| 733 |
|
|
//
|
| 734 |
|
|
.arb_pre_all (mux___pre_all),
|
| 735 |
|
|
.arb_refr (mux___refr ),
|
| 736 |
|
|
.arb_pre (mux___pre ),
|
| 737 |
|
|
.arb_act (mux___act ),
|
| 738 |
|
|
.arb_read (mux___read ),
|
| 739 |
|
|
.arb_write (mux___write ),
|
| 740 |
|
|
.arb_lmr (mux___lmr ),
|
| 741 |
|
|
.arb_rowa (mux___rowa ),
|
| 742 |
|
|
.arb_cola (mux___cola ),
|
| 743 |
|
|
.arb_ba (mux___ba ),
|
| 744 |
|
|
//
|
| 745 |
|
|
.addr (addr ),
|
| 746 |
|
|
.ba (ba ),
|
| 747 |
|
|
.cke (cke ),
|
| 748 |
|
|
.cs_n (cs_n ),
|
| 749 |
|
|
.ras_n (ras_n),
|
| 750 |
|
|
.cas_n (cas_n),
|
| 751 |
|
|
.we_n (we_n )
|
| 752 |
|
|
);
|
| 753 |
|
|
|
| 754 |
|
|
`endif
|
| 755 |
|
|
|
| 756 |
|
|
endmodule
|
| 757 |
|
|
|
| 758 |
|
|
|
