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[/] [hssdrc/] [trunk/] [testbench/] [sdram_interpretator.sv] - Blame information for rev 4

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//
// Project      : High-Speed SDRAM Controller with adaptive bank management and command pipeline
//
// Project Nick : HSSDRC
//
// Version      : 1.0-beta
//
// Revision     : $Revision: 1.1 $
//
// Date         : $Date: 2008-03-06 13:54:00 $
//
// Workfile     : sdram_interpretator.sv
//
// Description  : testbench only sdram command decoder
//
// HSSDRC is licensed under MIT License
//
// Copyright (c) 2007-2008, Denis V.Shekhalev (des00@opencores.org)
//
// Permission  is hereby granted, free of charge, to any person obtaining a copy of
// this  software  and  associated documentation files (the "Software"), to deal in
// the  Software  without  restriction,  including without limitation the rights to
// use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
// the  Software, and to permit persons to whom the Software is furnished to do so,
// subject to the following conditions:
//
// The  above  copyright notice and this permission notice shall be included in all
// copies or substantial portions of the Software.
//
// THE  SOFTWARE  IS  PROVIDED  "AS  IS",  WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
// IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
// FOR  A  PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
// COPYRIGHT  HOLDERS  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
// IN  AN  ACTION  OF  CONTRACT,  TORT  OR  OTHERWISE,  ARISING  FROM, OUT OF OR IN
// CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
//
 
 
 
`include "hssdrc_timescale.vh"
 
module sdram_interpretator (ba, cs_n, ras_n, cas_n, we_n, a10);
 
  input wire [1:0] ba;
  input wire cs_n;
  input wire ras_n;
  input wire cas_n;
  input wire we_n;
  input wire a10;
 
  enum {
    nop,
    act0, act1, act2, act3,
    rd0, rd1, rd2, rd3,
    wr0, wr1, wr2, wr3,
    bt,
    pre0, pre1, pre2, pre3,
    prea,  arefr, lmr, inop, unknown
    } cmd_e;
 
 
  always_comb begin
    logic [3:0] tmp;
 
    tmp = {cs_n, ras_n, cas_n, we_n};
 
    cmd_e = unknown;
 
    if (cs_n)
      cmd_e = inop;
    else
      case (tmp)
        4'b0111 : cmd_e = nop;
        4'b0011 : begin
          case (ba)
            2'd1    : cmd_e = act1;
            2'd2    : cmd_e = act2;
            2'd3    : cmd_e = act3;
            default : cmd_e = act0;
          endcase
        end
        4'b0101 : begin
          case (ba)
            2'd1    : cmd_e = rd1;
            2'd2    : cmd_e = rd2;
            2'd3    : cmd_e = rd3;
            default : cmd_e = rd0;
          endcase
        end
        4'b0100 : begin
          case (ba)
            2'd1    : cmd_e = wr1;
            2'd2    : cmd_e = wr2;
            2'd3    : cmd_e = wr3;
            default : cmd_e = wr0;
          endcase
        end
        4'b0110 : cmd_e = bt;
        4'b0010 :
          if (a10)  cmd_e = prea;
          else begin
            case (ba)
              2'd1    : cmd_e = pre1;
              2'd2    : cmd_e = pre2;
              2'd3    : cmd_e = pre3;
              default : cmd_e = pre0;
            endcase
          end
        4'b0001 : cmd_e = arefr;
        4'b0000 : cmd_e = lmr;
        default : cmd_e = unknown;
      endcase
  end
 
endmodule

Line No.	Rev	Author	Line
1	2	des00	`//`
2			`// Project : High-Speed SDRAM Controller with adaptive bank management and command pipeline`
3			`//`
4			`// Project Nick : HSSDRC`
5			`//`
6			`// Version : 1.0-beta`
7			`//`
8			`// Revision : $Revision: 1.1 $`
9			`//`
10			`// Date : $Date: 2008-03-06 13:54:00 $`
11			`//`
12			`// Workfile : sdram_interpretator.sv`
13			`//`
14			`// Description : testbench only sdram command decoder`
15			`//`
16			`// HSSDRC is licensed under MIT License`
17			`//`
18			`// Copyright (c) 2007-2008, Denis V.Shekhalev (des00@opencores.org)`
19			`//`
20			`// Permission is hereby granted, free of charge, to any person obtaining a copy of`
21			`// this software and associated documentation files (the "Software"), to deal in`
22			`// the Software without restriction, including without limitation the rights to`
23			`// use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of`
24			`// the Software, and to permit persons to whom the Software is furnished to do so,`
25			`// subject to the following conditions:`
26			`//`
27			`// The above copyright notice and this permission notice shall be included in all`
28			`// copies or substantial portions of the Software.`
29			`//`
30			`// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR`
31			`// IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS`
32			`// FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR`
33			`// COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER`
34			`// IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN`
35			`// CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.`
36			`//`
37
38
39
40			`include "hssdrc_timescale.vh"
41
42			`module sdram_interpretator (ba, cs_n, ras_n, cas_n, we_n, a10);`
43
44			`input wire [1:0] ba;`
45			`input wire cs_n;`
46			`input wire ras_n;`
47			`input wire cas_n;`
48			`input wire we_n;`
49			`input wire a10;`
50
51			`enum {`
52			`nop,`
53			`act0, act1, act2, act3,`
54			`rd0, rd1, rd2, rd3,`
55			`wr0, wr1, wr2, wr3,`
56			`bt,`
57			`pre0, pre1, pre2, pre3,`
58			`prea, arefr, lmr, inop, unknown`
59			`} cmd_e;`
60
61
62			`always_comb begin`
63			`logic [3:0] tmp;`
64
65			`tmp = {cs_n, ras_n, cas_n, we_n};`
66
67			`cmd_e = unknown;`
68
69			`if (cs_n)`
70			`cmd_e = inop;`
71			`else`
72			`case (tmp)`
73			`4'b0111 : cmd_e = nop;`
74			`4'b0011 : begin`
75			`case (ba)`
76			`2'd1 : cmd_e = act1;`
77			`2'd2 : cmd_e = act2;`
78			`2'd3 : cmd_e = act3;`
79			`default : cmd_e = act0;`
80			`endcase`
81			`end`
82			`4'b0101 : begin`
83			`case (ba)`
84			`2'd1 : cmd_e = rd1;`
85			`2'd2 : cmd_e = rd2;`
86			`2'd3 : cmd_e = rd3;`
87			`default : cmd_e = rd0;`
88			`endcase`
89			`end`
90			`4'b0100 : begin`
91			`case (ba)`
92			`2'd1 : cmd_e = wr1;`
93			`2'd2 : cmd_e = wr2;`
94			`2'd3 : cmd_e = wr3;`
95			`default : cmd_e = wr0;`
96			`endcase`
97			`end`
98			`4'b0110 : cmd_e = bt;`
99			`4'b0010 :`
100			`if (a10) cmd_e = prea;`
101			`else begin`
102			`case (ba)`
103			`2'd1 : cmd_e = pre1;`
104			`2'd2 : cmd_e = pre2;`
105			`2'd3 : cmd_e = pre3;`
106			`default : cmd_e = pre0;`
107			`endcase`
108			`end`
109			`4'b0001 : cmd_e = arefr;`
110			`4'b0000 : cmd_e = lmr;`
111			`default : cmd_e = unknown;`
112			`endcase`
113			`end`
114
115			`endmodule`

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[/] [hssdrc/] [trunk/] [testbench/] [sdram_interpretator.sv] - Blame information for rev 4