OpenCores
URL https://opencores.org/ocsvn/hssdrc/hssdrc/trunk

Subversion Repositories hssdrc

[/] [hssdrc/] [trunk/] [testbench/] [sdram_tread_class.sv] - Blame information for rev 3

Details | Compare with Previous | View Log

Line No. Rev Author Line
1 2 des00
//
2
// Project      : High-Speed SDRAM Controller with adaptive bank management and command pipeline
3
//
4
// Project Nick : HSSDRC
5
//
6
// Version      : 1.0-beta
7
//
8
// Revision     : $Revision: 1.1 $
9
//
10
// Date         : $Date: 2008-03-06 13:54:00 $
11
//
12
// Workfile     : sdram_tread_class.sv
13
//
14
// Description  : virtual sdram treads using for sdram chip testing
15
//
16
// HSSDRC is licensed under MIT License
17
//
18
// Copyright (c) 2007-2008, Denis V.Shekhalev (des00@opencores.org)
19
//
20
// Permission  is hereby granted, free of charge, to any person obtaining a copy of
21
// this  software  and  associated documentation files (the "Software"), to deal in
22
// the  Software  without  restriction,  including without limitation the rights to
23
// use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
24
// the  Software, and to permit persons to whom the Software is furnished to do so,
25
// subject to the following conditions:
26
//
27
// The  above  copyright notice and this permission notice shall be included in all
28
// copies or substantial portions of the Software.
29
//
30
// THE  SOFTWARE  IS  PROVIDED  "AS  IS",  WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
31
// IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
32
// FOR  A  PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
33
// COPYRIGHT  HOLDERS  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
34
// IN  AN  ACTION  OF  CONTRACT,  TORT  OR  OTHERWISE,  ARISING  FROM, OUT OF OR IN
35
// CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
36
//
37
 
38
 
39
 
40
 
41
`include "tb_define.svh"
42
 
43
`ifndef __SDRAM_TREAD_CLASS_SV__
44
 
45
  `define __SDRAM_TREAD_CLASS_SV__
46
 
47
  class sdram_tread_class;
48
 
49
    sdram_tread_state_s_t active_tread_state [sdram_tread_ptr_t];
50
 
51
    rand sdram_tread_ptr_t curr_tread_num; // no need to constrant
52
 
53
    sdram_tread_ptr_t disable_tread_num [$];
54
 
55
    constraint select_tread { !(curr_tread_num inside {disable_tread_num}); }
56
 
57
    //
58
    //
59
    //
60
 
61
    function void Init () ;
62
      int tread_num     = 0;
63
      const int shift   = clogb2(cBaMaxValue);
64
      sdram_tread_state_s_t tread_state;
65
 
66
      if (active_tread_state.num != 0)
67
        active_tread_state.delete;
68
 
69
      if (disable_tread_num.size != 0)
70
        disable_tread_num = {};
71
 
72
      for (int rowa = 0; rowa < cRowaMaxValue; rowa++) begin
73
        for (int ba = 0; ba < cBaMaxValue; ba++) begin
74
 
75
        tread_num = (rowa << shift) + ba;
76
 
77
        tread_state = '{ba : ba, rowa : rowa, cola : 0};
78
 
79
        active_tread_state[tread_num] = tread_state;
80
 
81
        end
82
      end
83
 
84
    endfunction
85
 
86
    //
87
    //
88
    //
89
 
90
    function burst_t GetBurst (input sdram_tread_state_s_t tread_state);
91
 
92
      int max_burst;
93
 
94
      max_burst = cColaMaxValue - tread_state.cola;
95
 
96
      if (max_burst > cBurstMaxValue) max_burst = 16;
97
 
98
      assert (std::randomize(GetBurst) with {GetBurst inside {[1:max_burst]};})
99
        else $error ("burst generate error : max burst = %0d burst = %0d", max_burst, GetBurst );
100
 
101
    endfunction
102
 
103
  endclass
104
 
105
`endif

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.