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acastong |
//link_rx_transmitter.h
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/* ***** BEGIN LICENSE BLOCK *****
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* Version: MPL 1.1
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*
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* The contents of this file are subject to the Mozilla Public License Version
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* 1.1 (the "License"); you may not use this file except in compliance with
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* the License. You may obtain a copy of the License at
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* http://www.mozilla.org/MPL/
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*
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* Software distributed under the License is distributed on an "AS IS" basis,
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* WITHOUT WARRANTY OF ANY KIND, either express or implied. See the License
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* for the specific language governing rights and limitations under the
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* License.
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*
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* The Original Code is HyperTransport Tunnel IP Core.
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*
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* The Initial Developer of the Original Code is
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* Ecole Polytechnique de Montreal.
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* Portions created by the Initial Developer are Copyright (C) 2005
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* the Initial Developer. All Rights Reserved.
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*
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* Contributor(s):
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* Ami Castonguay <acastong@grm.polymtl.ca>
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*
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* Alternatively, the contents of this file may be used under the terms
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* of the Polytechnique HyperTransport Tunnel IP Core Source Code License
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* (the "PHTICSCL License", see the file PHTICSCL.txt), in which case the
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* provisions of PHTICSCL License are applicable instead of those
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* above. If you wish to allow use of your version of this file only
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* under the terms of the PHTICSCL License and not to allow others to use
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* your version of this file under the MPL, indicate your decision by
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* deleting the provisions above and replace them with the notice and
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* other provisions required by the PHTICSCL License. If you do not delete
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* the provisions above, a recipient may use your version of this file
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* under either the MPL or the PHTICSCL License."
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*
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* ***** END LICENSE BLOCK ***** */
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#ifndef LINK_RX_TRANSMITTER_H
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#define LINK_RX_TRANSMITTER_H
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#include "../../../rtl/systemc/core_synth/synth_datatypes.h"
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///Allows to transmit data to the link in order to test it
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/**
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@class link_rx_transmitter
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@author Ami Castonguay
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@description
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This is a module that takes care of transmitting data to the
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link in order to test it. It takes care of sending an initial
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sequence and afterwards transmitting valid data. It does not
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take care of CRC's.
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The transmitter can run at various bit-widths and also at
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different offsets. What is meant by offset is that when data
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is received by the HT tunnel, it is deserialized to 32 bits from
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its original bit-width. Because of this deserialization, the
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final data might not be alligned naturally (the received 32-bit
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might contain the end of a dword and the beggining of another
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dword). The transmitter takes care of simulating this.
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Natural allignment (offset of 0) is this for a 4 bit link:
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output0: 28 ... 9 5 1
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output1: 29 ... 10 6 2
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output2: 30 ... 11 7 3
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output3: 31 ... 12 8 4
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Offset of 2 is this for a 4 bit link:
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output0: 20 ... 9 5 1 + 28 24
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output1: 21 ... 10 6 2 + 29 25
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output2: 22 ... 11 7 3 + 30 26
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output3: 23 ... 12 8 4 + 31 27
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The (+) marks a change in data dword, even if it's received in the same
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phy_cad_lk.
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*/
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class link_rx_transmitter : public sc_module{
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public:
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sc_in<bool > clk;
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///CTL value sent to the HT tunnel
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sc_out<sc_bv<CAD_IN_DEPTH> > phy_ctl_lk;
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///CAD value sent to the tunnel
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/** Every element of the array represent one input of the tunnel
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that was deserialized to a factor of CAD_IN_DEPTH*/
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sc_out<sc_bv<CAD_IN_DEPTH> > phy_cad_lk[CAD_IN_WIDTH];
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///If CAD and CTL values are available to be consumed
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/** True when a dword is sent through the transmitter, false
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otherwise*/
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sc_out<bool> phy_available_lk;
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///The bit-width of the link
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int bit_width;
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///The offset : how the data is offset from its natural allignment
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int transmission_offset;
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///The last data sent, so that it can be used when sending the data with offset
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sc_bv<32> last_sent_dword;
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///The last lctl sent, so that it can be used when sending the data with offset
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bool last_sent_lctl;
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///The last hctl sent, so that it can be used when sending the data with offset
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bool last_sent_hctl;
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#ifndef INTERNAL_SHIFTER_ALIGNMENT
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///High speed deserializer should stall shifting bits for lk_deser_stall_cycles_phy cycles
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/** Cannot be asserted with a lk_deser_stall_cycles_phy value of 0*/
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sc_in<bool > lk_deser_stall_phy;
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///Number of bit times to stall deserializing incoming data when lk_deser_stall_phy is asserted
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sc_in<sc_uint<LOG2_CAD_IN_DEPTH> > lk_deser_stall_cycles_phy;
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void realign();
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SC_HAS_PROCESS(link_rx_transmitter);
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#endif
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///Constructor
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link_rx_transmitter(sc_module_name name);
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///Sends the correct CAD and CTL values to initialize the link
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/**
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@param offset1 Offset at the beggining of the init sequence
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@param offset2 Offset at the end of the init sequence. It does not
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have to be the same as offset1. offset2 will be the final offset
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that will be kept after the init sequence is done
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*/
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void send_init_sequence(int offset1, int offset2);
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///Sends a dword on the link
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/**
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@param dword The dword to send
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@param lctl The CTL value sent with the dword for first half of transmission
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@param hctl The CTL value sent with the dword for last half of transmission
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@param ctl_error If a CTL transition error should be introduced. A
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transition at another moment than the half of the transmission will
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be made (which is illegal in HT)
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*/
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void send_dword_link(const sc_bv<32> & dword,
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bool lctl, bool hctl, bool ctl_error = false);
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///Send reset signaling
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void send_initial_value(int nb_cyles);
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};
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#endif
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