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acastong |
//main.cpp
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/* ***** BEGIN LICENSE BLOCK *****
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* Version: MPL 1.1
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*
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* The contents of this file are subject to the Mozilla Public License Version
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* 1.1 (the "License"); you may not use this file except in compliance with
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* the License. You may obtain a copy of the License at
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* http://www.mozilla.org/MPL/
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*
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* Software distributed under the License is distributed on an "AS IS" basis,
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* WITHOUT WARRANTY OF ANY KIND, either express or implied. See the License
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* for the specific language governing rights and limitations under the
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* License.
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*
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* The Original Code is HyperTransport Tunnel IP Core.
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*
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* The Initial Developer of the Original Code is
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* Ecole Polytechnique de Montreal.
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* Portions created by the Initial Developer are Copyright (C) 2005
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* the Initial Developer. All Rights Reserved.
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*
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* Contributor(s):
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* Ami Castonguay <acastong@grm.polymtl.ca>
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*
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* Alternatively, the contents of this file may be used under the terms
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* of the Polytechnique HyperTransport Tunnel IP Core Source Code License
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* (the "PHTICSCL License", see the file PHTICSCL.txt), in which case the
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* provisions of PHTICSCL License are applicable instead of those
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* above. If you wish to allow use of your version of this file only
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* under the terms of the PHTICSCL License and not to allow others to use
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* your version of this file under the MPL, indicate your decision by
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* deleting the provisions above and replace them with the notice and
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* other provisions required by the PHTICSCL License. If you do not delete
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* the provisions above, a recipient may use your version of this file
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* under either the MPL or the PHTICSCL License."
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*
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* ***** END LICENSE BLOCK ***** */
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//Main for link_frame_rx_l3 testbench
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#ifndef SC_USER_DEFINED_MAX_NUMBER_OF_PROCESSES
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#define SC_USER_DEFINED_MAX_NUMBER_OF_PROCESSES
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#define SC_VC6_MAX_NUMBER_OF_PROCESSES 20
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#endif
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#include <systemc.h>
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#include "../../../rtl/systemc/core_synth/synth_datatypes.h"
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#include "../../../rtl/systemc/core_synth/constants.h"
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#include "../../../rtl/systemc/link_l2/link_frame_tx_l3.h"
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#include "link_frame_tx_l3_tb.h"
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#include <iostream>
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#include <string>
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#include <sstream>
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#include <iomanip>
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using namespace std;
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int sc_main( int argc, char* argv[] ){
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//The Design Under Test
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link_frame_tx_l3* dut = new link_frame_tx_l3("link_frame_tx_l3");
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//The TestBench
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link_frame_tx_l3_tb* tb = new link_frame_tx_l3_tb("link_frame_tx_l3_tb");
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//Signals used to link the design to the testbench
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sc_clock clk("clk", 1); // system clk
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sc_signal<sc_bv<CAD_OUT_DEPTH> > lk_ctl_phy;
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sc_signal<sc_bv<CAD_OUT_DEPTH> > lk_cad_phy[CAD_OUT_WIDTH];
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sc_signal<bool> phy_consume_lk;
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sc_signal<bool > disable_drivers;
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sc_signal<sc_bv<32> > cad_to_frame;
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sc_signal<bool> lctl_to_frame;
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sc_signal<bool > hctl_to_frame;
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sc_signal<bool> tx_consume_data;
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sc_signal<bool> resetx;
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sc_signal<bool> pwrok;
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sc_signal<bool> ldtstopx;
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sc_signal<sc_bv<3> > csr_tx_link_width_lk;
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sc_signal<bool > csr_end_of_chain;
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sc_signal<bool> csr_transmitter_off_lk;
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sc_signal<bool> csr_ldtstop_tristate_enable_lk;
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sc_signal<bool> ldtstop_disconnect_tx;
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sc_signal<bool> rx_waiting_for_ctl_tx;
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#ifdef RETRY_MODE_ENABLED
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sc_signal<bool> fc_disconnect_lk;
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#endif
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sc_signal<bool> csr_extented_ctl_lk;
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//Connect the design
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dut->clk(clk);
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dut->lk_ctl_phy(lk_ctl_phy);
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for(int n = 0; n < CAD_OUT_WIDTH; n++)
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dut->lk_cad_phy[n](lk_cad_phy[n]);
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dut->phy_consume_lk(phy_consume_lk);
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dut->disable_drivers(disable_drivers);
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dut->cad_to_frame(cad_to_frame);
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dut->lctl_to_frame(lctl_to_frame);
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dut->hctl_to_frame(hctl_to_frame);
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dut->tx_consume_data(tx_consume_data);
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dut->resetx(resetx);
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dut->ldtstopx(ldtstopx);
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dut->csr_tx_link_width_lk(csr_tx_link_width_lk);
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dut->csr_end_of_chain(csr_end_of_chain);
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dut->csr_transmitter_off_lk(csr_transmitter_off_lk);
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dut->csr_ldtstop_tristate_enable_lk(csr_ldtstop_tristate_enable_lk);
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dut->ldtstop_disconnect_tx(ldtstop_disconnect_tx);
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dut->rx_waiting_for_ctl_tx(rx_waiting_for_ctl_tx);
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#ifdef RETRY_MODE_ENABLED
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dut->tx_retry_disconnect(fc_disconnect_lk);
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#endif
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dut->csr_extented_ctl_lk(csr_extented_ctl_lk);
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//Connect the testbench
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tb->clk(clk);
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tb->lk_ctl_phy(lk_ctl_phy);
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for(int n = 0; n < CAD_OUT_WIDTH; n++)
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tb->lk_cad_phy[n](lk_cad_phy[n]);
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tb->phy_consume_lk(phy_consume_lk);
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tb->disable_drivers(disable_drivers);
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tb->cad_to_frame(cad_to_frame);
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tb->lctl_to_frame(lctl_to_frame);
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tb->hctl_to_frame(hctl_to_frame);
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tb->tx_consume_data(tx_consume_data);
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tb->resetx(resetx);
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tb->pwrok(pwrok);
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tb->ldtstopx(ldtstopx);
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tb->csr_tx_link_width_lk(csr_tx_link_width_lk);
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tb->csr_end_of_chain(csr_end_of_chain);
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tb->ldtstop_disconnect_tx(ldtstop_disconnect_tx);
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tb->rx_waiting_for_ctl_tx(rx_waiting_for_ctl_tx);
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#ifdef RETRY_MODE_ENABLED
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tb->fc_disconnect_lk(fc_disconnect_lk);
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#endif
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// tracing:
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// trace file creation
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sc_trace_file *tf = sc_create_vcd_trace_file("sim_link_frame_tx_l3");
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// External Signals
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sc_trace(tf, clk, "clk");
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sc_trace(tf,lk_ctl_phy,"lk_ctl_phy");
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for(int n = 0; n < CAD_OUT_WIDTH; n++){
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ostringstream s;
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s << "lk_cad_phy(" << n << ")";
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sc_trace(tf,lk_cad_phy[n], s.str().c_str());
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}
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sc_trace(tf,phy_consume_lk,"phy_consume_lk");
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sc_trace(tf,disable_drivers,"disable_drivers");
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sc_trace(tf,cad_to_frame,"cad_to_frame");
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sc_trace(tf,lctl_to_frame,"lctl_to_frame");
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sc_trace(tf,hctl_to_frame,"hctl_to_frame");
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sc_trace(tf,tx_consume_data,"tx_consume_data");
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sc_trace(tf,resetx,"resetx");
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sc_trace(tf,pwrok,"pwrok");
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sc_trace(tf,ldtstopx,"ldtstopx");
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sc_trace(tf,csr_tx_link_width_lk,"csr_tx_link_width_lk");
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sc_trace(tf,csr_end_of_chain,"csr_end_of_chain");
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sc_trace(tf,ldtstop_disconnect_tx,"ldtstop_disconnect_tx");
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sc_trace(tf,rx_waiting_for_ctl_tx,"rx_waiting_for_ctl_tx");
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#ifdef RETRY_MODE_ENABLED
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sc_trace(tf,fc_disconnect_lk,"fc_disconnect_lk");
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#endif
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//------------------------------------------
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// Start simulation
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//------------------------------------------
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cout << "Debut de la simulation" << endl;
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sc_start(14000/CAD_OUT_DEPTH);
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sc_close_vcd_trace_file(tf);
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cout << "fin de la simulation" << endl;
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delete dut;
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delete tb;
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return 0;
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}
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