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acastong |
//main.cpp
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/* ***** BEGIN LICENSE BLOCK *****
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* Version: MPL 1.1
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*
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* The contents of this file are subject to the Mozilla Public License Version
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* 1.1 (the "License"); you may not use this file except in compliance with
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* the License. You may obtain a copy of the License at
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* http://www.mozilla.org/MPL/
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*
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* Software distributed under the License is distributed on an "AS IS" basis,
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* WITHOUT WARRANTY OF ANY KIND, either express or implied. See the License
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* for the specific language governing rights and limitations under the
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* License.
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*
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* The Original Code is HyperTransport Tunnel IP Core.
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*
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* The Initial Developer of the Original Code is
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* Ecole Polytechnique de Montreal.
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* Portions created by the Initial Developer are Copyright (C) 2005
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* the Initial Developer. All Rights Reserved.
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*
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* Contributor(s):
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* Ami Castonguay <acastong@grm.polymtl.ca>
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*
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* Alternatively, the contents of this file may be used under the terms
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* of the Polytechnique HyperTransport Tunnel IP Core Source Code License
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* (the "PHTICSCL License", see the file PHTICSCL.txt), in which case the
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* provisions of PHTICSCL License are applicable instead of those
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* above. If you wish to allow use of your version of this file only
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* under the terms of the PHTICSCL License and not to allow others to use
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* your version of this file under the MPL, indicate your decision by
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* deleting the provisions above and replace them with the notice and
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* other provisions required by the PHTICSCL License. If you do not delete
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* the provisions above, a recipient may use your version of this file
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* under either the MPL or the PHTICSCL License."
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*
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* ***** END LICENSE BLOCK ***** */
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//Main for link_frame_rx_l3 testbench
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#ifndef SC_USER_DEFINED_MAX_NUMBER_OF_PROCESSES
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#define SC_USER_DEFINED_MAX_NUMBER_OF_PROCESSES
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#define SC_VC6_MAX_NUMBER_OF_PROCESSES 20
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#endif
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#include <systemc.h>
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#include "../../../rtl/systemc/core_synth/synth_datatypes.h"
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#include "../../../rtl/systemc/core_synth/constants.h"
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#include "../../../rtl/systemc/link_l2/link_l2.h"
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#include "../../../rtl/systemc/link_l2/link_frame_rx_l3.h"
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#include "link_l2_tb.h"
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#include <iostream>
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#include <string>
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#include <sstream>
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#include <iomanip>
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using namespace std;
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int sc_main( int argc, char* argv[] ){
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//The Design Under Test
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link_l2* dut = new link_l2("link_l2");
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//The TestBench
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link_l2_tb* tb = new link_l2_tb("link_l2_tb");
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//Signals used to link the design to the testbench
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sc_clock clk("clk", 1); // system clk
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sc_signal<bool> resetx;
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sc_signal<bool> pwrok;
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sc_signal<bool> ldtstopx;
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sc_signal<sc_bv<CAD_IN_DEPTH> > phy_ctl_lk;
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sc_signal<sc_bv<CAD_IN_DEPTH> > phy_cad_lk[CAD_IN_WIDTH];
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sc_signal<bool> phy_available_lk;
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sc_signal<sc_bv<CAD_OUT_DEPTH> > lk_ctl_phy;
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sc_signal<sc_bv<CAD_OUT_DEPTH> > lk_cad_phy[CAD_OUT_WIDTH];
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sc_signal<bool> phy_consume_lk;
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sc_signal<bool> lk_disable_drivers_phy;
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sc_signal<bool> lk_disable_receivers_phy;
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/**
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Data to be sent to the next link
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This data comes from the flow control
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@{
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*/
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///Dword to send
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sc_signal<sc_bv<32> > fc_dword_lk;
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///The LCTL value associated with the dword to send
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sc_signal<bool> fc_lctl_lk;
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///The HCTL value associated with the dword to send
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sc_signal<bool> fc_hctl_lk;
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///To consume the data from the flow control
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sc_signal<bool> lk_consume_fc;
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///@}
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//*******************************
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// Signals from link
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//*******************************
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///Bit vector output for command decoder
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sc_signal< sc_bv<32> > lk_dword_cd;
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///Control bit
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sc_signal< bool > lk_hctl_cd;
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///Control bit
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sc_signal< bool > lk_lctl_cd;
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///FIFO is ready to be read from
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sc_signal< bool > lk_available_cd;
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/**
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Link widths
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000 8 bits
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100 2 bits
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101 4 bits
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111 Link physically not connected
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@{
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*/
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///The link width for the RX side
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sc_signal<sc_bv<3> > csr_rx_link_width_lk;
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///The link width for the TX side
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sc_signal<sc_bv<3> > csr_tx_link_width_lk;
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///@}
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//If the chain is being synched
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sc_signal<bool> csr_sync;
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///If this link should be inactive because it is the end of chain
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sc_signal<bool> csr_end_of_chain;
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///To update the link width registered in the CSR with the new value
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sc_signal<bool> lk_update_link_width_csr;
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///The link width that is being sampled
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sc_signal<sc_bv<3> > lk_sampled_link_width_csr;
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///A protocol error has been detected
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sc_signal<bool> lk_protocol_error_csr;
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///Force CRC errors to be generated
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sc_signal<bool> csr_crc_force_error_lk;
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///To turn off the transmitter
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sc_signal<bool> csr_transmitter_off_lk;
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///Hold CTL longer in the ini sequemce
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sc_signal<bool> csr_extented_ctl_lk;
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///The timeout for CTL being low too long is extended
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sc_signal<bool> csr_extended_ctl_timeout_lk;
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///If we are enabled to tristated the drivers when in ldtstop
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sc_signal<bool> csr_ldtstop_tristate_enable_lk;
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///CRC error detected on link
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sc_signal<bool> lk_crc_error_csr;
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///Update the link failure flag in CSR with the lk_link_failure_csr signal
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sc_signal<bool> lk_update_link_failure_property_csr;
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#ifdef RETRY_MODE_ENABLED
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///Start a retry sequence
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sc_signal<bool> lk_initiate_retry_disconnect;
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///Command decoder commands a retry disconnect
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sc_signal<bool> cd_initiate_retry_disconnect;
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///The flow control asks us to disconnect the link
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sc_signal<bool> fc_disconnect_lk;
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///If we are in the retry mode
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sc_signal<bool > csr_retry;
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#endif
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///RX link is connected (identical to lk_initialization_complete_csr)
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sc_signal<bool> lk_rx_connected;
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///This signal should only be evaluated at lk_update_link_failure_property_csr
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sc_signal<bool> lk_link_failure_csr;
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//A sync error has been detected
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// - Not used anymore, sync only detected through standard decode logic
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//sc_signal<bool> lk_sync_detected_csr;
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///Command decoder commands a ltdstop disconnect
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sc_signal<bool> cd_initiate_nonretry_disconnect_lk;
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#ifndef INTERNAL_SHIFTER_ALIGNMENT
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sc_signal<bool > lk_deser_stall_phy;
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///Number of bit times to stall deserializing incoming data when lk_deser_stall_phy is asserted
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sc_signal<sc_uint<LOG2_CAD_IN_DEPTH> > lk_deser_stall_cycles_phy;
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#endif
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//Connect the design
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dut->clk(clk);
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dut->resetx(resetx);
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dut->pwrok(pwrok);
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dut->ldtstopx(ldtstopx);
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dut->phy_ctl_lk(phy_ctl_lk);
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for(int n = 0; n < CAD_IN_WIDTH; n++)
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dut->phy_cad_lk[n](phy_cad_lk[n]);
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dut->phy_available_lk(phy_available_lk);
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dut->lk_ctl_phy(lk_ctl_phy);
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for(int n = 0; n < CAD_OUT_WIDTH; n++)
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dut->lk_cad_phy[n](lk_cad_phy[n]);
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dut->phy_consume_lk(phy_consume_lk);
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dut->lk_disable_drivers_phy(lk_disable_drivers_phy);
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dut->lk_disable_receivers_phy(lk_disable_receivers_phy);
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dut->fc_dword_lk(fc_dword_lk);
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dut->fc_lctl_lk(fc_lctl_lk);
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dut->fc_hctl_lk(fc_hctl_lk);
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dut->lk_consume_fc(lk_consume_fc);
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dut->lk_dword_cd(lk_dword_cd);
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dut->lk_hctl_cd(lk_hctl_cd);
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dut->lk_lctl_cd(lk_lctl_cd);
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dut->lk_available_cd(lk_available_cd);
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dut->csr_rx_link_width_lk(csr_rx_link_width_lk);
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dut->csr_tx_link_width_lk(csr_tx_link_width_lk);
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dut->csr_sync(csr_sync);
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dut->csr_end_of_chain(csr_end_of_chain);
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dut->lk_update_link_width_csr(lk_update_link_width_csr);
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dut->lk_sampled_link_width_csr(lk_sampled_link_width_csr);
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dut->lk_protocol_error_csr(lk_protocol_error_csr);
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dut->csr_crc_force_error_lk(csr_crc_force_error_lk);
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dut->csr_transmitter_off_lk(csr_transmitter_off_lk);
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dut->csr_extented_ctl_lk(csr_extented_ctl_lk);
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dut->csr_extended_ctl_timeout_lk(csr_extended_ctl_timeout_lk);
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dut->csr_ldtstop_tristate_enable_lk(csr_ldtstop_tristate_enable_lk);
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dut->lk_crc_error_csr(lk_crc_error_csr);
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dut->lk_update_link_failure_property_csr(lk_update_link_failure_property_csr);
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#ifdef RETRY_MODE_ENABLED
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dut->lk_initiate_retry_disconnect(lk_initiate_retry_disconnect);
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dut->cd_initiate_retry_disconnect(cd_initiate_retry_disconnect);
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dut->fc_disconnect_lk(fc_disconnect_lk);
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dut->csr_retry(csr_retry);
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#endif
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dut->lk_rx_connected(lk_rx_connected);
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dut->lk_link_failure_csr(lk_link_failure_csr);
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dut->cd_initiate_nonretry_disconnect_lk(cd_initiate_nonretry_disconnect_lk);
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#ifndef INTERNAL_SHIFTER_ALIGNMENT
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dut->lk_deser_stall_phy(lk_deser_stall_phy);
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dut->lk_deser_stall_cycles_phy(lk_deser_stall_cycles_phy);
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#endif
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//Connect the testbench
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tb->clk(clk);
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tb->resetx(resetx);
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tb->pwrok(pwrok);
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tb->ldtstopx(ldtstopx);
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tb->phy_ctl_lk(phy_ctl_lk);
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for(int n = 0; n < CAD_IN_WIDTH; n++)
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tb->phy_cad_lk[n](phy_cad_lk[n]);
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tb->phy_available_lk(phy_available_lk);
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tb->lk_ctl_phy(lk_ctl_phy);
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for(int n = 0; n < CAD_OUT_WIDTH; n++)
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tb->lk_cad_phy[n](lk_cad_phy[n]);
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tb->phy_consume_lk(phy_consume_lk);
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tb->lk_disable_drivers_phy(lk_disable_drivers_phy);
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tb->lk_disable_receivers_phy(lk_disable_receivers_phy);
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tb->fc_dword_lk(fc_dword_lk);
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tb->fc_lctl_lk(fc_lctl_lk);
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tb->fc_hctl_lk(fc_hctl_lk);
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tb->lk_consume_fc(lk_consume_fc);
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tb->lk_dword_cd(lk_dword_cd);
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tb->lk_hctl_cd(lk_hctl_cd);
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tb->lk_lctl_cd(lk_lctl_cd);
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tb->lk_available_cd(lk_available_cd);
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tb->csr_rx_link_width_lk(csr_rx_link_width_lk);
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tb->csr_tx_link_width_lk(csr_tx_link_width_lk);
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tb->csr_sync(csr_sync);
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tb->csr_end_of_chain(csr_end_of_chain);
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tb->lk_update_link_width_csr(lk_update_link_width_csr);
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tb->lk_sampled_link_width_csr(lk_sampled_link_width_csr);
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tb->lk_protocol_error_csr(lk_protocol_error_csr);
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tb->csr_crc_force_error_lk(csr_crc_force_error_lk);
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tb->csr_transmitter_off_lk(csr_transmitter_off_lk);
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tb->csr_extented_ctl_lk(csr_extented_ctl_lk);
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tb->csr_extended_ctl_timeout_lk(csr_extended_ctl_timeout_lk);
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tb->csr_ldtstop_tristate_enable_lk(csr_ldtstop_tristate_enable_lk);
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tb->lk_crc_error_csr(lk_crc_error_csr);
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tb->lk_update_link_failure_property_csr(lk_update_link_failure_property_csr);
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#ifdef RETRY_MODE_ENABLED
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tb->lk_initiate_retry_disconnect(lk_initiate_retry_disconnect);
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tb->cd_initiate_retry_disconnect(cd_initiate_retry_disconnect);
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tb->fc_disconnect_lk(fc_disconnect_lk);
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tb->csr_retry(csr_retry);
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#endif
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tb->lk_rx_connected(lk_rx_connected);
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tb->lk_link_failure_csr(lk_link_failure_csr);
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tb->cd_initiate_nonretry_disconnect_lk(cd_initiate_nonretry_disconnect_lk);
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#ifndef INTERNAL_SHIFTER_ALIGNMENT
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tb->lk_deser_stall_phy(lk_deser_stall_phy);
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tb->lk_deser_stall_cycles_phy(lk_deser_stall_cycles_phy);
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#endif
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// tracing:
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// trace file creation
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sc_trace_file *tf = sc_create_vcd_trace_file("sim_link_l2");
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// External Signals
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sc_trace(tf, clk, "clk");
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sc_trace(tf,resetx,"resetx");
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sc_trace(tf,pwrok,"pwrok");
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sc_trace(tf,ldtstopx,"ldtstopx");
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sc_trace(tf,phy_ctl_lk,"phy_ctl_lk");
|
302 |
|
|
for(int n = 0 ; n < CAD_IN_WIDTH; n++){
|
303 |
|
|
std::ostringstream s;
|
304 |
|
|
s << "phy_cad_lk(" << n << ')';
|
305 |
|
|
sc_trace(tf, phy_cad_lk[n],s.str().c_str());
|
306 |
|
|
}
|
307 |
|
|
sc_trace(tf,phy_available_lk,"phy_available_lk");
|
308 |
|
|
sc_trace(tf,lk_ctl_phy,"lk_ctl_phy");
|
309 |
|
|
for(int n = 0 ; n < CAD_OUT_WIDTH; n++){
|
310 |
|
|
std::ostringstream s;
|
311 |
|
|
s << "lk_cad_phy(" << n << ')';
|
312 |
|
|
sc_trace(tf,lk_cad_phy[n],s.str().c_str());
|
313 |
|
|
}
|
314 |
|
|
sc_trace(tf,phy_consume_lk,"phy_consume_lk");
|
315 |
|
|
sc_trace(tf,lk_disable_drivers_phy,"lk_disable_drivers_phy");
|
316 |
|
|
sc_trace(tf,lk_disable_receivers_phy,"lk_disable_receivers_phy");
|
317 |
|
|
sc_trace(tf,fc_dword_lk,"fc_dword_lk");
|
318 |
|
|
sc_trace(tf,fc_lctl_lk,"fc_lctl_lk");
|
319 |
|
|
sc_trace(tf,fc_hctl_lk,"fc_hctl_lk");
|
320 |
|
|
sc_trace(tf,lk_consume_fc,"lk_consume_fc");
|
321 |
|
|
sc_trace(tf,lk_dword_cd,"lk_dword_cd");
|
322 |
|
|
sc_trace(tf,lk_hctl_cd,"lk_hctl_cd");
|
323 |
|
|
sc_trace(tf,lk_lctl_cd,"lk_lctl_cd");
|
324 |
|
|
sc_trace(tf,lk_available_cd,"lk_available_cd");
|
325 |
|
|
sc_trace(tf,csr_rx_link_width_lk,"csr_rx_link_width_lk");
|
326 |
|
|
sc_trace(tf,csr_tx_link_width_lk,"csr_tx_link_width_lk");
|
327 |
|
|
sc_trace(tf,csr_sync,"csr_sync");
|
328 |
|
|
sc_trace(tf,csr_end_of_chain,"csr_end_of_chain");
|
329 |
|
|
sc_trace(tf,lk_update_link_width_csr,"lk_update_link_width_csr");
|
330 |
|
|
sc_trace(tf,lk_sampled_link_width_csr,"lk_sampled_link_width_csr");
|
331 |
|
|
sc_trace(tf,lk_protocol_error_csr,"lk_protocol_error_csr");
|
332 |
|
|
sc_trace(tf,csr_crc_force_error_lk,"csr_crc_force_error_lk");
|
333 |
|
|
sc_trace(tf,csr_transmitter_off_lk,"csr_transmitter_off_lk");
|
334 |
|
|
sc_trace(tf,csr_extented_ctl_lk,"csr_extented_ctl_lk");
|
335 |
|
|
sc_trace(tf,csr_extended_ctl_timeout_lk,"csr_extended_ctl_timeout_lk");
|
336 |
|
|
sc_trace(tf,csr_ldtstop_tristate_enable_lk,"csr_ldtstop_tristate_enable_lk");
|
337 |
|
|
sc_trace(tf,lk_crc_error_csr,"lk_crc_error_csr");
|
338 |
|
|
sc_trace(tf,lk_update_link_failure_property_csr,"lk_update_link_failure_property_csr");
|
339 |
|
|
|
340 |
|
|
#ifdef RETRY_MODE_ENABLED
|
341 |
|
|
sc_trace(tf,lk_initiate_retry_disconnect,"lk_initiate_retry_disconnect");
|
342 |
|
|
sc_trace(tf,cd_initiate_retry_disconnect,"cd_initiate_retry_disconnect");
|
343 |
|
|
sc_trace(tf,fc_disconnect_lk,"fc_disconnect_lk");
|
344 |
|
|
sc_trace(tf,csr_retry,"csr_retry");
|
345 |
|
|
#endif
|
346 |
|
|
sc_trace(tf,lk_rx_connected,"lk_rx_connected");
|
347 |
|
|
sc_trace(tf,lk_link_failure_csr,"lk_link_failure_csr");
|
348 |
|
|
sc_trace(tf,cd_initiate_nonretry_disconnect_lk,"cd_initiate_nonretry_disconnect_lk");
|
349 |
|
|
|
350 |
|
|
|
351 |
|
|
|
352 |
|
|
//------------------------------------------
|
353 |
|
|
// Start simulation
|
354 |
|
|
//------------------------------------------
|
355 |
|
|
cout << "Debut de la simulation" << endl;
|
356 |
|
|
sc_start(4500);
|
357 |
|
|
|
358 |
|
|
|
359 |
|
|
sc_close_vcd_trace_file(tf);
|
360 |
|
|
cout << "fin de la simulation" << endl;
|
361 |
|
|
|
362 |
|
|
delete dut;
|
363 |
|
|
delete tb;
|
364 |
|
|
return 0;
|
365 |
|
|
}
|