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//main_synth.h for vc_ht_tunnel_l1 testbench in ModelSim
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/*==========================================================================
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HyperTransport Tunnel IP Core Source Code
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Copyright (C) 2005 by École Polytechnique de Montréal, All rights
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reserved.
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No part of this file may be duplicated, revised, translated, localized or
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modified in any manner or compiled, synthetized, linked or uploaded or
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downloaded to or from any computer system without the prior written
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consent of École Polytechnique de Montréal.
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==========================================================================*/
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#ifndef MTI2_SYSTEMC
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#error The file main_synth.h must not be included in a normal compilation
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#endif
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/**
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@file main_synth.h
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@author Ami Castonguay
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@description This file is to be used exclusively to do simulation with
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ModelSim. It should not be included in normal compilation.
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More specifically, main_synth.h is for post synthesis simulation
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*/
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#include "../../core_synth/synth_datatypes.h"
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#include <iostream>
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#include <string>
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#include <sstream>
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#include <iomanip>
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#include "vc_ht_tunnel_l1_synth.h"
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#include "vc_ht_tunnel_l1_tb.h"
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using namespace std;
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///Top simulation module for Tunnel simulation with ModelSim
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class top : public sc_module{
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public:
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sc_clock clk;
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//------------------------------------------
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// Instanciation de FLOW CONTROL
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//------------------------------------------
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vc_ht_tunnel_l1 the_ht_tunnel;
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vc_ht_tunnel_l1_tb tb;
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// ***************************************************
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// Signals
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// ***************************************************
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/// The Clock, LDTSTOP and reset signals
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sc_signal<bool> resetx;
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sc_signal<bool> pwrok;
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sc_signal<bool> ldtstopx;
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//Link0 signals
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//sc_signal<bool > receive_clk0;
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sc_signal<bool> phy0_available_lk0;
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sc_signal<sc_bv<CAD_IN_DEPTH> > phy0_ctl_lk0;
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sc_signal<sc_bv<CAD_IN_DEPTH> > phy0_cad_lk0__0;
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sc_signal<sc_bv<CAD_IN_DEPTH> > phy0_cad_lk0__1;
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sc_signal<sc_bv<CAD_IN_DEPTH> > phy0_cad_lk0__2;
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sc_signal<sc_bv<CAD_IN_DEPTH> > phy0_cad_lk0__3;
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sc_signal<sc_bv<CAD_IN_DEPTH> > phy0_cad_lk0__4;
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sc_signal<sc_bv<CAD_IN_DEPTH> > phy0_cad_lk0__5;
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sc_signal<sc_bv<CAD_IN_DEPTH> > phy0_cad_lk0__6;
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sc_signal<sc_bv<CAD_IN_DEPTH> > phy0_cad_lk0__7;
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//sc_signal< bool > transmit_clk0;
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sc_signal<sc_bv<CAD_OUT_DEPTH> > lk0_ctl_phy0;
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sc_signal<sc_bv<CAD_OUT_DEPTH> > lk0_cad_phy0__0;
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sc_signal<sc_bv<CAD_OUT_DEPTH> > lk0_cad_phy0__1;
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sc_signal<sc_bv<CAD_OUT_DEPTH> > lk0_cad_phy0__2;
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sc_signal<sc_bv<CAD_OUT_DEPTH> > lk0_cad_phy0__3;
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sc_signal<sc_bv<CAD_OUT_DEPTH> > lk0_cad_phy0__4;
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sc_signal<sc_bv<CAD_OUT_DEPTH> > lk0_cad_phy0__5;
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sc_signal<sc_bv<CAD_OUT_DEPTH> > lk0_cad_phy0__6;
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sc_signal<sc_bv<CAD_OUT_DEPTH> > lk0_cad_phy0__7;
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sc_signal<bool> phy0_consume_lk0;
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sc_signal<bool> lk0_disable_drivers_phy0;
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sc_signal<bool> lk0_disable_receivers_phy0;
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//Link1 signals
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//sc_signal<bool > receive_clk1;
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sc_signal<bool> phy1_available_lk1;
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sc_signal<sc_bv<CAD_IN_DEPTH> > phy1_ctl_lk1;
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sc_signal<sc_bv<CAD_IN_DEPTH> > phy1_cad_lk1__0;
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sc_signal<sc_bv<CAD_IN_DEPTH> > phy1_cad_lk1__1;
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sc_signal<sc_bv<CAD_IN_DEPTH> > phy1_cad_lk1__2;
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sc_signal<sc_bv<CAD_IN_DEPTH> > phy1_cad_lk1__3;
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sc_signal<sc_bv<CAD_IN_DEPTH> > phy1_cad_lk1__4;
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sc_signal<sc_bv<CAD_IN_DEPTH> > phy1_cad_lk1__5;
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sc_signal<sc_bv<CAD_IN_DEPTH> > phy1_cad_lk1__6;
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sc_signal<sc_bv<CAD_IN_DEPTH> > phy1_cad_lk1__7;
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//sc_signal< bool > transmit_clk0;
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sc_signal<sc_bv<CAD_OUT_DEPTH> > lk1_ctl_phy1;
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sc_signal<sc_bv<CAD_OUT_DEPTH> > lk1_cad_phy1__0;
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sc_signal<sc_bv<CAD_OUT_DEPTH> > lk1_cad_phy1__1;
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sc_signal<sc_bv<CAD_OUT_DEPTH> > lk1_cad_phy1__2;
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sc_signal<sc_bv<CAD_OUT_DEPTH> > lk1_cad_phy1__3;
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sc_signal<sc_bv<CAD_OUT_DEPTH> > lk1_cad_phy1__4;
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sc_signal<sc_bv<CAD_OUT_DEPTH> > lk1_cad_phy1__5;
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sc_signal<sc_bv<CAD_OUT_DEPTH> > lk1_cad_phy1__6;
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sc_signal<sc_bv<CAD_OUT_DEPTH> > lk1_cad_phy1__7;
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sc_signal<bool> phy1_consume_lk1;
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sc_signal<bool> lk1_disable_drivers_phy1;
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sc_signal<bool> lk1_disable_receivers_phy1;
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/////////////////////////////////////////////////////
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// Interface to UserInterface memory - synchronous
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/////////////////////////////////////////////////////
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sc_signal<bool> ui_memory_write0;
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sc_signal<bool> ui_memory_write1;//20
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sc_signal<sc_bv<USER_MEMORY_ADDRESS_WIDTH> > ui_memory_write_address;
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sc_signal<sc_bv<32> > ui_memory_write_data;
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sc_signal<sc_bv<USER_MEMORY_ADDRESS_WIDTH> > ui_memory_read_address0;
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sc_signal<sc_bv<USER_MEMORY_ADDRESS_WIDTH> > ui_memory_read_address1;
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sc_signal<sc_bv<32> > ui_memory_read_data0;
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sc_signal<sc_bv<32> > ui_memory_read_data1;
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#ifdef RETRY_MODE_ENABLED
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//////////////////////////////////////////
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// Memory interface flowcontrol0- synchronous
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/////////////////////////////////////////
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sc_signal<bool> history_memory_write0;
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sc_signal<sc_uint<LOG2_HISTORY_MEMORY_SIZE> > history_memory_write_address0;
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sc_signal<sc_bv<32> > history_memory_write_data0;
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sc_signal<sc_uint<LOG2_HISTORY_MEMORY_SIZE> > history_memory_read_address0;//30
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sc_signal<sc_bv<32> > history_memory_output0;
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//////////////////////////////////////////
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// Memory interface flowcontrol1- synchronous
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/////////////////////////////////////////
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sc_signal<bool> history_memory_write1;
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sc_signal<sc_uint<LOG2_HISTORY_MEMORY_SIZE> > history_memory_write_address1;
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sc_signal<sc_bv<32> > history_memory_write_data1;
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sc_signal<sc_uint<LOG2_HISTORY_MEMORY_SIZE> > history_memory_read_address1;
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sc_signal<sc_bv<32> > history_memory_output1;
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#endif
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////////////////////////////////////
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// Memory interface databuffer0 - synchronous
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////////////////////////////////////
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sc_signal<bool> memory_write0;
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sc_signal<sc_uint<2> > memory_write_address_vc0;
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sc_signal<sc_uint<BUFFERS_ADDRESS_WIDTH> > memory_write_address_buffer0;
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sc_signal<sc_uint<DATABUFFER_LOG2_MAX_DATA_PER_BUFFER> > memory_write_address_pos0;//40
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sc_signal<sc_bv<32> > memory_write_data0;
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sc_signal<sc_uint<2> > memory_read_address_vc0__0;
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sc_signal<sc_uint<2> > memory_read_address_vc0__1;
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sc_signal<sc_uint<BUFFERS_ADDRESS_WIDTH> >memory_read_address_buffer0__0;
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sc_signal<sc_uint<BUFFERS_ADDRESS_WIDTH> >memory_read_address_buffer0__1;
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sc_signal<sc_uint<DATABUFFER_LOG2_MAX_DATA_PER_BUFFER> > memory_read_address_pos0__0;//50
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sc_signal<sc_uint<DATABUFFER_LOG2_MAX_DATA_PER_BUFFER> > memory_read_address_pos0__1;//50
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sc_signal<sc_bv<32> > memory_output0__0;
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sc_signal<sc_bv<32> > memory_output0__1;
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//////////////////////////////////////
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// Memory interface databuffer1 - synchronous
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////////////////////////////////////
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sc_signal<bool> memory_write1;
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sc_signal<sc_uint<2> > memory_write_address_vc1;
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sc_signal<sc_uint<BUFFERS_ADDRESS_WIDTH> > memory_write_address_buffer1;
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sc_signal<sc_uint<DATABUFFER_LOG2_MAX_DATA_PER_BUFFER> > memory_write_address_pos1;
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sc_signal<sc_bv<32> > memory_write_data1;
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sc_signal<sc_uint<2> > memory_read_address_vc1__0;
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sc_signal<sc_uint<2> > memory_read_address_vc1__1;
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sc_signal<sc_uint<BUFFERS_ADDRESS_WIDTH> >memory_read_address_buffer1__0;
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sc_signal<sc_uint<BUFFERS_ADDRESS_WIDTH> >memory_read_address_buffer1__1;
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sc_signal<sc_uint<DATABUFFER_LOG2_MAX_DATA_PER_BUFFER> > memory_read_address_pos1__0;
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sc_signal<sc_uint<DATABUFFER_LOG2_MAX_DATA_PER_BUFFER> > memory_read_address_pos1__1;
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sc_signal<sc_bv<32> > memory_output1__0;
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sc_signal<sc_bv<32> > memory_output1__1;
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//************************************
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// Reset generated by link
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//************************************
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//sc_signal<bool> warmrstx;
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//sc_signal<bool> coldrstx;
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//sc_signal<bool> dummy_warmrstx;
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//sc_signal<bool> dummy_coldrstx;
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//******************************************
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// Signals to User
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//******************************************
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//------------------------------------------
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// Signals to send received packets to User
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//------------------------------------------
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/**The actual control/data packet to the user*/
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sc_signal<sc_bv<64> > ui_packet_usr;
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/**The virtual channel of the ctl/data packet*/
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sc_signal<VirtualChannel> ui_vc_usr;
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/**The side from which came the packet*/
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sc_signal< bool > ui_side_usr;
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/**If the packet is a direct_route packet - only valid for
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requests (posted and non-posted) */
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sc_signal<bool> ui_directroute_usr;
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/**If this is the last part of the packet*/
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sc_signal< bool > ui_eop_usr;
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/**If there is another packet available*/
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sc_signal< bool > ui_available_usr;
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/**If what is read is 64 bits or 32 bits*/
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sc_signal< bool > ui_output_64bits_usr;
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/**To allow the user to consume the packets*/
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sc_signal< bool > usr_consume_ui;
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//------------------------------------------
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// Signals to allow the User to send packets
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//------------------------------------------
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/**The actual control/data packet from the user*/
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sc_signal<sc_bv<64> > usr_packet_ui;
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/**If there is another packet available*/
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sc_signal< bool > usr_available_ui;
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/**
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The side to send the packet if it is a response
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This bit is ignored if the packet is not a response
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since the side to send a request is determined automatically
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taking in acount DirectRoute functionnality.
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*/
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sc_signal< bool > usr_side_ui;
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/**If the packet is trying to be sent to a VC that is full,
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We let the user know that he is doing something illegal
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Packet is not consumed if this is 1
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*/
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//sc_signal < bool > ui_invalid_usr;
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/**Which what type of ctl packets can be sent to side0*/
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sc_signal<sc_bv<6> > ui_freevc0_usr;
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/**Which what type of ctl packets can be sent to side0*/
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sc_signal<sc_bv<6> > ui_freevc1_usr;
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//-----------------------------------------------
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// Content of CSR that might be useful to user
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//-----------------------------------------------
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/** Signals table containing all 40 bits Base Addresses from BARs implemented */
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sc_signal<sc_bv<40> > csr_bar__0;
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sc_signal<sc_bv<40> > csr_bar__1;
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sc_signal<sc_bv<40> > csr_bar__2;
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sc_signal<sc_bv<40> > csr_bar__3;
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sc_signal<sc_bv<40> > csr_bar__4;
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sc_signal<sc_bv<40> > csr_bar__5;
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/** Signal from register Interface->Command->csr_unit_id */
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sc_signal<sc_bv<5> > csr_unit_id;
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//------------------------------------------
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// Signals to affect CSR
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//------------------------------------------
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sc_signal<bool> usr_receivedResponseError_csr;
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//--------------------------------------------------------
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// Interface for having registers outside CSR if necessary
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//--------------------------------------------------------
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///Signals to allow external registers with minimal logic
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/**
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Connect usr_read_data_csr to zeroes if not used!
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*/
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//@{
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sc_signal<sc_uint<6> > csr_read_addr_usr;
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sc_signal<sc_bv<32> > usr_read_data_csr;
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sc_signal<bool > csr_write_usr;
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sc_signal<sc_uint<6> > csr_write_addr_usr;
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sc_signal<sc_bv<32> > csr_write_data_usr;
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/**Every bit is a byte mask for the dword to write*/
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sc_signal<sc_bv<4> > csr_write_mask_usr;
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//@}
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top(sc_module_name name) : sc_module(name),
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clk("clk",100,SC_NS,0.5),the_ht_tunnel("dut","vc_ht_tunnel_l1"),
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tb("tb"),
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resetx("resetx"),
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pwrok("pwrok"),
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ldtstopx("ldtstopx"),
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|
|
phy0_available_lk0("phy0_available_lk0"),
|
313 |
|
|
phy0_ctl_lk0("phy0_ctl_lk0"),
|
314 |
|
|
phy0_cad_lk0__0("phy0_cad_lk0__0"),
|
315 |
|
|
phy0_cad_lk0__1("phy0_cad_lk0__1"),
|
316 |
|
|
phy0_cad_lk0__2("phy0_cad_lk0__2"),
|
317 |
|
|
phy0_cad_lk0__3("phy0_cad_lk0__3"),
|
318 |
|
|
phy0_cad_lk0__4("phy0_cad_lk0__4"),
|
319 |
|
|
phy0_cad_lk0__5("phy0_cad_lk0__5"),
|
320 |
|
|
phy0_cad_lk0__6("phy0_cad_lk0__6"),
|
321 |
|
|
phy0_cad_lk0__7("phy0_cad_lk0__7"),
|
322 |
|
|
lk0_ctl_phy0("lk0_ctl_phy0"),
|
323 |
|
|
lk0_cad_phy0__0("lk0_cad_phy0__0"),
|
324 |
|
|
lk0_cad_phy0__1("lk0_cad_phy0__1"),
|
325 |
|
|
lk0_cad_phy0__2("lk0_cad_phy0__2"),
|
326 |
|
|
lk0_cad_phy0__3("lk0_cad_phy0__3"),
|
327 |
|
|
lk0_cad_phy0__4("lk0_cad_phy0__4"),
|
328 |
|
|
lk0_cad_phy0__5("lk0_cad_phy0__5"),
|
329 |
|
|
lk0_cad_phy0__6("lk0_cad_phy0__6"),
|
330 |
|
|
lk0_cad_phy0__7("lk0_cad_phy0__7"),
|
331 |
|
|
phy0_consume_lk0("phy0_consume_lk0"),
|
332 |
|
|
lk0_disable_drivers_phy0("lk0_disable_drivers_phy0"),
|
333 |
|
|
lk0_disable_receivers_phy0("lk0_disable_receivers_phy0"),
|
334 |
|
|
phy1_available_lk1("phy1_available_lk1"),
|
335 |
|
|
phy1_ctl_lk1("phy1_ctl_lk1"),
|
336 |
|
|
phy1_cad_lk1__0("phy1_cad_lk1__0"),
|
337 |
|
|
phy1_cad_lk1__1("phy1_cad_lk1__1"),
|
338 |
|
|
phy1_cad_lk1__2("phy1_cad_lk1__2"),
|
339 |
|
|
phy1_cad_lk1__3("phy1_cad_lk1__3"),
|
340 |
|
|
phy1_cad_lk1__4("phy1_cad_lk1__4"),
|
341 |
|
|
phy1_cad_lk1__5("phy1_cad_lk1__5"),
|
342 |
|
|
phy1_cad_lk1__6("phy1_cad_lk1__6"),
|
343 |
|
|
phy1_cad_lk1__7("phy1_cad_lk1__7"),
|
344 |
|
|
lk1_ctl_phy1("lk1_ctl_phy1"),
|
345 |
|
|
lk1_cad_phy1__0("lk1_cad_phy1__0"),
|
346 |
|
|
lk1_cad_phy1__1("lk1_cad_phy1__1"),
|
347 |
|
|
lk1_cad_phy1__2("lk1_cad_phy1__2"),
|
348 |
|
|
lk1_cad_phy1__3("lk1_cad_phy1__3"),
|
349 |
|
|
lk1_cad_phy1__4("lk1_cad_phy1__4"),
|
350 |
|
|
lk1_cad_phy1__5("lk1_cad_phy1__5"),
|
351 |
|
|
lk1_cad_phy1__6("lk1_cad_phy1__6"),
|
352 |
|
|
lk1_cad_phy1__7("lk1_cad_phy1__7"),
|
353 |
|
|
phy1_consume_lk1("phy1_consume_lk1"),
|
354 |
|
|
lk1_disable_drivers_phy1("lk1_disable_drivers_phy1"),
|
355 |
|
|
lk1_disable_receivers_phy1("lk1_disable_receivers_phy1"),
|
356 |
|
|
ui_memory_write0("ui_memory_write0"),
|
357 |
|
|
ui_memory_write1("ui_memory_write1"),
|
358 |
|
|
ui_memory_write_address("ui_memory_write_address"),
|
359 |
|
|
ui_memory_write_data("ui_memory_write_data"),
|
360 |
|
|
ui_memory_read_address0("ui_memory_read_address0"),
|
361 |
|
|
ui_memory_read_address1("ui_memory_read_address1"),
|
362 |
|
|
ui_memory_read_data0("ui_memory_read_data0"),
|
363 |
|
|
ui_memory_read_data1("ui_memory_read_data1"),
|
364 |
|
|
history_memory_write0("history_memory_write0"),
|
365 |
|
|
history_memory_write_address0("history_memory_write_address0"),
|
366 |
|
|
history_memory_write_data0("history_memory_write_data0"),
|
367 |
|
|
history_memory_read_address0("history_memory_read_address0"),
|
368 |
|
|
history_memory_output0("history_memory_output0"),
|
369 |
|
|
history_memory_write1("history_memory_write1"),
|
370 |
|
|
history_memory_write_address1("history_memory_write_address1"),
|
371 |
|
|
history_memory_write_data1("history_memory_write_data1"),
|
372 |
|
|
history_memory_read_address1("history_memory_read_address1"),
|
373 |
|
|
history_memory_output1("history_memory_output1"),
|
374 |
|
|
memory_write0("memory_write0"),
|
375 |
|
|
memory_write_address_vc0("memory_write_address_vc0"),
|
376 |
|
|
memory_write_address_buffer0("memory_write_address_buffer0"),
|
377 |
|
|
memory_write_address_pos0("memory_write_address_pos0"),
|
378 |
|
|
memory_write_data0("memory_write_data0"),
|
379 |
|
|
memory_read_address_vc0__0("memory_read_address_vc0__0"),
|
380 |
|
|
memory_read_address_vc0__1("memory_read_address_vc0__1"),
|
381 |
|
|
memory_read_address_buffer0__0("memory_read_address_buffer0__0"),
|
382 |
|
|
memory_read_address_buffer0__1("memory_read_address_buffer0__1"),
|
383 |
|
|
memory_read_address_pos0__0("memory_read_address_pos0__0"),
|
384 |
|
|
memory_read_address_pos0__1("memory_read_address_pos0__1"),
|
385 |
|
|
memory_output0__0("memory_output0__0"),
|
386 |
|
|
memory_output0__1("memory_output0__1"),
|
387 |
|
|
memory_write1("memory_write1"),
|
388 |
|
|
memory_write_address_vc1("memory_write_address_vc1"),
|
389 |
|
|
memory_write_address_buffer1("memory_write_address_buffer1"),
|
390 |
|
|
memory_write_address_pos1("memory_write_address_pos1"),
|
391 |
|
|
memory_write_data1("memory_write_data1"),
|
392 |
|
|
memory_read_address_vc1__0("memory_read_address_vc1__0"),
|
393 |
|
|
memory_read_address_vc1__1("memory_read_address_vc1__1"),
|
394 |
|
|
memory_read_address_buffer1__0("memory_read_address_buffer1__0"),
|
395 |
|
|
memory_read_address_buffer1__1("memory_read_address_buffer1__1"),
|
396 |
|
|
memory_read_address_pos1__0("memory_read_address_pos1__0"),
|
397 |
|
|
memory_read_address_pos1__1("memory_read_address_pos1__1"),
|
398 |
|
|
memory_output1__0("memory_output1__0"),
|
399 |
|
|
memory_output1__1("memory_output1__1"),
|
400 |
|
|
ui_packet_usr("ui_packet_usr"),
|
401 |
|
|
ui_vc_usr("ui_vc_usr"),
|
402 |
|
|
ui_side_usr("ui_side_usr"),
|
403 |
|
|
ui_directroute_usr("ui_directroute_usr"),
|
404 |
|
|
ui_eop_usr("ui_eop_usr"),
|
405 |
|
|
ui_available_usr("ui_available_usr"),
|
406 |
|
|
ui_output_64bits_usr("ui_output_64bits_usr"),
|
407 |
|
|
usr_consume_ui("usr_consume_ui"),
|
408 |
|
|
usr_packet_ui("usr_packet_ui"),
|
409 |
|
|
usr_available_ui("usr_available_ui"),
|
410 |
|
|
usr_side_ui("usr_side_ui"),
|
411 |
|
|
ui_freevc0_usr("ui_freevc0_usr"),
|
412 |
|
|
ui_freevc1_usr("ui_freevc1_usr"),
|
413 |
|
|
csr_bar__0("csr_bar__0"),
|
414 |
|
|
csr_bar__1("csr_bar__1"),
|
415 |
|
|
csr_bar__2("csr_bar__2"),
|
416 |
|
|
csr_bar__3("csr_bar__3"),
|
417 |
|
|
csr_bar__4("csr_bar__4"),
|
418 |
|
|
csr_bar__5("csr_bar__5"),
|
419 |
|
|
csr_unit_id("csr_unit_id"),
|
420 |
|
|
usr_receivedResponseError_csr("usr_receivedResponseError_csr"),
|
421 |
|
|
csr_read_addr_usr("csr_read_addr_usr"),
|
422 |
|
|
usr_read_data_csr("usr_read_data_csr"),
|
423 |
|
|
csr_write_usr("csr_write_usr"),
|
424 |
|
|
csr_write_addr_usr("csr_write_addr_usr"),
|
425 |
|
|
csr_write_data_usr("csr_write_data_usr"),
|
426 |
|
|
csr_write_mask_usr("csr_write_mask_usr")
|
427 |
|
|
{
|
428 |
|
|
|
429 |
|
|
// ***************************************************
|
430 |
|
|
// LINKING DUT
|
431 |
|
|
// ***************************************************
|
432 |
|
|
the_ht_tunnel.clk(clk);
|
433 |
|
|
the_ht_tunnel.resetx(resetx);
|
434 |
|
|
the_ht_tunnel.pwrok(pwrok);
|
435 |
|
|
the_ht_tunnel.ldtstopx(ldtstopx);
|
436 |
|
|
|
437 |
|
|
the_ht_tunnel.phy0_available_lk0(phy0_available_lk0);
|
438 |
|
|
the_ht_tunnel.phy0_ctl_lk0(phy0_ctl_lk0);
|
439 |
|
|
|
440 |
|
|
#if CAD_IN_WIDTH != 8
|
441 |
|
|
#error Not right input width
|
442 |
|
|
#endif
|
443 |
|
|
#if CAD_OUT_WIDTH != 8
|
444 |
|
|
#error Not right output width
|
445 |
|
|
#endif
|
446 |
|
|
|
447 |
|
|
the_ht_tunnel.phy0_cad_lk0__0(phy0_cad_lk0__0);
|
448 |
|
|
the_ht_tunnel.lk0_cad_phy0__0(lk0_cad_phy0__0);
|
449 |
|
|
the_ht_tunnel.phy1_cad_lk1__0(phy1_cad_lk1__0);
|
450 |
|
|
the_ht_tunnel.lk1_cad_phy1__0(lk1_cad_phy1__0);
|
451 |
|
|
|
452 |
|
|
the_ht_tunnel.phy0_cad_lk0__1(phy0_cad_lk0__1);
|
453 |
|
|
the_ht_tunnel.lk0_cad_phy0__1(lk0_cad_phy0__1);
|
454 |
|
|
the_ht_tunnel.phy1_cad_lk1__1(phy1_cad_lk1__1);
|
455 |
|
|
the_ht_tunnel.lk1_cad_phy1__1(lk1_cad_phy1__1);
|
456 |
|
|
|
457 |
|
|
the_ht_tunnel.phy0_cad_lk0__2(phy0_cad_lk0__2);
|
458 |
|
|
the_ht_tunnel.lk0_cad_phy0__2(lk0_cad_phy0__2);
|
459 |
|
|
the_ht_tunnel.phy1_cad_lk1__2(phy1_cad_lk1__2);
|
460 |
|
|
the_ht_tunnel.lk1_cad_phy1__2(lk1_cad_phy1__2);
|
461 |
|
|
|
462 |
|
|
the_ht_tunnel.phy0_cad_lk0__3(phy0_cad_lk0__3);
|
463 |
|
|
the_ht_tunnel.lk0_cad_phy0__3(lk0_cad_phy0__3);
|
464 |
|
|
the_ht_tunnel.phy1_cad_lk1__3(phy1_cad_lk1__3);
|
465 |
|
|
the_ht_tunnel.lk1_cad_phy1__3(lk1_cad_phy1__3);
|
466 |
|
|
|
467 |
|
|
the_ht_tunnel.phy0_cad_lk0__4(phy0_cad_lk0__4);
|
468 |
|
|
the_ht_tunnel.lk0_cad_phy0__4(lk0_cad_phy0__4);
|
469 |
|
|
the_ht_tunnel.phy1_cad_lk1__4(phy1_cad_lk1__4);
|
470 |
|
|
the_ht_tunnel.lk1_cad_phy1__4(lk1_cad_phy1__4);
|
471 |
|
|
|
472 |
|
|
the_ht_tunnel.phy0_cad_lk0__5(phy0_cad_lk0__5);
|
473 |
|
|
the_ht_tunnel.lk0_cad_phy0__5(lk0_cad_phy0__5);
|
474 |
|
|
the_ht_tunnel.phy1_cad_lk1__5(phy1_cad_lk1__5);
|
475 |
|
|
the_ht_tunnel.lk1_cad_phy1__5(lk1_cad_phy1__5);
|
476 |
|
|
|
477 |
|
|
the_ht_tunnel.phy0_cad_lk0__6(phy0_cad_lk0__6);
|
478 |
|
|
the_ht_tunnel.lk0_cad_phy0__6(lk0_cad_phy0__6);
|
479 |
|
|
the_ht_tunnel.phy1_cad_lk1__6(phy1_cad_lk1__6);
|
480 |
|
|
the_ht_tunnel.lk1_cad_phy1__6(lk1_cad_phy1__6);
|
481 |
|
|
|
482 |
|
|
the_ht_tunnel.phy0_cad_lk0__7(phy0_cad_lk0__7);
|
483 |
|
|
the_ht_tunnel.lk0_cad_phy0__7(lk0_cad_phy0__7);
|
484 |
|
|
the_ht_tunnel.phy1_cad_lk1__7(phy1_cad_lk1__7);
|
485 |
|
|
the_ht_tunnel.lk1_cad_phy1__7(lk1_cad_phy1__7);
|
486 |
|
|
|
487 |
|
|
the_ht_tunnel.lk0_ctl_phy0(lk0_ctl_phy0);
|
488 |
|
|
the_ht_tunnel.phy0_consume_lk0(phy0_consume_lk0);
|
489 |
|
|
|
490 |
|
|
the_ht_tunnel.lk0_disable_drivers_phy0(lk0_disable_drivers_phy0);
|
491 |
|
|
the_ht_tunnel.lk0_disable_receivers_phy0(lk0_disable_receivers_phy0);
|
492 |
|
|
|
493 |
|
|
the_ht_tunnel.phy1_available_lk1(phy1_available_lk1);
|
494 |
|
|
the_ht_tunnel.phy1_ctl_lk1(phy1_ctl_lk1);
|
495 |
|
|
|
496 |
|
|
the_ht_tunnel.lk1_ctl_phy1(lk1_ctl_phy1);
|
497 |
|
|
the_ht_tunnel.phy1_consume_lk1(phy1_consume_lk1);
|
498 |
|
|
|
499 |
|
|
the_ht_tunnel.lk1_disable_drivers_phy1(lk1_disable_drivers_phy1);
|
500 |
|
|
the_ht_tunnel.lk1_disable_receivers_phy1(lk1_disable_receivers_phy1);
|
501 |
|
|
|
502 |
|
|
the_ht_tunnel.ui_memory_write0(ui_memory_write0);
|
503 |
|
|
the_ht_tunnel.ui_memory_write1(ui_memory_write1);//20
|
504 |
|
|
the_ht_tunnel.ui_memory_write_address(ui_memory_write_address);
|
505 |
|
|
the_ht_tunnel.ui_memory_write_data(ui_memory_write_data);
|
506 |
|
|
|
507 |
|
|
the_ht_tunnel.ui_memory_read_address0(ui_memory_read_address0);
|
508 |
|
|
the_ht_tunnel.ui_memory_read_address1(ui_memory_read_address1);
|
509 |
|
|
the_ht_tunnel.ui_memory_read_data0(ui_memory_read_data0);
|
510 |
|
|
the_ht_tunnel.ui_memory_read_data1(ui_memory_read_data1);
|
511 |
|
|
|
512 |
|
|
#ifdef RETRY_MODE_ENABLED
|
513 |
|
|
the_ht_tunnel.history_memory_write0(history_memory_write0);
|
514 |
|
|
the_ht_tunnel.history_memory_write_address0(history_memory_write_address0);
|
515 |
|
|
the_ht_tunnel.history_memory_write_data0(history_memory_write_data0);
|
516 |
|
|
the_ht_tunnel.history_memory_read_address0(history_memory_read_address0);//30
|
517 |
|
|
the_ht_tunnel.history_memory_output0(history_memory_output0);
|
518 |
|
|
|
519 |
|
|
the_ht_tunnel.history_memory_write1(history_memory_write1);
|
520 |
|
|
the_ht_tunnel.history_memory_write_address1(history_memory_write_address1);
|
521 |
|
|
the_ht_tunnel.history_memory_write_data1(history_memory_write_data1);
|
522 |
|
|
the_ht_tunnel.history_memory_read_address1(history_memory_read_address1);
|
523 |
|
|
the_ht_tunnel.history_memory_output1(history_memory_output1);
|
524 |
|
|
|
525 |
|
|
#endif
|
526 |
|
|
|
527 |
|
|
|
528 |
|
|
the_ht_tunnel.memory_write0(memory_write0);
|
529 |
|
|
the_ht_tunnel.memory_write_address_vc0(memory_write_address_vc0);
|
530 |
|
|
the_ht_tunnel.memory_write_address_buffer0(memory_write_address_buffer0);
|
531 |
|
|
the_ht_tunnel.memory_write_address_pos0(memory_write_address_pos0);//40
|
532 |
|
|
the_ht_tunnel.memory_write_data0(memory_write_data0);
|
533 |
|
|
|
534 |
|
|
the_ht_tunnel.memory_read_address_vc0__0(memory_read_address_vc0__0);
|
535 |
|
|
the_ht_tunnel.memory_read_address_buffer0__0(memory_read_address_buffer0__0);
|
536 |
|
|
the_ht_tunnel.memory_read_address_pos0__0(memory_read_address_pos0__0);//50
|
537 |
|
|
the_ht_tunnel.memory_output0__0(memory_output0__0);
|
538 |
|
|
|
539 |
|
|
the_ht_tunnel.memory_read_address_vc0__1(memory_read_address_vc0__1);
|
540 |
|
|
the_ht_tunnel.memory_read_address_buffer0__1(memory_read_address_buffer0__1);
|
541 |
|
|
the_ht_tunnel.memory_read_address_pos0__1(memory_read_address_pos0__1);//50
|
542 |
|
|
the_ht_tunnel.memory_output0__1(memory_output0__1);
|
543 |
|
|
|
544 |
|
|
|
545 |
|
|
the_ht_tunnel.memory_write1(memory_write1);
|
546 |
|
|
the_ht_tunnel.memory_write_address_vc1(memory_write_address_vc1);
|
547 |
|
|
the_ht_tunnel.memory_write_address_buffer1(memory_write_address_buffer1);
|
548 |
|
|
the_ht_tunnel.memory_write_address_pos1(memory_write_address_pos1);
|
549 |
|
|
the_ht_tunnel.memory_write_data1(memory_write_data1);
|
550 |
|
|
|
551 |
|
|
the_ht_tunnel.memory_read_address_vc1__0(memory_read_address_vc1__0);
|
552 |
|
|
the_ht_tunnel.memory_read_address_buffer1__0(memory_read_address_buffer1__0);
|
553 |
|
|
the_ht_tunnel.memory_read_address_pos1__0(memory_read_address_pos1__0);
|
554 |
|
|
the_ht_tunnel.memory_output1__0(memory_output1__0);
|
555 |
|
|
|
556 |
|
|
the_ht_tunnel.memory_read_address_vc1__1(memory_read_address_vc1__1);
|
557 |
|
|
the_ht_tunnel.memory_read_address_buffer1__1(memory_read_address_buffer1__1);
|
558 |
|
|
the_ht_tunnel.memory_read_address_pos1__1(memory_read_address_pos1__1);
|
559 |
|
|
the_ht_tunnel.memory_output1__1(memory_output1__1);
|
560 |
|
|
|
561 |
|
|
|
562 |
|
|
the_ht_tunnel.ui_packet_usr(ui_packet_usr);
|
563 |
|
|
the_ht_tunnel.ui_vc_usr(ui_vc_usr);
|
564 |
|
|
the_ht_tunnel.ui_side_usr(ui_side_usr);
|
565 |
|
|
the_ht_tunnel.ui_directroute_usr(ui_directroute_usr);
|
566 |
|
|
the_ht_tunnel.ui_eop_usr(ui_eop_usr);
|
567 |
|
|
the_ht_tunnel.ui_available_usr(ui_available_usr);
|
568 |
|
|
the_ht_tunnel.ui_output_64bits_usr(ui_output_64bits_usr);
|
569 |
|
|
the_ht_tunnel.usr_consume_ui(usr_consume_ui);
|
570 |
|
|
the_ht_tunnel.usr_packet_ui(usr_packet_ui);
|
571 |
|
|
the_ht_tunnel.usr_available_ui(usr_available_ui);
|
572 |
|
|
the_ht_tunnel.usr_side_ui(usr_side_ui);
|
573 |
|
|
the_ht_tunnel.ui_freevc0_usr(ui_freevc0_usr);
|
574 |
|
|
the_ht_tunnel.ui_freevc1_usr(ui_freevc1_usr);
|
575 |
|
|
#if NbRegsBars != 6
|
576 |
|
|
#error Not correct number of BARs
|
577 |
|
|
#endif
|
578 |
|
|
the_ht_tunnel.csr_bar__0(csr_bar__0);
|
579 |
|
|
the_ht_tunnel.csr_bar__1(csr_bar__1);
|
580 |
|
|
the_ht_tunnel.csr_bar__2(csr_bar__2);
|
581 |
|
|
the_ht_tunnel.csr_bar__3(csr_bar__3);
|
582 |
|
|
the_ht_tunnel.csr_bar__4(csr_bar__4);
|
583 |
|
|
the_ht_tunnel.csr_bar__5(csr_bar__5);
|
584 |
|
|
|
585 |
|
|
the_ht_tunnel.csr_unit_id(csr_unit_id);
|
586 |
|
|
the_ht_tunnel.usr_receivedResponseError_csr(usr_receivedResponseError_csr);
|
587 |
|
|
|
588 |
|
|
the_ht_tunnel.csr_read_addr_usr(csr_read_addr_usr);
|
589 |
|
|
the_ht_tunnel.usr_read_data_csr(usr_read_data_csr);
|
590 |
|
|
the_ht_tunnel.csr_write_usr(csr_write_usr);
|
591 |
|
|
the_ht_tunnel.csr_write_addr_usr(csr_write_addr_usr);
|
592 |
|
|
the_ht_tunnel.csr_write_data_usr(csr_write_data_usr);
|
593 |
|
|
the_ht_tunnel.csr_write_mask_usr(csr_write_mask_usr);
|
594 |
|
|
|
595 |
|
|
// ***************************************************
|
596 |
|
|
// LINKING TB
|
597 |
|
|
// ***************************************************
|
598 |
|
|
|
599 |
|
|
tb.clk(clk);
|
600 |
|
|
tb.resetx(resetx);
|
601 |
|
|
tb.pwrok(pwrok);
|
602 |
|
|
tb.ldtstopx(ldtstopx);
|
603 |
|
|
|
604 |
|
|
tb.phy0_available_lk0(phy0_available_lk0);
|
605 |
|
|
tb.phy0_ctl_lk0(phy0_ctl_lk0);
|
606 |
|
|
|
607 |
|
|
tb.phy0_cad_lk0[0](phy0_cad_lk0__0);
|
608 |
|
|
tb.lk0_cad_phy0[0](lk0_cad_phy0__0);
|
609 |
|
|
tb.phy1_cad_lk1[0](phy1_cad_lk1__0);
|
610 |
|
|
tb.lk1_cad_phy1[0](lk1_cad_phy1__0);
|
611 |
|
|
|
612 |
|
|
tb.phy0_cad_lk0[1](phy0_cad_lk0__1);
|
613 |
|
|
tb.lk0_cad_phy0[1](lk0_cad_phy0__1);
|
614 |
|
|
tb.phy1_cad_lk1[1](phy1_cad_lk1__1);
|
615 |
|
|
tb.lk1_cad_phy1[1](lk1_cad_phy1__1);
|
616 |
|
|
|
617 |
|
|
tb.phy0_cad_lk0[2](phy0_cad_lk0__2);
|
618 |
|
|
tb.lk0_cad_phy0[2](lk0_cad_phy0__2);
|
619 |
|
|
tb.phy1_cad_lk1[2](phy1_cad_lk1__2);
|
620 |
|
|
tb.lk1_cad_phy1[2](lk1_cad_phy1__2);
|
621 |
|
|
|
622 |
|
|
tb.phy0_cad_lk0[3](phy0_cad_lk0__3);
|
623 |
|
|
tb.lk0_cad_phy0[3](lk0_cad_phy0__3);
|
624 |
|
|
tb.phy1_cad_lk1[3](phy1_cad_lk1__3);
|
625 |
|
|
tb.lk1_cad_phy1[3](lk1_cad_phy1__3);
|
626 |
|
|
|
627 |
|
|
tb.phy0_cad_lk0[4](phy0_cad_lk0__4);
|
628 |
|
|
tb.lk0_cad_phy0[4](lk0_cad_phy0__4);
|
629 |
|
|
tb.phy1_cad_lk1[4](phy1_cad_lk1__4);
|
630 |
|
|
tb.lk1_cad_phy1[4](lk1_cad_phy1__4);
|
631 |
|
|
|
632 |
|
|
tb.phy0_cad_lk0[5](phy0_cad_lk0__5);
|
633 |
|
|
tb.lk0_cad_phy0[5](lk0_cad_phy0__5);
|
634 |
|
|
tb.phy1_cad_lk1[5](phy1_cad_lk1__5);
|
635 |
|
|
tb.lk1_cad_phy1[5](lk1_cad_phy1__5);
|
636 |
|
|
|
637 |
|
|
tb.phy0_cad_lk0[6](phy0_cad_lk0__6);
|
638 |
|
|
tb.lk0_cad_phy0[6](lk0_cad_phy0__6);
|
639 |
|
|
tb.phy1_cad_lk1[6](phy1_cad_lk1__6);
|
640 |
|
|
tb.lk1_cad_phy1[6](lk1_cad_phy1__6);
|
641 |
|
|
|
642 |
|
|
tb.phy0_cad_lk0[7](phy0_cad_lk0__7);
|
643 |
|
|
tb.lk0_cad_phy0[7](lk0_cad_phy0__7);
|
644 |
|
|
tb.phy1_cad_lk1[7](phy1_cad_lk1__7);
|
645 |
|
|
tb.lk1_cad_phy1[7](lk1_cad_phy1__7);
|
646 |
|
|
|
647 |
|
|
tb.lk0_ctl_phy0(lk0_ctl_phy0);
|
648 |
|
|
tb.phy0_consume_lk0(phy0_consume_lk0);
|
649 |
|
|
|
650 |
|
|
tb.lk0_disable_drivers_phy0(lk0_disable_drivers_phy0);
|
651 |
|
|
tb.lk0_disable_receivers_phy0(lk0_disable_receivers_phy0);
|
652 |
|
|
|
653 |
|
|
tb.phy1_available_lk1(phy1_available_lk1);
|
654 |
|
|
tb.phy1_ctl_lk1(phy1_ctl_lk1);
|
655 |
|
|
|
656 |
|
|
tb.lk1_ctl_phy1(lk1_ctl_phy1);
|
657 |
|
|
tb.phy1_consume_lk1(phy1_consume_lk1);
|
658 |
|
|
|
659 |
|
|
tb.lk1_disable_drivers_phy1(lk1_disable_drivers_phy1);
|
660 |
|
|
tb.lk1_disable_receivers_phy1(lk1_disable_receivers_phy1);
|
661 |
|
|
|
662 |
|
|
tb.ui_memory_write0(ui_memory_write0);
|
663 |
|
|
tb.ui_memory_write1(ui_memory_write1);//20
|
664 |
|
|
tb.ui_memory_write_address(ui_memory_write_address);
|
665 |
|
|
tb.ui_memory_write_data(ui_memory_write_data);
|
666 |
|
|
|
667 |
|
|
tb.ui_memory_read_address0(ui_memory_read_address0);
|
668 |
|
|
tb.ui_memory_read_address1(ui_memory_read_address1);
|
669 |
|
|
tb.ui_memory_read_data0(ui_memory_read_data0);
|
670 |
|
|
tb.ui_memory_read_data1(ui_memory_read_data1);
|
671 |
|
|
|
672 |
|
|
#ifdef RETRY_MODE_ENABLED
|
673 |
|
|
tb.history_memory_write0(history_memory_write0);
|
674 |
|
|
tb.history_memory_write_address0(history_memory_write_address0);
|
675 |
|
|
tb.history_memory_write_data0(history_memory_write_data0);
|
676 |
|
|
tb.history_memory_read_address0(history_memory_read_address0);//30
|
677 |
|
|
tb.history_memory_output0(history_memory_output0);
|
678 |
|
|
|
679 |
|
|
tb.history_memory_write1(history_memory_write1);
|
680 |
|
|
tb.history_memory_write_address1(history_memory_write_address1);
|
681 |
|
|
tb.history_memory_write_data1(history_memory_write_data1);
|
682 |
|
|
tb.history_memory_read_address1(history_memory_read_address1);
|
683 |
|
|
tb.history_memory_output1(history_memory_output1);
|
684 |
|
|
|
685 |
|
|
#endif
|
686 |
|
|
|
687 |
|
|
|
688 |
|
|
tb.memory_write0(memory_write0);
|
689 |
|
|
tb.memory_write_address_vc0(memory_write_address_vc0);
|
690 |
|
|
tb.memory_write_address_buffer0(memory_write_address_buffer0);
|
691 |
|
|
tb.memory_write_address_pos0(memory_write_address_pos0);//40
|
692 |
|
|
tb.memory_write_data0(memory_write_data0);
|
693 |
|
|
|
694 |
|
|
tb.memory_read_address_vc0[0](memory_read_address_vc0__0);
|
695 |
|
|
tb.memory_read_address_buffer0[0](memory_read_address_buffer0__0);
|
696 |
|
|
tb.memory_read_address_pos0[0](memory_read_address_pos0__0);//50
|
697 |
|
|
tb.memory_output0[0](memory_output0__0);
|
698 |
|
|
|
699 |
|
|
tb.memory_read_address_vc0[1](memory_read_address_vc0__1);
|
700 |
|
|
tb.memory_read_address_buffer0[1](memory_read_address_buffer0__1);
|
701 |
|
|
tb.memory_read_address_pos0[1](memory_read_address_pos0__1);//50
|
702 |
|
|
tb.memory_output0[1](memory_output0__1);
|
703 |
|
|
|
704 |
|
|
|
705 |
|
|
tb.memory_write1(memory_write1);
|
706 |
|
|
tb.memory_write_address_vc1(memory_write_address_vc1);
|
707 |
|
|
tb.memory_write_address_buffer1(memory_write_address_buffer1);
|
708 |
|
|
tb.memory_write_address_pos1(memory_write_address_pos1);
|
709 |
|
|
tb.memory_write_data1(memory_write_data1);
|
710 |
|
|
|
711 |
|
|
tb.memory_read_address_vc1[0](memory_read_address_vc1__0);
|
712 |
|
|
tb.memory_read_address_buffer1[0](memory_read_address_buffer1__0);
|
713 |
|
|
tb.memory_read_address_pos1[0](memory_read_address_pos1__0);
|
714 |
|
|
tb.memory_output1[0](memory_output1__0);
|
715 |
|
|
|
716 |
|
|
tb.memory_read_address_vc1[1](memory_read_address_vc1__1);
|
717 |
|
|
tb.memory_read_address_buffer1[1](memory_read_address_buffer1__1);
|
718 |
|
|
tb.memory_read_address_pos1[1](memory_read_address_pos1__1);
|
719 |
|
|
tb.memory_output1[1](memory_output1__1);
|
720 |
|
|
|
721 |
|
|
|
722 |
|
|
tb.ui_packet_usr(ui_packet_usr);
|
723 |
|
|
tb.ui_vc_usr(ui_vc_usr);
|
724 |
|
|
tb.ui_side_usr(ui_side_usr);
|
725 |
|
|
tb.ui_directroute_usr(ui_directroute_usr);
|
726 |
|
|
tb.ui_eop_usr(ui_eop_usr);
|
727 |
|
|
tb.ui_available_usr(ui_available_usr);
|
728 |
|
|
tb.ui_output_64bits_usr(ui_output_64bits_usr);
|
729 |
|
|
tb.usr_consume_ui(usr_consume_ui);
|
730 |
|
|
tb.usr_packet_ui(usr_packet_ui);
|
731 |
|
|
tb.usr_available_ui(usr_available_ui);
|
732 |
|
|
tb.usr_side_ui(usr_side_ui);
|
733 |
|
|
tb.ui_freevc0_usr(ui_freevc0_usr);
|
734 |
|
|
tb.ui_freevc1_usr(ui_freevc1_usr);
|
735 |
|
|
tb.usr_receivedResponseError_csr(usr_receivedResponseError_csr);
|
736 |
|
|
}
|
737 |
|
|
};
|
738 |
|
|
|