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// cd_cmdwdata_buffer_l3.h
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/* ***** BEGIN LICENSE BLOCK *****
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* Version: MPL 1.1
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*
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* The contents of this file are subject to the Mozilla Public License Version
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* 1.1 (the "License"); you may not use this file except in compliance with
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* the License. You may obtain a copy of the License at
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* http://www.mozilla.org/MPL/
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*
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* Software distributed under the License is distributed on an "AS IS" basis,
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* WITHOUT WARRANTY OF ANY KIND, either express or implied. See the License
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* for the specific language governing rights and limitations under the
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* License.
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*
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* The Original Code is HyperTransport Tunnel IP Core.
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*
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* The Initial Developer of the Original Code is
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* Ecole Polytechnique de Montreal.
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* Portions created by the Initial Developer are Copyright (C) 2005
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* the Initial Developer. All Rights Reserved.
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*
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* Contributor(s):
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* Max-Elie Salomon
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* Ami Castonguay <acastong@grm.polymtl.ca>
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*
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* Alternatively, the contents of this file may be used under the terms
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* of the Polytechnique HyperTransport Tunnel IP Core Source Code License
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* (the "PHTICSCL License", see the file PHTICSCL.txt), in which case the
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* provisions of PHTICSCL License are applicable instead of those
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* above. If you wish to allow use of your version of this file only
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* under the terms of the PHTICSCL License and not to allow others to use
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* your version of this file under the MPL, indicate your decision by
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* deleting the provisions above and replace them with the notice and
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* other provisions required by the PHTICSCL License. If you do not delete
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* the provisions above, a recipient may use your version of this file
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* under either the MPL or the PHTICSCL License."
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*
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* ***** END LICENSE BLOCK ***** */
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#ifndef CD_CMDWDATA_BUFFER_L3_H
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#define CD_CMDWDATA_BUFFER_L3_H
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#include "../core_synth/synth_datatypes.h"
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#include "../core_synth/constants.h"
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///Command register sub-module for the decoder module
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/**
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@description A buffer (register) for control commands
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that do have data associated
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@author Max-Elie Salomon
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Ami Castonguay
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*/
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class cd_cmdwdata_buffer_l3 : public sc_module
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{
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public:
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//*******************************
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// Inputs
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//*******************************
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///Clock to synchronize module
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sc_in< bool > clk;
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///Input bit vector
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sc_in< sc_bv<32> > dataDword;
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///Address of data associated to the control command
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sc_in< sc_uint<BUFFERS_ADDRESS_WIDTH> > db_address_cd;
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///Enables registering of the first doubleword of the packet
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sc_in< bool > enCtl1;
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///Enables registering of the second doubleword of the packet
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sc_in< bool > enCtl2;
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///Indication that the packet has an address error
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sc_in< bool > error64BitsCtlwData;
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///Clear the register
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sc_in< bool > resetx;
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//*******************************
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// Outputs
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//*******************************
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///Output control packet
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sc_out< syn_ControlPacketComplete > packet;
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/**Where we are storing data. This is used by the ro to know
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if we have finished receiving the data of a packet, so it can know if
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it can send it.*/
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sc_out< sc_uint<BUFFERS_ADDRESS_WIDTH> > cd_data_pending_addr_ro;
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/**
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Process of updating the output of the register
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according to the inputs present on the rising edge
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of the clock
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*/
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void bufferize();
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///SystemC Macro
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SC_HAS_PROCESS(cd_cmdwdata_buffer_l3);
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///SystemC Macro - Module constructor
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cd_cmdwdata_buffer_l3(sc_module_name name);
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};
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#endif
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