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acastong |
//decoder_l2.h
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/* ***** BEGIN LICENSE BLOCK *****
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* Version: MPL 1.1
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*
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* The contents of this file are subject to the Mozilla Public License Version
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* 1.1 (the "License"); you may not use this file except in compliance with
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* the License. You may obtain a copy of the License at
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* http://www.mozilla.org/MPL/
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*
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* Software distributed under the License is distributed on an "AS IS" basis,
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* WITHOUT WARRANTY OF ANY KIND, either express or implied. See the License
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* for the specific language governing rights and limitations under the
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* License.
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*
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* The Original Code is HyperTransport Tunnel IP Core.
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*
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* The Initial Developer of the Original Code is
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* Ecole Polytechnique de Montreal.
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* Portions created by the Initial Developer are Copyright (C) 2005
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* the Initial Developer. All Rights Reserved.
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*
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* Contributor(s):
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* Max-Elie Salomon
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* Ami Castonguay <acastong@grm.polymtl.ca>
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*
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* Alternatively, the contents of this file may be used under the terms
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* of the Polytechnique HyperTransport Tunnel IP Core Source Code License
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* (the "PHTICSCL License", see the file PHTICSCL.txt), in which case the
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* provisions of PHTICSCL License are applicable instead of those
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* above. If you wish to allow use of your version of this file only
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* under the terms of the PHTICSCL License and not to allow others to use
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* your version of this file under the MPL, indicate your decision by
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* deleting the provisions above and replace them with the notice and
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* other provisions required by the PHTICSCL License. If you do not delete
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* the provisions above, a recipient may use your version of this file
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* under either the MPL or the PHTICSCL License."
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*
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* ***** END LICENSE BLOCK ***** */
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#include "../core_synth/synth_datatypes.h"
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#include "../core_synth/constants.h"
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#ifndef DECODER_L2_H
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#define DECODER_L2_H
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//Forward declerations
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class cd_state_machine_l3;
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class cd_counter_l3;
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class cd_cmd_buffer_l3;
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class cd_cmdwdata_buffer_l3;
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class cd_mux_l3;
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class cd_nop_handler_l3;
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#ifdef RETRY_MODE_ENABLED
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class cd_packet_crc_l3;
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class cd_history_rx_l3;
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#endif
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///Input decoder for the Hypertransport module
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/**
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@class decoder_l2
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@description The decoder has the task of first analyzing what dwords
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are received from the link and to organize them in packets
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that can be stored in the command buffer (reordering) or
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data buffer. It also takes care of sending flow control (nop)
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information to the flow control module.
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When malformed or invalid packets are received, an error in logged
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but most likely, everything that will follow will be completely
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corrupted...
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If the retry mode is on, it verifies that the
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per-packet CRC's are valid. If they are not, then the decoder
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initiates a retry sequence. It also ignores stomped packet. If
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a stomped packet that has data associated is received, the data
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that's already stored in the databuffers is dropped.
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This is basically just a big state machine that directs the received
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dwords. There are a lot of states because it is possible to insert
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a command packet inside a data transfer. Per packet CRC's also complicate
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things quite a bit because there is no garantee in which order they will
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arrive when a command packet is inserted in a data transfer. *Note: per
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packet CRC was simplified with revision 2.0b of the spec : inserted
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command CRC must follow the packet CRC.
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Contains the following sub-modules:
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-state_machine
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-counter
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-cmd_buffer
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-cmdwdata_buffer
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-mux
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-NOP_handler
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-historyRxCnt
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@author Max-Elie Salomon
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Ami Castonguay
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*/
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class decoder_l2 : public sc_module
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{
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public:
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//*******************************
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// Internal signals
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//*******************************
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//-------------------------------
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// state machine / buffer 1
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//-------------------------------
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///Load the lower 32 bits of the buffer with no data
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sc_signal< bool > enCtl1;
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///Load the upper 32 bits of the buffer with no data
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sc_signal< bool > enCtl2;
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//----------------------------------------
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// state machine / buffer 2 (with data)
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//----------------------------------------
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///Load the lower 32 bits of the buffer with data
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sc_signal< bool > enCtlWdata1;
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///Load the upper 32 bits of the buffer with data
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sc_signal< bool > enCtlWdata2;
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//----------------------------------------
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// state machine / counter
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//----------------------------------------
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///Flag indicating the next valid data dword will be the last
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sc_signal< bool > end_of_count;
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///Flag indicating the last data dword has been received
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//sc_signal< bool > count_done;
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//----------------------------------------
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// buffers / MUX
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//----------------------------------------
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///The buffer for the packet without data
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sc_signal< syn_ControlPacketComplete > ctlPacket0;
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///The buffer for the packet with data
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sc_signal< syn_ControlPacketComplete > ctlPacket1;
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///To select wich buffer is being outputed between ctlPacket0 and ctlPacket1
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sc_signal< bool > selCtlPckt;
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//----------------------------------------
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// state machine / NOP handler
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//----------------------------------------
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///A nop has been received, register the nop content
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sc_signal< bool > setNopCnt;
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///Send a notification that a nop has been received/validated
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sc_signal< bool > send_nop_notification;
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#ifdef RETRY_MODE_ENABLED
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//----------------------------------------
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// state machine / NOP handler
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//----------------------------------------
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//Signals for CRC
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///If the signal on the input matches the calculated CRC1
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sc_signal<bool> crc1_good;
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///If the signal on the input is the inverse of the calculated CRC1
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sc_signal<bool> crc1_stomped;
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///Add the input vector to the CRC1 calculation
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sc_signal<bool> crc1_enable;
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///Reset the CRC1 value
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sc_signal<bool> crc1_reset;
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///If the signal on the input matches the calculated CRC2
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sc_signal<bool> crc2_good;
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///If the signal on the input is the inverse of the calculated CRC2
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sc_signal<bool> crc2_stomped;
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///Add the input vector to the CRC2 calculation
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sc_signal<bool> crc2_enable;
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///Reset the CRC1 value
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sc_signal<bool> crc2_reset;
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///If CTL is activated, should CRC2 be calculated instead of CRC1
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sc_signal< bool > crc2_if_ctl;
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#endif
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//----------------------------------------
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// other internal signals
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//----------------------------------------
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///Command of the packet received from the input fifo
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sc_signal< PacketCommand > cmd;
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///error signal for extended 64 address
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sc_signal< bool > error64Bits;
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///error signal for extended 64 address for packet that has data associated
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sc_signal< bool > error64BitsCtlwData;
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// /get an address from data buffer and set data count
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sc_signal< bool > getAddressSetCnt;
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//----------------------------------------
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// sub-module instanciation
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//----------------------------------------
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cd_state_machine_l3 *SM;///<The controler of the decoder
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cd_counter_l3 *CNT;///<A simple counter
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cd_cmd_buffer_l3 *CMD_BUF;///<A command buffer
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cd_cmdwdata_buffer_l3 *CMDWDATA_BUF;///<A command buffer for packets that contain data
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cd_mux_l3 *MUX;///<A simple multiplexer
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cd_nop_handler_l3 *NOP_HANDLER;///<Module that handles received nop packets
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#ifdef RETRY_MODE_ENABLED
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cd_history_rx_l3 *HISTORY;///<Counts the number of received packets for history (retry mode) purpose
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cd_packet_crc_l3 *packet_crc_unit;///<Calcultates and checks per-packet CRC
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#endif
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//*******************************
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// General signals
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//*******************************
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///Clock to synchronize module
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sc_in < bool > clk;
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///Warm Reset to initialize module
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sc_in < bool > resetx;
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//*******************************
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// Signals for Control Buffer
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//*******************************
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/**Packet to be transmitted to control buffer module*/
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sc_out< syn_ControlPacketComplete > cd_packet_ro;
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/**Enables control buffer module to read cd_packet_ro port*/
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sc_out< bool > cd_available_ro;
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/**If we're currently receiving data. This is used by the ro to know
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if we have finished receiving the data of a packet, so it can know if
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it can send it.*/
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sc_out<bool> cd_data_pending_ro;
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/**Where we are storing data. This is used by the ro to know
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if we have finished receiving the data of a packet, so it can know if
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it can send it.*/
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sc_out<sc_uint<BUFFERS_ADDRESS_WIDTH> > cd_data_pending_addr_ro;
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//*******************************
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// Signals for Data Buffer
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//*******************************
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///ddress of data in data buffer module
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sc_in< sc_uint<BUFFERS_ADDRESS_WIDTH> > db_address_cd;
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///Get an address form data buffer module
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sc_out< bool > cd_getaddr_db;
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///Size of data packet to be written
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sc_out< sc_uint<4> > cd_datalen_db;
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///Virtual channel where data will be written
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sc_out< VirtualChannel > cd_vctype_db;
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///Data to be written in data buffer module
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sc_out< sc_bv<32> > cd_data_db;
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///Enables data buffer to read cd_data_db port
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sc_out< bool > cd_write_db;
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#ifdef RETRY_MODE_ENABLED
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///Erase signal for packet stomping
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sc_out< bool > cd_drop_db;
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#endif
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//*************************************
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// Signals to CSR
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//*************************************
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///A protocol error has been detected
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sc_out< bool > cd_protocol_error_csr;
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///A sync packet has been received
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sc_out< bool > cd_sync_detected_csr;
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#ifdef RETRY_MODE_ENABLED
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///If retry mode is active
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sc_in< bool > csr_retry;
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#endif
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//*******************************
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// Signals from link
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//*******************************
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///Bit vector input from the FIFO
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sc_in< sc_bv<32> > lk_dword_cd;
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///Control bit
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sc_in< bool > lk_hctl_cd;
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///Control bit
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sc_in< bool > lk_lctl_cd;
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///FIFO is ready to be read from
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sc_in< bool > lk_available_cd;
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#ifdef RETRY_MODE_ENABLED
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///If a retry sequence is initiated by link
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sc_in< bool > lk_initiate_retry_disconnect;
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#endif
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//*******************************
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// Signals for Forwarding module
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//*******************************
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#ifdef RETRY_MODE_ENABLED
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///History count
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sc_out< sc_uint<8> > cd_rx_next_pkt_to_ack_fc;
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///rxPacketToAck (retry mode)
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sc_out< sc_uint<8> > cd_nop_ack_value_fc;
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#endif
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///Info registered from NOP word
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sc_out< sc_bv<12> > cd_nopinfo_fc;
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///Signal that new nop info are available
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sc_out< bool > cd_nop_received_fc;
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#ifdef RETRY_MODE_ENABLED
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///Start the sequence for a retry disconnect
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sc_out< bool > cd_initiate_retry_disconnect;
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///A stomped packet has been received
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sc_out<bool> cd_received_stomped_csr;
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///Let the reordering know we received a non flow control stomped packet
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/** When this situation happens, packet available bit does not become
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asserted but the correct packet is sent, which can be used to know
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from which VC to free a flow control credit.
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*/
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sc_out<bool> cd_received_non_flow_stomped_ro;
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#endif
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///The link can start a sequence for a ldtstop disconnect
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sc_out< bool > cd_initiate_nonretry_disconnect_lk;
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/**
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This process sets outputs that need to become
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available by the end of the clock time where an
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input bit vector is received:
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cd_data_db
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cd_getaddr_db
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cd_datalen_db
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cd_vctype_db
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erasedAddress
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*/
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void set_outputs();
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///SystemC macro
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SC_HAS_PROCESS(decoder_l2);
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/**
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Module constructor
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*/
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decoder_l2( sc_module_name name);
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#ifdef SYSTEMC_SIM
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~decoder_l2();
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#endif
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};
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#endif
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