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acastong |
//csr_l2_tb.h
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/* ***** BEGIN LICENSE BLOCK *****
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* Version: MPL 1.1
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*
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* The contents of this file are subject to the Mozilla Public License Version
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* 1.1 (the "License"); you may not use this file except in compliance with
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* the License. You may obtain a copy of the License at
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* http://www.mozilla.org/MPL/
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*
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* Software distributed under the License is distributed on an "AS IS" basis,
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* WITHOUT WARRANTY OF ANY KIND, either express or implied. See the License
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* for the specific language governing rights and limitations under the
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* License.
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*
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* The Original Code is HyperTransport Tunnel IP Core.
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*
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* The Initial Developer of the Original Code is
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* Ecole Polytechnique de Montreal.
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* Portions created by the Initial Developer are Copyright (C) 2005
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* the Initial Developer. All Rights Reserved.
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*
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* Contributor(s):
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* Ami Castonguay <acastong@grm.polymtl.ca>
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*
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* Alternatively, the contents of this file may be used under the terms
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* of the Polytechnique HyperTransport Tunnel IP Core Source Code License
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* (the "PHTICSCL License", see the file PHTICSCL.txt), in which case the
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* provisions of PHTICSCL License are applicable instead of those
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* above. If you wish to allow use of your version of this file only
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* under the terms of the PHTICSCL License and not to allow others to use
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* your version of this file under the MPL, indicate your decision by
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* deleting the provisions above and replace them with the notice and
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* other provisions required by the PHTICSCL License. If you do not delete
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* the provisions above, a recipient may use your version of this file
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* under either the MPL or the PHTICSCL License."
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*
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* ***** END LICENSE BLOCK ***** */
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#ifndef CSR_L2_TB_H
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#define CSR_L2_TB_H
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#include "../../rtl/systemc/core_synth/synth_datatypes.h"
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#include "../../rtl/systemc/core_synth/constants.h"
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#include "../core/ht_datatypes.h"
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#include <deque>
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///Testbench for the csr_l2 module
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/**
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@class csr_l2_tb
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@author Ami Castonguay
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*/
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class csr_l2_tb : public sc_module {
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///Structure that groups both packet complete and it's associated data
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struct PacketContainerWithData{
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ControlPacketComplete pkt_cplt;
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int data[16];
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};
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///Expected response to a request to CSR
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struct ExpectedResponse{
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unsigned int dwords[17];///< The dwords of the response, including data
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unsigned int size_with_data;///< Size of the response, including data
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};
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public:
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/// Global system clock signal.
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sc_in_clk clk;
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/** Warm Reset signal (active low) */
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sc_out<bool> resetx;
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///Power is stable (used for cold reset of the design
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sc_out<bool> pwrok;
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///LDSTOP sequence (power saving mode)
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sc_out<bool> ldtstopx;
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///If the tunnel is in sync mode
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/**
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When a critical error is detected, sync flood is sent. When
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a sync flood is received, we also fall in sync mode. This
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cascades and resyncs the complete HT chain.
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*/
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sc_in<bool> csr_sync;
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//****************************************************
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// Signals for communication with User Interface module
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//****************************************************
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/** Access to the databuffer is shared with UI, must request acess*/
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sc_in<bool> csr_request_databuffer0_access_ui;
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/** Access to the databuffer is shared with UI, must request acess*/
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sc_in<bool> csr_request_databuffer1_access_ui;
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/** When the access to databuffer is granted following the assertion of
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::csr_request_databuffer0_access_ui or ::csr_request_databuffer1_access_ui*/
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sc_out<bool> ui_databuffer_access_granted_csr;
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//****************************************************
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// Signals for communication with Reordering module
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//****************************************************
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/** @name Reordering
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* Signals for communication with Reordering module
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*/
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//@{
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/** Packet is ready to read from Reordering module */
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sc_out<bool> ro0_available_csr;
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/** Packet from Reordering module */
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sc_out<syn_ControlPacketComplete > ro0_packet_csr;
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/** Packet from Reordering has been read by CSR */
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sc_in<bool> csr_ack_ro0;
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/** Packet is ready to read from Reordering module */
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sc_out<bool> ro1_available_csr;
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/** Packet from Reordering module */
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sc_out<syn_ControlPacketComplete > ro1_packet_csr;
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/** Packet from Reordering has been read by CSR */
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sc_in<bool> csr_ack_ro1;
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//@}
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//*****************************************************
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// Signals for communication with Data Buffer module
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//*****************************************************
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/** @name DataBuffer
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* Signals for communication with Data Buffer module
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*/
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//@{
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/** Consume data from Data Buffer */
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sc_in<bool> csr_read_db0;
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/** Consume data from Data Buffer 1 */
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sc_in<bool> csr_read_db1;
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/** Address of the data packet requested in Data Buffer 0 */
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sc_in<sc_uint<BUFFERS_ADDRESS_WIDTH> > csr_address_db0;
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/** Address of the data packet requested in Data Buffer 1 */
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sc_in<sc_uint<BUFFERS_ADDRESS_WIDTH> > csr_address_db1;
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/** Virtual Channel of the data requested in Data Buffer 0 */
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sc_in<VirtualChannel > csr_vctype_db0;
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/** Virtual Channel of the data requested in Data Buffer 1 */
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sc_in<VirtualChannel > csr_vctype_db1;
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/** 32 bit data sent from Data Buffer to CSR */
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sc_out<sc_bv<32> > db0_data_csr;
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/** 32 bit data sent from Data Buffer to CSR */
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sc_out<sc_bv<32> > db1_data_csr;
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/** Last dword of data from Data Buffer 0 */
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sc_in<bool> csr_erase_db0;
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/** Last dword of data from Data Buffer 1 */
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sc_in<bool> csr_erase_db1;
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//@}
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//******************************************************
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// Signals for communication with Flow Control module
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//******************************************************
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/** @name FlowControl
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* Signals for communication with Flow Control module
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*/
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//@{
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/** Request to Flow Control to send packet */
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sc_in<bool> csr_available_fc0;
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/** 32 bit packet or data to Flow Control */
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sc_in<sc_bv<32> > csr_dword_fc0;
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/** Flow Control has read the last 32 bit packet or data */
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sc_out<bool> fc0_ack_csr;
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/** Request to Flow Control to send packet */
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sc_in<bool> csr_available_fc1;
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/** 32 bit packet or data to Flow Control */
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sc_in<sc_bv<32> > csr_dword_fc1;
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/** Flow Control has read the last 32 bit packet or data */
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sc_out<bool> fc1_ack_csr;
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//@}
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///SystemC Macro
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SC_HAS_PROCESS(csr_l2_tb);
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///Testbench module constructor
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csr_l2_tb(sc_module_name name);
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///Queue of packets to send from size 0
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std::deque<PacketContainerWithData> to_send0;
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///Queue of packets that are expected to be received on side 0
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std::deque<ExpectedResponse> to_receive0;
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///Queue of packets to send from size 1
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std::deque<PacketContainerWithData> to_send1;
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///Queue of packets that are expected to be received on side 1
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std::deque<ExpectedResponse> to_receive1;
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///Queue of packets to send from any side (
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std::deque<PacketContainerWithData> to_send;
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///Queue of packets that are expected to be received on any side
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std::deque<ExpectedResponse> to_receive;
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/**
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When sending a packet from within the queue of packets to send, if
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it contains data, it must then be sent by a process simulating the databuffer.
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The information about the data to be sent from side 0 is store in these variables
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*/
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//@{
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///Actual data to send
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unsigned int data0[16];
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///Number of dwords to send
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unsigned int data_size0;
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///Number of dwords to are currently sent
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unsigned int data_sent0;
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///If the data being sent to CSR is valid (it takes a delay of one cycle)
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sc_signal<bool> valid_output0;
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///The address where the data is stored
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sc_uint<BUFFERS_ADDRESS_WIDTH> data_address0;
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///The virtual channel of the data
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VirtualChannel data_vc0;
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//@}
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/**
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When sending a packet from within the queue of packets to send, if
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it contains data, it must then be sent by a process simulating the databuffer.
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The information about the data to be sent from side 1 is store in these variables
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*/
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//@{
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///Actual data to send
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unsigned int data1[16];
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///Number of dwords to send
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unsigned int data_size1;
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///Number of dwords to are currently sent
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unsigned int data_sent1;
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///If the data being sent to CSR is valid (it takes a delay of one cycle)
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sc_signal<bool> valid_output1;
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///The address where the data is stored
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sc_uint<BUFFERS_ADDRESS_WIDTH> data_address1;
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///The virtual channel of the data
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VirtualChannel data_vc1;
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//@}
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///The number of dword received fomr the CSR response to side 0
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unsigned int received0;
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///The number of dword received fomr the CSR response to side 1
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unsigned int received1;
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///The side from which the request has been sent
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/** to_send queue contains packets that can be sent to any side,
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this stores which side it is sent to so that the response can
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be correctly verified.
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*/
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int side_pkt_sent;
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///Process that sends packets in the queues to the CSR module
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void send_packets_csr();
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///Process that verifies that the responses of the CSR are corerct
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void verify_csr_response();
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///Process that simulates the databuffer so that the CSR can access data
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void simulate_databuffer();
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///Process that generates packets to be sent to CSR
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void generate_csr_requests_and_responses();
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///Randomly acks dwords sent to flow control
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void flow_control_read_signals();
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///Process that takes care of granting access to databuffer when CSR needs data
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void grant_access_databuffer();
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};
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#endif
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