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acastong |
//main.cpp - CSR testbench
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/* ***** BEGIN LICENSE BLOCK *****
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* Version: MPL 1.1
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*
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* The contents of this file are subject to the Mozilla Public License Version
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* 1.1 (the "License"); you may not use this file except in compliance with
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* the License. You may obtain a copy of the License at
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* http://www.mozilla.org/MPL/
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*
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* Software distributed under the License is distributed on an "AS IS" basis,
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* WITHOUT WARRANTY OF ANY KIND, either express or implied. See the License
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* for the specific language governing rights and limitations under the
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* License.
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*
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* The Original Code is HyperTransport Tunnel IP Core.
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*
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* The Initial Developer of the Original Code is
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* Ecole Polytechnique de Montreal.
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* Portions created by the Initial Developer are Copyright (C) 2005
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* the Initial Developer. All Rights Reserved.
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*
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* Contributor(s):
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* Ami Castonguay <acastong@grm.polymtl.ca>
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*
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* Alternatively, the contents of this file may be used under the terms
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* of the Polytechnique HyperTransport Tunnel IP Core Source Code License
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* (the "PHTICSCL License", see the file PHTICSCL.txt), in which case the
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* provisions of PHTICSCL License are applicable instead of those
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* above. If you wish to allow use of your version of this file only
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* under the terms of the PHTICSCL License and not to allow others to use
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* your version of this file under the MPL, indicate your decision by
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* deleting the provisions above and replace them with the notice and
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* other provisions required by the PHTICSCL License. If you do not delete
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* the provisions above, a recipient may use your version of this file
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* under either the MPL or the PHTICSCL License."
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*
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* ***** END LICENSE BLOCK ***** */
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#include "../../rtl/systemc/core_synth/synth_datatypes.h"
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#include "../../rtl/systemc/core_synth/constants.h"
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#include "../../rtl/systemc/csr_l2/csr_l2.h"
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#include "csr_l2_tb.h"
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#include <iostream>
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#include <string>
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#include <sstream>
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#include <iomanip>
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using namespace std;
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int sc_main( int argc, char* argv[] ){
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//The Design Under Test
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csr_l2* dut = new csr_l2("csr_l2");
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//The TestBench
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csr_l2_tb* tb = new csr_l2_tb("csr_l2_tb");
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//Signals used to link the design to the testbench
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sc_clock clk("clk", 1); // system clk
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/** Warm Reset signal (active low) */
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sc_signal<bool> resetx;
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sc_signal<bool> pwrok;
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sc_signal<bool> ldtstopx;
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///If the tunnel is in sync mode
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/**
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When a critical error is detected, sync flood is sent. When
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a sync flood is received, we also fall in sync mode. This
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cascades and resyncs the complete HT chain.
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*/
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sc_signal<bool> csr_sync;
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//****************************************************
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// Signals for communication with User Interface module
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//****************************************************
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sc_signal<bool> csr_request_databuffer0_access_ui;
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sc_signal<bool> csr_request_databuffer1_access_ui;
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sc_signal<bool> ui_databuffer_access_granted_csr;
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//****************************************************
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// Signals for communication with Reordering module
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//****************************************************
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/** @name Reordering
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* Signals for communication with Reordering module
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*/
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//@{
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/** Packet is ready to read from Reordering module */
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sc_signal<bool> ro0_available_csr;
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/** Packet from Reordering module */
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sc_signal<syn_ControlPacketComplete > ro0_packet_csr;
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/** Packet from Reordering has been read by CSR */
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sc_signal<bool> csr_ack_ro0;
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/** Packet is ready to read from Reordering module */
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sc_signal<bool> ro1_available_csr;
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/** Packet from Reordering module */
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sc_signal<syn_ControlPacketComplete > ro1_packet_csr;
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/** Packet from Reordering has been read by CSR */
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sc_signal<bool> csr_ack_ro1;
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//@}
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//*****************************************************
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// Signals for communication with Data Buffer module
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//*****************************************************
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/** @name DataBuffer
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* Signals for communication with Data Buffer module
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*/
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//@{
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/** Consume data from Data Buffer */
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sc_signal<bool> csr_read_db0;
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sc_signal<bool> csr_read_db1;
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/** Address of the data packet requested in Data Buffer */
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sc_signal<sc_uint<BUFFERS_ADDRESS_WIDTH> > csr_address_db0;
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sc_signal<sc_uint<BUFFERS_ADDRESS_WIDTH> > csr_address_db1;
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/** Virtual Channel of the data requested in Data Buffer */
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sc_signal<VirtualChannel > csr_vctype_db0;
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sc_signal<VirtualChannel > csr_vctype_db1;
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/** 32 bit data sent from Data Buffer to CSR */
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sc_signal<sc_bv<32> > db0_data_csr;
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sc_signal<sc_bv<32> > db1_data_csr;
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/** Last dword of data from Data Buffer */
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sc_signal<bool> csr_erase_db0;
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sc_signal<bool> csr_erase_db1;
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//@}
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//******************************************************
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// Signals for communication with Flow Control module
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//******************************************************
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/** @name FlowControl
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* Signals for communication with Flow Control module
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*/
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//@{
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/** Request to Flow Control to send packet */
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sc_signal<bool> csr_available_fc0;
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/** 32 bit packet or data to Flow Control */
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sc_signal<sc_bv<32> > csr_dword_fc0;
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/** Flow Control has read the last 32 bit packet or data */
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sc_signal<bool> fc0_ack_csr;
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/** Request to Flow Control to send packet */
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sc_signal<bool> csr_available_fc1;
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/** 32 bit packet or data to Flow Control */
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sc_signal<sc_bv<32> > csr_dword_fc1;
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/** Flow Control has read the last 32 bit packet or data */
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sc_signal<bool> fc1_ack_csr;
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//@}
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//************************************************************
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// Normal input signals from other modules to CSR registers
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//************************************************************
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/*
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* Input signals received from other modules to CSR
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*/
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///Signals that come from analyzed packet going through the UI
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//@{
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sc_signal<bool> ui_sendingPostedDataError_csr;
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sc_signal<bool> ui_sendingTargetAbort_csr;
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sc_signal<bool> ui_receivedResponseDataError_csr;
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sc_signal<bool> ui_receivedPostedDataError_csr;
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sc_signal<bool> ui_receivedTargetAbort_csr;
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sc_signal<bool> ui_receivedMasterAbort_csr;
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//@}
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///When the user received a response with an error
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sc_signal<bool> usr_receivedResponseError_csr;
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///Overflow of the buffers of the databuffer0
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sc_signal<bool> db0_overflow_csr;
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///Overflow of the buffers of the reordering0
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sc_signal<bool> ro0_overflow_csr;
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///Overflow of the buffers of the databuffer1
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sc_signal<bool> db1_overflow_csr;
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///Overflow of the buffers of the reordering1
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sc_signal<bool> ro1_overflow_csr;
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///If the Error Handler consumes data, it means that there is an end of chain error
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//@{
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sc_signal<bool> eh0_ack_ro0;
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sc_signal<bool> eh1_ack_ro1;
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//@}
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/// Link0 has completed it's initialization
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sc_signal<bool> lk0_initialization_complete_csr;
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#ifdef RETRY_MODE_ENABLED
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///Link0 asks to initiate a retry disconnect (probably due to a protocol error)
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sc_signal<bool> lk0_initiate_retry_disconnect;
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#endif
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/// Link0 has completed it's initialization
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sc_signal<bool > lk0_crc_error_csr;
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/// Link0 detected a sync packet
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//sc_signal<bool> lk0_sync_detected_csr;
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/// Link0 detected a protocol error
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sc_signal<bool> lk0_protocol_error_csr;
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/// Link1 has completed it's initialization
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sc_signal<bool> lk1_initialization_complete_csr;
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#ifdef RETRY_MODE_ENABLED
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///Link1 asks to initiate a retry disconnect (probably due to a protocol error)
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sc_signal<bool> lk1_initiate_retry_disconnect;
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#endif
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/// Link1 has completed it's initialization
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sc_signal<bool > lk1_crc_error_csr;
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/// Link1 detected a sync packet
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//sc_signal<bool> lk1_sync_detected_csr;
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/// Link1 detected a protocol error
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sc_signal<bool> lk1_protocol_error_csr;
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/** Signal to register Interface->LinkError_0->ProtocolError_0 */
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sc_signal<bool> cd0_protocol_error_csr;
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///When the command decoder0 detects a sync
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sc_signal<bool> cd0_sync_detected_csr;
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/** Signal to register Interface->LinkError_1->ProtocolError_1 */
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sc_signal<bool> cd1_protocol_error_csr;
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#ifdef RETRY_MODE_ENABLED
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/** Signal to register ErrorRetry->Status_0->RetrySent_0 */
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sc_signal<bool> cd0_initiate_retry_disconnect;
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/** Signal to register ErrorRetry->Status_0->StompReceived_0 */
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sc_signal<bool> cd0_received_stomped_csr;
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/** Signal to register ErrorRetry->Status_1->RetrySent_1 */
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sc_signal<bool> cd1_initiate_retry_disconnect;
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/** Signal to register ErrorRetry->Status_1->StompReceived_1 */
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sc_signal<bool> cd1_received_stomped_csr;
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#endif
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///When the command decode1r detects a sync
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sc_signal<bool> cd1_sync_detected_csr;
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///Update the registers with the value of "link failure" from the link
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sc_signal<bool> lk0_update_link_failure_property_csr;
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///Update the registers with the value of "link width" from the link
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sc_signal<bool> lk0_update_link_width_csr;
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///Detected link width (only valid when lk0_update_link_width_csr)
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sc_signal<sc_bv<3> > lk0_sampled_link_width_csr;
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///Detected link failure (only valid when lk0_update_link_failure_property_csr)
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sc_signal<bool> lk0_link_failure_csr;
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///Clear the bit that forces a single CRC error to be sent
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sc_signal<bool> fc0_clear_single_error_csr;
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///Clear the bit that forces a single CRC stomp to be sent
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sc_signal<bool> fc0_clear_single_stomp_csr;
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///Update the registers with the value of "link failure" from the link
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sc_signal<bool> lk1_update_link_failure_property_csr;
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///Update the registers with the value of "link width" from the link
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sc_signal<bool> lk1_update_link_width_csr;
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///Detected link width (only valid when lk1_update_link_width_csr)
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sc_signal<sc_bv<3> > lk1_sampled_link_width_csr;
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///Detected link failure (only valid when lk1_update_link_failure_property_csr)
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sc_signal<bool> lk1_link_failure_csr;
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///Clear the bit that forces a single CRC error to be sent
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sc_signal<bool> fc1_clear_single_error_csr;
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///Clear the bit that forces a single CRC stomp to be sent
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sc_signal<bool> fc1_clear_single_stomp_csr;
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//***********************************************
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// Outputs from CSR registers to other modules
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//***********************************************
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/** Signal from register DeviceHeader->Command->csr_io_space_enable */
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sc_signal<bool> csr_io_space_enable;
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/** Signal from register DeviceHeader->Command->csr_memory_space_enable */
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sc_signal<bool> csr_memory_space_enable;
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/** Signal from register DeviceHeader->Command->csr_bus_master_enable */
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sc_signal<bool> csr_bus_master_enable;
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/** Signal from register Interface->Command->Master host */
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sc_signal<bool> csr_master_host;
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/** Signals table containing all 40 bits Base Addresses from BARs implemented */
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sc_signal<sc_bv<40> > csr_bar[NbRegsBars];
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/** Signal from register Interface->Command->csr_unit_id */
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sc_signal<sc_bv<5> > csr_unit_id;
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/** Signal from register Interface->Command->csr_default_dir */
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sc_signal<bool> csr_default_dir;
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/** Signal from register Interface->Command->csr_drop_uninit_link */
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sc_signal<bool> csr_drop_uninit_link;
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/** Signal from register Interface->LinkControl_0->csr_crc_force_error_lk0 */
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sc_signal<bool> csr_crc_force_error_lk0;
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/** Signal from register Interface->LinkControl_0->csr_end_of_chain0 */
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sc_signal<bool> csr_end_of_chain0;
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/** Signal from register Interface->LinkControl_0->csr_transmitter_off_lk0 */
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sc_signal<bool> csr_transmitter_off_lk0;
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/** Signal from register Interface->LinkControl_0->csr_ldtstop_tristate_enable_lk0 */
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sc_signal<bool> csr_ldtstop_tristate_enable_lk0;
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/** Signal from register Interface->LinkControl_0->csr_extented_ctl_lk0 */
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sc_signal<bool> csr_extented_ctl_lk0;
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/** Signal from register Interface->LinkConfiguration_0->csr_rx_link_width_lk0 */
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sc_signal<sc_bv<3> > csr_rx_link_width_lk0;
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/** Signal from register Interface->LinkConfiguration_0->csr_tx_link_width_lk0 */
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sc_signal<sc_bv<3> > csr_tx_link_width_lk0;
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6 |
acastong |
/** Signal from register Interface->Link Freq 0 */
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sc_signal<sc_bv<4> >csr_link_frequency0;
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acastong |
/** Signal from register Interface->LinkControl_1->csr_crc_force_error_lk1 */
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sc_signal<bool> csr_crc_force_error_lk1;
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/** Signal from register Interface->LinkControl_1->csr_end_of_chain1 */
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|
|
sc_signal<bool> csr_end_of_chain1;
|
324 |
|
|
/** Signal from register Interface->LinkControl_1->csr_transmitter_off_lk1 */
|
325 |
|
|
sc_signal<bool> csr_transmitter_off_lk1;
|
326 |
|
|
/** Signal from register Interface->LinkControl_1->csr_ldtstop_tristate_enable_lk1 */
|
327 |
|
|
sc_signal<bool> csr_ldtstop_tristate_enable_lk1;
|
328 |
|
|
/** Signal from register Interface->LinkControl_1->csr_extented_ctl_lk1 */
|
329 |
|
|
sc_signal<bool> csr_extented_ctl_lk1;
|
330 |
|
|
/** Signal from register Interface->LinkConfiguration_1->csr_rx_link_width_lk1 */
|
331 |
|
|
sc_signal<sc_bv<3> > csr_rx_link_width_lk1;
|
332 |
|
|
/** Signal from register Interface->LinkConfiguration_1->csr_tx_link_width_lk1 */
|
333 |
|
|
sc_signal<sc_bv<3> > csr_tx_link_width_lk1;
|
334 |
6 |
acastong |
/** Signal from register Interface->Link Freq 1 */
|
335 |
|
|
sc_signal<sc_bv<4> >csr_link_frequency1;
|
336 |
2 |
acastong |
/** Signal from register Interface->LinkError_0->csr_extended_ctl_timeout_lk0 */
|
337 |
|
|
sc_signal<bool> csr_extended_ctl_timeout_lk0;
|
338 |
|
|
#ifdef ENABLE_REORDERING
|
339 |
|
|
/** Signal from register Interface->FeatureCapability->csr_unitid_reorder_disable */
|
340 |
|
|
sc_signal<bool> csr_unitid_reorder_disable;
|
341 |
|
|
#endif
|
342 |
|
|
/** Signal from register Interface->LinkError_1->csr_extended_ctl_timeout_lk1 */
|
343 |
|
|
sc_signal<bool> csr_extended_ctl_timeout_lk1;
|
344 |
|
|
#ifdef RETRY_MODE_ENABLED
|
345 |
|
|
/** Signal from register ErrorRetry->Control_0->LinkRetryEnable_0 */
|
346 |
|
|
sc_signal<bool> csr_retry0;
|
347 |
|
|
/** Signal from register ErrorRetry->Control_0->csr_force_single_error_fc0 */
|
348 |
|
|
sc_signal<bool> csr_force_single_error_fc0;
|
349 |
|
|
/** Signal from register ErrorRetry->Control_0->csr_force_single_stomp_fc0 */
|
350 |
|
|
sc_signal<bool> csr_force_single_stomp_fc0;
|
351 |
|
|
/** Signal from register ErrorRetry->Control_1->LinkRetryEnable_1 */
|
352 |
|
|
sc_signal<bool> csr_retry1;
|
353 |
|
|
/** Signal from register ErrorRetry->Control_1->csr_force_single_error_fc1 */
|
354 |
|
|
sc_signal<bool> csr_force_single_error_fc1;
|
355 |
|
|
/** Signal from register ErrorRetry->Control_1->csr_force_single_stomp_fc1 */
|
356 |
|
|
sc_signal<bool> csr_force_single_stomp_fc1;
|
357 |
|
|
#endif
|
358 |
|
|
/** Signal from register DirectRoute->csr_direct_route_enable */
|
359 |
|
|
sc_signal<sc_bv<32> > csr_direct_route_enable;
|
360 |
|
|
/** Signal from register DirectRoute->csr_clumping_configuration */
|
361 |
|
|
sc_signal<sc_bv<32> > csr_clumping_configuration;
|
362 |
|
|
/** Signals table containing all csr_direct_route_oppposite_dir from Direct Route spaces implemented */
|
363 |
|
|
sc_signal<bool> csr_direct_route_oppposite_dir[DirectRoute_NumberDirectRouteSpaces];
|
364 |
|
|
/** Signals table containing all Base Addresses from Direct Route spaces implemented
|
365 |
|
|
These are the bits 39:8*/
|
366 |
|
|
sc_signal<sc_bv<32> > csr_direct_route_base[DirectRoute_NumberDirectRouteSpaces];
|
367 |
|
|
/** Signals table containing all Limit Addresses from Direct Route spaces implemented
|
368 |
|
|
These are the bits 39:8*/
|
369 |
|
|
sc_signal<sc_bv<32> > csr_direct_route_limit[DirectRoute_NumberDirectRouteSpaces];
|
370 |
|
|
|
371 |
|
|
/** If the link has finished it's initialization (is connected)*/
|
372 |
|
|
sc_signal<bool> csr_initcomplete0;
|
373 |
|
|
/** If the link has finished it's initialization (is connected)*/
|
374 |
|
|
sc_signal<bool> csr_initcomplete1;
|
375 |
|
|
|
376 |
|
|
|
377 |
|
|
sc_signal<sc_uint<6> > csr_read_addr_usr;
|
378 |
|
|
sc_signal<sc_bv<32> > usr_read_data_csr;
|
379 |
|
|
sc_signal<bool > csr_write_usr;
|
380 |
|
|
sc_signal<sc_uint<6> > csr_write_addr_usr;
|
381 |
|
|
sc_signal<sc_bv<32> > csr_write_data_usr;
|
382 |
|
|
sc_signal<sc_bv<4> > csr_write_mask_usr;
|
383 |
|
|
|
384 |
|
|
////////////////////////////////////////////////////////////////
|
385 |
|
|
////////////////////////////////////////////////////////////////
|
386 |
|
|
// CSR DUT connections
|
387 |
|
|
////////////////////////////////////////////////////////////////
|
388 |
|
|
////////////////////////////////////////////////////////////////
|
389 |
|
|
|
390 |
|
|
//Signals used to link the design to the testbench
|
391 |
|
|
dut->clk(clk);
|
392 |
|
|
|
393 |
|
|
dut->resetx(resetx);
|
394 |
|
|
dut->pwrok(pwrok);
|
395 |
|
|
dut->ldtstopx(ldtstopx);
|
396 |
|
|
dut->csr_sync(csr_sync);
|
397 |
|
|
dut->csr_request_databuffer0_access_ui(csr_request_databuffer0_access_ui);
|
398 |
|
|
dut->csr_request_databuffer1_access_ui(csr_request_databuffer1_access_ui);
|
399 |
|
|
dut->ui_databuffer_access_granted_csr(ui_databuffer_access_granted_csr);
|
400 |
|
|
|
401 |
|
|
dut->ro0_available_csr(ro0_available_csr);
|
402 |
|
|
dut->ro0_packet_csr(ro0_packet_csr);
|
403 |
|
|
dut->csr_ack_ro0(csr_ack_ro0);
|
404 |
|
|
|
405 |
|
|
dut->ro1_available_csr(ro1_available_csr);
|
406 |
|
|
dut->ro1_packet_csr(ro1_packet_csr);
|
407 |
|
|
dut->csr_ack_ro1(csr_ack_ro1);
|
408 |
|
|
|
409 |
|
|
dut->csr_read_db0(csr_read_db0);
|
410 |
|
|
dut->csr_read_db1(csr_read_db1);
|
411 |
|
|
|
412 |
|
|
dut->csr_address_db0(csr_address_db0);
|
413 |
|
|
dut->csr_address_db1(csr_address_db1);
|
414 |
|
|
|
415 |
|
|
dut->csr_vctype_db0(csr_vctype_db0);
|
416 |
|
|
dut->csr_vctype_db1(csr_vctype_db1);
|
417 |
|
|
|
418 |
|
|
dut->db0_data_csr(db0_data_csr);
|
419 |
|
|
dut->db1_data_csr(db1_data_csr);
|
420 |
|
|
dut->csr_erase_db0(csr_erase_db0);
|
421 |
|
|
dut->csr_erase_db1(csr_erase_db1);
|
422 |
|
|
dut->csr_available_fc0(csr_available_fc0);
|
423 |
|
|
dut->csr_dword_fc0(csr_dword_fc0);
|
424 |
|
|
dut->fc0_ack_csr(fc0_ack_csr);
|
425 |
|
|
|
426 |
|
|
|
427 |
|
|
dut->csr_available_fc1(csr_available_fc1);
|
428 |
|
|
dut->csr_dword_fc1(csr_dword_fc1);
|
429 |
|
|
dut->fc1_ack_csr(fc1_ack_csr);
|
430 |
|
|
|
431 |
|
|
dut->ui_sendingPostedDataError_csr(ui_sendingPostedDataError_csr);
|
432 |
|
|
dut->ui_sendingTargetAbort_csr(ui_sendingTargetAbort_csr);
|
433 |
|
|
dut->ui_receivedResponseDataError_csr(ui_receivedResponseDataError_csr);
|
434 |
|
|
dut->ui_receivedPostedDataError_csr(ui_receivedPostedDataError_csr);
|
435 |
|
|
dut->ui_receivedTargetAbort_csr(ui_receivedTargetAbort_csr);
|
436 |
|
|
dut->ui_receivedMasterAbort_csr(ui_receivedMasterAbort_csr);
|
437 |
|
|
|
438 |
|
|
dut->usr_receivedResponseError_csr(usr_receivedResponseError_csr);
|
439 |
|
|
|
440 |
|
|
dut->db0_overflow_csr(db0_overflow_csr);
|
441 |
|
|
dut->ro0_overflow_csr(ro0_overflow_csr);
|
442 |
|
|
dut->db1_overflow_csr(db1_overflow_csr);
|
443 |
|
|
dut->ro1_overflow_csr(ro1_overflow_csr);
|
444 |
|
|
dut->eh0_ack_ro0(eh0_ack_ro0);
|
445 |
|
|
dut->eh1_ack_ro1(eh1_ack_ro1);
|
446 |
|
|
|
447 |
|
|
dut->lk0_initialization_complete_csr(lk0_initialization_complete_csr);
|
448 |
|
|
#ifdef RETRY_MODE_ENABLED
|
449 |
|
|
dut->lk0_initiate_retry_disconnect(lk0_initiate_retry_disconnect);
|
450 |
|
|
#endif
|
451 |
|
|
dut->lk0_crc_error_csr(lk0_crc_error_csr);
|
452 |
|
|
dut->lk0_protocol_error_csr(lk0_protocol_error_csr);
|
453 |
|
|
dut->lk1_initialization_complete_csr(lk1_initialization_complete_csr);
|
454 |
|
|
#ifdef RETRY_MODE_ENABLED
|
455 |
|
|
dut->lk1_initiate_retry_disconnect(lk1_initiate_retry_disconnect);
|
456 |
|
|
#endif
|
457 |
|
|
dut->lk1_crc_error_csr(lk1_crc_error_csr);
|
458 |
|
|
dut->lk1_protocol_error_csr(lk1_protocol_error_csr);
|
459 |
|
|
dut->cd0_protocol_error_csr(cd0_protocol_error_csr);
|
460 |
|
|
dut->cd0_sync_detected_csr(cd0_sync_detected_csr);
|
461 |
|
|
dut->cd1_protocol_error_csr(cd1_protocol_error_csr);
|
462 |
|
|
#ifdef RETRY_MODE_ENABLED
|
463 |
|
|
dut->cd0_initiate_retry_disconnect(cd0_initiate_retry_disconnect);
|
464 |
|
|
dut->cd0_received_stomped_csr(cd0_received_stomped_csr);
|
465 |
|
|
dut->cd1_initiate_retry_disconnect(cd1_initiate_retry_disconnect);
|
466 |
|
|
dut->cd1_received_stomped_csr(cd1_received_stomped_csr);
|
467 |
|
|
#endif
|
468 |
|
|
|
469 |
|
|
dut->cd1_sync_detected_csr(cd1_sync_detected_csr);
|
470 |
|
|
dut->lk0_update_link_failure_property_csr(lk0_update_link_failure_property_csr);
|
471 |
|
|
dut->lk0_update_link_width_csr(lk0_update_link_width_csr);
|
472 |
|
|
dut->lk0_sampled_link_width_csr(lk0_sampled_link_width_csr);
|
473 |
|
|
dut->lk0_link_failure_csr(lk0_link_failure_csr);
|
474 |
|
|
|
475 |
|
|
dut->fc0_clear_single_error_csr(fc0_clear_single_error_csr);
|
476 |
|
|
dut->fc0_clear_single_stomp_csr(fc0_clear_single_stomp_csr);
|
477 |
|
|
|
478 |
|
|
|
479 |
|
|
dut->lk1_update_link_failure_property_csr(lk1_update_link_failure_property_csr);
|
480 |
|
|
dut->lk1_update_link_width_csr(lk1_update_link_width_csr);
|
481 |
|
|
dut->lk1_sampled_link_width_csr(lk1_sampled_link_width_csr);
|
482 |
|
|
dut->lk1_link_failure_csr(lk1_link_failure_csr);
|
483 |
|
|
dut->fc1_clear_single_error_csr(fc1_clear_single_error_csr);
|
484 |
|
|
dut->fc1_clear_single_stomp_csr(fc1_clear_single_stomp_csr);
|
485 |
|
|
dut->csr_io_space_enable(csr_io_space_enable);
|
486 |
|
|
dut->csr_memory_space_enable(csr_memory_space_enable);
|
487 |
|
|
dut->csr_bus_master_enable(csr_bus_master_enable);
|
488 |
|
|
dut->csr_master_host(csr_master_host);
|
489 |
|
|
for(int n = 0; n < NbRegsBars; n++)
|
490 |
|
|
dut->csr_bar[n](csr_bar[n]);
|
491 |
|
|
dut->csr_unit_id(csr_unit_id);
|
492 |
|
|
dut->csr_default_dir(csr_default_dir);
|
493 |
|
|
dut->csr_drop_uninit_link(csr_drop_uninit_link);
|
494 |
|
|
dut->csr_crc_force_error_lk0(csr_crc_force_error_lk0);
|
495 |
|
|
dut->csr_end_of_chain0(csr_end_of_chain0);
|
496 |
|
|
dut->csr_transmitter_off_lk0(csr_transmitter_off_lk0);
|
497 |
|
|
dut->csr_ldtstop_tristate_enable_lk0(csr_ldtstop_tristate_enable_lk0);
|
498 |
|
|
dut->csr_extented_ctl_lk0(csr_extented_ctl_lk0);
|
499 |
|
|
dut->csr_rx_link_width_lk0(csr_rx_link_width_lk0);
|
500 |
|
|
dut->csr_tx_link_width_lk0(csr_tx_link_width_lk0);
|
501 |
6 |
acastong |
dut->csr_link_frequency0(csr_link_frequency0);
|
502 |
2 |
acastong |
dut->csr_crc_force_error_lk1(csr_crc_force_error_lk1);
|
503 |
|
|
dut->csr_end_of_chain1(csr_end_of_chain1);
|
504 |
|
|
dut->csr_transmitter_off_lk1(csr_transmitter_off_lk1);
|
505 |
|
|
dut->csr_ldtstop_tristate_enable_lk1(csr_ldtstop_tristate_enable_lk1);
|
506 |
|
|
dut->csr_extented_ctl_lk1(csr_extented_ctl_lk1);
|
507 |
|
|
dut->csr_rx_link_width_lk1(csr_rx_link_width_lk1);
|
508 |
|
|
dut->csr_tx_link_width_lk1(csr_tx_link_width_lk1);
|
509 |
6 |
acastong |
dut->csr_link_frequency1(csr_link_frequency1);
|
510 |
2 |
acastong |
dut->csr_extended_ctl_timeout_lk0(csr_extended_ctl_timeout_lk0);
|
511 |
|
|
#ifdef ENABLE_REORDERING
|
512 |
|
|
dut->csr_unitid_reorder_disable(csr_unitid_reorder_disable);
|
513 |
|
|
#endif
|
514 |
|
|
dut->csr_extended_ctl_timeout_lk1(csr_extended_ctl_timeout_lk1);
|
515 |
|
|
#ifdef RETRY_MODE_ENABLED
|
516 |
|
|
dut->csr_retry0(csr_retry0);
|
517 |
|
|
dut->csr_force_single_error_fc0(csr_force_single_error_fc0);
|
518 |
|
|
dut->csr_force_single_stomp_fc0(csr_force_single_stomp_fc0);
|
519 |
|
|
dut->csr_retry1(csr_retry1);
|
520 |
|
|
dut->csr_force_single_error_fc1(csr_force_single_error_fc1);
|
521 |
|
|
dut->csr_force_single_stomp_fc1(csr_force_single_stomp_fc1);
|
522 |
|
|
#endif
|
523 |
|
|
dut->csr_direct_route_enable(csr_direct_route_enable);
|
524 |
|
|
dut->csr_clumping_configuration(csr_clumping_configuration);
|
525 |
|
|
for(int n = 0; n < DirectRoute_NumberDirectRouteSpaces; n++){
|
526 |
|
|
dut->csr_direct_route_oppposite_dir[n](csr_direct_route_oppposite_dir[n]);
|
527 |
|
|
dut->csr_direct_route_base[n](csr_direct_route_base[n]);
|
528 |
|
|
dut->csr_direct_route_limit[n](csr_direct_route_limit[n]);
|
529 |
|
|
}
|
530 |
|
|
dut->csr_initcomplete0(csr_initcomplete0);
|
531 |
|
|
dut->csr_initcomplete1(csr_initcomplete1);
|
532 |
|
|
|
533 |
|
|
dut->csr_read_addr_usr(csr_read_addr_usr);
|
534 |
|
|
dut->usr_read_data_csr(usr_read_data_csr);
|
535 |
|
|
dut->csr_write_usr(csr_write_usr);
|
536 |
|
|
dut->csr_write_addr_usr(csr_write_addr_usr);
|
537 |
|
|
dut->csr_write_data_usr(csr_write_data_usr);
|
538 |
|
|
dut->csr_write_mask_usr(csr_write_mask_usr);
|
539 |
|
|
|
540 |
|
|
////////////////////////////////////////////////////////////////
|
541 |
|
|
////////////////////////////////////////////////////////////////
|
542 |
|
|
// CSR TB connections
|
543 |
|
|
////////////////////////////////////////////////////////////////
|
544 |
|
|
////////////////////////////////////////////////////////////////
|
545 |
|
|
|
546 |
|
|
tb->clk(clk);
|
547 |
|
|
tb->resetx(resetx);
|
548 |
|
|
tb->pwrok(pwrok);
|
549 |
|
|
tb->ldtstopx(ldtstopx);
|
550 |
|
|
tb->csr_sync(csr_sync);
|
551 |
|
|
tb->csr_request_databuffer0_access_ui(csr_request_databuffer0_access_ui);
|
552 |
|
|
tb->csr_request_databuffer1_access_ui(csr_request_databuffer1_access_ui);
|
553 |
|
|
tb->ui_databuffer_access_granted_csr(ui_databuffer_access_granted_csr);
|
554 |
|
|
|
555 |
|
|
tb->ro0_available_csr(ro0_available_csr);
|
556 |
|
|
tb->ro0_packet_csr(ro0_packet_csr);
|
557 |
|
|
tb->csr_ack_ro0(csr_ack_ro0);
|
558 |
|
|
|
559 |
|
|
tb->ro1_available_csr(ro1_available_csr);
|
560 |
|
|
tb->ro1_packet_csr(ro1_packet_csr);
|
561 |
|
|
tb->csr_ack_ro1(csr_ack_ro1);
|
562 |
|
|
|
563 |
|
|
tb->csr_read_db0(csr_read_db0);
|
564 |
|
|
tb->csr_read_db1(csr_read_db1);
|
565 |
|
|
|
566 |
|
|
tb->csr_address_db0(csr_address_db0);
|
567 |
|
|
tb->csr_address_db1(csr_address_db1);
|
568 |
|
|
|
569 |
|
|
tb->csr_vctype_db0(csr_vctype_db0);
|
570 |
|
|
tb->csr_vctype_db1(csr_vctype_db1);
|
571 |
|
|
|
572 |
|
|
tb->db0_data_csr(db0_data_csr);
|
573 |
|
|
tb->db1_data_csr(db1_data_csr);
|
574 |
|
|
tb->csr_erase_db0(csr_erase_db0);
|
575 |
|
|
tb->csr_erase_db1(csr_erase_db1);
|
576 |
|
|
tb->csr_available_fc0(csr_available_fc0);
|
577 |
|
|
tb->csr_dword_fc0(csr_dword_fc0);
|
578 |
|
|
tb->fc0_ack_csr(fc0_ack_csr);
|
579 |
|
|
|
580 |
|
|
|
581 |
|
|
tb->csr_available_fc1(csr_available_fc1);
|
582 |
|
|
tb->csr_dword_fc1(csr_dword_fc1);
|
583 |
|
|
tb->fc1_ack_csr(fc1_ack_csr);
|
584 |
|
|
|
585 |
|
|
////////////////////////////////////////////////////////////////
|
586 |
|
|
////////////////////////////////////////////////////////////////
|
587 |
|
|
// Trace signals
|
588 |
|
|
////////////////////////////////////////////////////////////////
|
589 |
|
|
////////////////////////////////////////////////////////////////
|
590 |
|
|
|
591 |
|
|
sc_trace_file *tf = sc_create_vcd_trace_file("sim_csr_l2");
|
592 |
|
|
|
593 |
|
|
sc_trace(tf,clk,"clk");
|
594 |
|
|
sc_trace(tf,resetx,"resetx");
|
595 |
|
|
sc_trace(tf,pwrok,"pwrok");
|
596 |
|
|
sc_trace(tf,ldtstopx,"ldtstopx");
|
597 |
|
|
sc_trace(tf,csr_sync,"csr_sync");
|
598 |
|
|
sc_trace(tf,csr_request_databuffer0_access_ui,"csr_request_databuffer0_access_ui");
|
599 |
|
|
sc_trace(tf,csr_request_databuffer1_access_ui,"csr_request_databuffer1_access_ui");
|
600 |
|
|
sc_trace(tf,ui_databuffer_access_granted_csr,"ui_databuffer_access_granted_csr");
|
601 |
|
|
|
602 |
|
|
sc_trace(tf,ro0_available_csr,"ro0_available_csr");
|
603 |
|
|
sc_trace(tf,ro0_packet_csr,"ro0_packet_csr");
|
604 |
|
|
sc_trace(tf,csr_ack_ro0,"csr_ack_ro0");
|
605 |
|
|
|
606 |
|
|
sc_trace(tf,ro1_available_csr,"ro1_available_csr");
|
607 |
|
|
sc_trace(tf,ro1_packet_csr,"ro1_packet_csr");
|
608 |
|
|
sc_trace(tf,csr_ack_ro1,"csr_ack_ro1");
|
609 |
|
|
|
610 |
|
|
sc_trace(tf,csr_read_db0,"csr_read_db0");
|
611 |
|
|
sc_trace(tf,csr_read_db1,"csr_read_db1");
|
612 |
|
|
|
613 |
|
|
sc_trace(tf,csr_address_db0,"csr_address_db0");
|
614 |
|
|
sc_trace(tf,csr_address_db1,"csr_address_db1");
|
615 |
|
|
|
616 |
|
|
sc_trace(tf,csr_vctype_db0,"csr_vctype_db0");
|
617 |
|
|
sc_trace(tf,csr_vctype_db1,"csr_vctype_db1");
|
618 |
|
|
|
619 |
|
|
sc_trace(tf,db0_data_csr,"db0_data_csr");
|
620 |
|
|
sc_trace(tf,db1_data_csr,"db1_data_csr");
|
621 |
|
|
sc_trace(tf,csr_erase_db0,"csr_erase_db0");
|
622 |
|
|
sc_trace(tf,csr_erase_db1,"csr_erase_db1");
|
623 |
|
|
sc_trace(tf,csr_available_fc0,"csr_available_fc0");
|
624 |
|
|
sc_trace(tf,csr_dword_fc0,"csr_dword_fc0");
|
625 |
|
|
sc_trace(tf,fc0_ack_csr,"fc0_ack_csr");
|
626 |
|
|
|
627 |
|
|
|
628 |
|
|
sc_trace(tf,csr_available_fc1,"csr_available_fc1");
|
629 |
|
|
sc_trace(tf,csr_dword_fc1,"csr_dword_fc1");
|
630 |
|
|
|
631 |
|
|
sc_trace(tf,dut->config_registers[19],"bar0(31..24)");
|
632 |
|
|
sc_trace(tf,dut->config_registers[18],"bar0(23..16)");
|
633 |
|
|
sc_trace(tf,dut->config_registers[17],"bar0(15..8)");
|
634 |
|
|
sc_trace(tf,dut->config_registers[16],"bar0(7..0)");
|
635 |
|
|
|
636 |
|
|
sc_trace(tf,dut->config_registers[23],"bar1(31..24)");
|
637 |
|
|
sc_trace(tf,dut->config_registers[22],"bar1(23..16)");
|
638 |
|
|
sc_trace(tf,dut->config_registers[21],"bar1(15..8)");
|
639 |
|
|
sc_trace(tf,dut->config_registers[20],"bar1(7..0)");
|
640 |
|
|
|
641 |
|
|
sc_trace(tf,dut->config_registers[27],"bar2(31..24)");
|
642 |
|
|
sc_trace(tf,dut->config_registers[26],"bar2(23..16)");
|
643 |
|
|
sc_trace(tf,dut->config_registers[25],"bar2(15..8)");
|
644 |
|
|
sc_trace(tf,dut->config_registers[24],"bar2(7..0)");
|
645 |
|
|
|
646 |
|
|
sc_trace(tf,dut->config_registers[31],"bar3(31..24)");
|
647 |
|
|
sc_trace(tf,dut->config_registers[30],"bar3(23..16)");
|
648 |
|
|
sc_trace(tf,dut->config_registers[29],"bar3(15..8)");
|
649 |
|
|
sc_trace(tf,dut->config_registers[28],"bar3(7..0)");
|
650 |
|
|
|
651 |
|
|
//------------------------------------------
|
652 |
|
|
// Start simulation
|
653 |
|
|
//------------------------------------------
|
654 |
|
|
cout << "Start of simulation" << endl;
|
655 |
|
|
sc_start(60);
|
656 |
|
|
|
657 |
|
|
|
658 |
|
|
sc_close_vcd_trace_file(tf);
|
659 |
|
|
cout << "End of simulation" << endl;
|
660 |
|
|
|
661 |
|
|
delete dut;
|
662 |
|
|
delete tb;
|
663 |
|
|
return 0;
|
664 |
|
|
}
|
665 |
|
|
|