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acastong |
//decoder_l2_tb.h
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/* ***** BEGIN LICENSE BLOCK *****
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* Version: MPL 1.1
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*
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* The contents of this file are subject to the Mozilla Public License Version
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* 1.1 (the "License"); you may not use this file except in compliance with
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* the License. You may obtain a copy of the License at
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* http://www.mozilla.org/MPL/
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*
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* Software distributed under the License is distributed on an "AS IS" basis,
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* WITHOUT WARRANTY OF ANY KIND, either express or implied. See the License
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* for the specific language governing rights and limitations under the
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* License.
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*
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* The Original Code is HyperTransport Tunnel IP Core.
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*
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* The Initial Developer of the Original Code is
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* Ecole Polytechnique de Montreal.
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* Portions created by the Initial Developer are Copyright (C) 2005
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* the Initial Developer. All Rights Reserved.
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*
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* Contributor(s):
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* Ami Castonguay <acastong@grm.polymtl.ca>
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*
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* Alternatively, the contents of this file may be used under the terms
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* of the Polytechnique HyperTransport Tunnel IP Core Source Code License
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* (the "PHTICSCL License", see the file PHTICSCL.txt), in which case the
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* provisions of PHTICSCL License are applicable instead of those
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* above. If you wish to allow use of your version of this file only
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* under the terms of the PHTICSCL License and not to allow others to use
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* your version of this file under the MPL, indicate your decision by
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* deleting the provisions above and replace them with the notice and
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* other provisions required by the PHTICSCL License. If you do not delete
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* the provisions above, a recipient may use your version of this file
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* under either the MPL or the PHTICSCL License."
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*
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* ***** END LICENSE BLOCK ***** */
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#ifndef DECODER_L2_TB_H
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#define DECODER_L2_TB_H
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#include "../../rtl/systemc/core_synth/synth_datatypes.h"
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#include <deque>
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///Testbench for the decoder_l2 module
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class decoder_l2_tb : public sc_module{
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public:
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///Contains all data important to check validity of what is sent to databuffer
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/** An instance of the struct is added to the queue when a data packet is
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sent to the databuffer and is checked when the packet is sent to the
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databuffer. The variable address_requested is false at the beggining and
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is set to be true when the packet address is requested (it is modified
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in the queue).
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*/
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struct DataBufferEntry{
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int size;///<Size in dwords of the data packet (minus 1)
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int data[16];///<Content of the data packet
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bool badcrc;///<If a bad CRC accompanies the data packet
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///<Currently not used but potentially there to check if the
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///<data packet is dropped in case of bad per packet CRC
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bool address_requested;///<Set to true when decoder asks for address from Databuffer
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VirtualChannel vc;///<The virtual channel this data packet belongs to
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};
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///A packet to be sent to the reordering module
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struct ReorderingEntry{
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syn_ControlPacketComplete pkt;
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bool has_data;
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};
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///Information contained in a nop
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struct NopEntry{
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sc_uint<8> cd_nop_ack_value_fc;
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sc_bv<12> cd_nopinfo_fc;
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};
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///clk signal
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sc_in<bool> clk;
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///Warm Reset to initialize module
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sc_out < bool > resetx;
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//*******************************
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// Signals for Control Buffer
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//*******************************
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/**Packet to be transmitted to control buffer module*/
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sc_in< syn_ControlPacketComplete > cd_packet_ro;
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/**Enables control buffer module to read cd_packet_ro port*/
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sc_in< bool > cd_available_ro;
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/**If we're currently receiving data. This is used by the ro to know
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if we have finished receiving the data of a packet, so it can know if
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it can send it.*/
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sc_in<bool> cd_data_pending_ro;
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/**Where we are storing data. This is used by the ro to know
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if we have finished receiving the data of a packet, so it can know if
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it can send it.*/
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sc_in<sc_uint<BUFFERS_ADDRESS_WIDTH> > cd_data_pending_addr_ro;
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//*******************************
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// Signals for Data Buffer
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//*******************************
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///ddress of data in data buffer module
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sc_out< sc_uint<BUFFERS_ADDRESS_WIDTH> > db_address_cd;
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///Get an address form data buffer module
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sc_in< bool > cd_getaddr_db;
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///Size of data packet to be written
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sc_in< sc_uint<4> > cd_datalen_db;
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///Virtual channel where data will be written
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sc_in< VirtualChannel > cd_vctype_db;
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///Data to be written in data buffer module
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sc_in< sc_bv<32> > cd_data_db;
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///Enables data buffer to read cd_data_db port
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sc_in< bool > cd_write_db;
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#ifdef RETRY_MODE_ENABLED
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///Erase signal for packet stomping
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sc_in< bool > cd_drop_db;
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#endif
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//*************************************
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// Signals to CSR
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//*************************************
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///A protocol error has been detected
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sc_in< bool > cd_protocol_error_csr;
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///A sync packet has been received
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sc_in< bool > cd_sync_detected_csr;
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#ifdef RETRY_MODE_ENABLED
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///If retry mode is active
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sc_out< bool > csr_retry;
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#endif
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//*******************************
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// Signals from link
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//*******************************
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///Bit vector input from the FIFO
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sc_out< sc_bv<32> > lk_dword_cd;
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///Control bit
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sc_out< bool > lk_hctl_cd;
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///Control bit
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sc_out< bool > lk_lctl_cd;
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///FIFO is ready to be read from
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sc_out< bool > lk_available_cd;
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#ifdef RETRY_MODE_ENABLED
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///If a retry sequence is initiated by link
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sc_out< bool > lk_initiate_retry_disconnect;
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#endif
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//*******************************
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// Signals for Forwarding module
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//*******************************
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#ifdef RETRY_MODE_ENABLED
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///History count
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sc_in< sc_uint<8> > cd_rx_next_pkt_to_ack_fc;
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///rxPacketToAck (retry mode)
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sc_in< sc_uint<8> > cd_nop_ack_value_fc;
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#endif
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///Info registered from NOP word
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sc_in< sc_bv<12> > cd_nopinfo_fc;
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///Signal that new nop info are available
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sc_in< bool > cd_nop_received_fc;
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#ifdef RETRY_MODE_ENABLED
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///Start the sequence for a retry disconnect
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sc_in< bool > cd_initiate_retry_disconnect;
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///A stomped packet has been received
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sc_in<bool> cd_received_stomped_csr;
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///Let the reordering know we received a non flow control stomped packet
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/** When this situation happens, packet available bit does not become
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asserted but the correct packet is sent, which can be used to know
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from which VC to free a flow control credit.
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*/
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sc_in<bool> cd_received_non_flow_stomped_ro;
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#endif
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///The link can start a sequence for a ldtstop disconnect
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sc_in< bool > cd_initiate_nonretry_disconnect_lk;
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///SystemC Macro
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SC_HAS_PROCESS(decoder_l2_tb);
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///Queue of data packet that will be sent to databuffer
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std::deque<DataBufferEntry> databuffer_queue;
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///Qeue of command packet that will be sent to reordering
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std::deque<ReorderingEntry> reordering_queue;
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///Queue of information that will be sent out when nops are received
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std::deque<NopEntry> nop_queue;
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///List of ack values associated with packet sent to databuffer
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std::deque<sc_uint<8> > ack_value;
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///Stores the latest data address given out by the databuffer
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sc_uint<BUFFERS_ADDRESS_WIDTH> last_databuffer_address;
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///If an error was detected by the testbench
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bool error;
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/** Stores with various degrees of delay when the decoder request to
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get an address from the databuffer. Used to calculate when the
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decoder should start to say that there is data pending.
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*/
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//@{
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sc_signal<bool> delayed_start_writing_data;
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sc_signal<bool> delayed_start_writing_data2;
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sc_signal<bool> delayed_start_writing_data3;
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//@}
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///Asserted while the decoder is writing data to databuffer
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sc_signal<bool> writing_data;
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/**
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Expected values of different control signals from the decoder
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The value is the maximum number of cycles before it should be
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asserted. Set to zero when it is asserted
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*/
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//@{
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int expect_cd_initiate_retry_disconnect;
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int expect_cd_received_stomped_csr;
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int expect_cd_initiate_nonretry_disconnect_lk;
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//@}
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///Calculated CRC as testbench sends a packet to decoder that has no data
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unsigned crc1;
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///Calculated CRC as testbench sends a packet to decoder with data
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unsigned crc2;
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///Module constructor
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decoder_l2_tb(sc_module_name name);
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///Module desctructor
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virtual ~decoder_l2_tb(){}
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///Main control thread of the testbench
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void stimulate_input();
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///Validates that nop_received is correct, along with freed buffers and ack values
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void nop_info_validation();
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///Validates that what is sent to the databuffer is correct
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void databuffer_validation();
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///Validates that disconnect (retry or not) and stomped signals are good
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void disconnect_retry_validation();
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///Validates that whas is sent to the reordering is correct
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void reordering_validation();
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///Display the message and set that an error was received
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void displayError(const char * error_message);
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///Sends a dword to the databuffer (contains wait)
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void send_dword(sc_bv<32> dword,bool lctl, bool hctl);
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///Send random nop to decoder
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void send_nop();
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///Send target done packet to decoder
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void send_tgtdone();
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///Send read packet to decoder
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void send_read();
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///Send write packet to decoder
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void send_write();
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///Takes care of sending a random write header packet
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/**@param datalength_m1 The number minus one of dwords
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of data that will follow the header
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*/
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void send_write_header(int datalength_m1);
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///Creates a databuffer entry: random dword to send for databuffer
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/**@param datalength_m1 The number minus one of dwords of data
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@param vc The virtual channel the data belongs to
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@return The generated databuffer entry
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*/
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DataBufferEntry generate_data_packet(int datalength_m1,
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VirtualChannel vc);
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///Sends a data packet
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/**@description Allows to sent part of a datapacket at a time with
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the offset and last parameters
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@param entry The datapacket to send
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@param offset From where to start the datapacket
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@param last What is the last position to send
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*/
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void send_data_packet(DataBufferEntry &entry,
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int offset,int last);
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///Send a packet with a 64 bit extension
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void send_ext();
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///Send an extended flow control packet
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void send_ext_fc();
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///Send an extended flow control packet (64 bit version)
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void send_ext_fc64();
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///Send a packet with data and a targetdone inserted inside it
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void send_tgtdone_in_data();
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///Send a packet with data and a flow control packet inserted inside it
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void send_fc_in_data();
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///Send a packet with data and a 64 bit flow control packet inserted inside it
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void send_fc64_in_data();
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///Send a packet with data and a nop packet inserted inside it
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void send_nop_in_data();
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///Send a disconnect nop
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void send_discon_nop();
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///Get a random 32-bit vector
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void getRandomVector(sc_bv<32> &vector);
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///Get a random 64-bit vector
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void getRandomVector(sc_bv<64> &vector);
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///Add a reordering entry to the queue for a dword packet
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void addReorderingEntry(sc_bv<32> &vector,bool hasData);
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///Add a reordering entry to the queue for a qword packet
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void addReorderingEntry(sc_bv<64> &vector,bool hasData);
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///Update the CRC1 value
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/**
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@param dword The dword to use for per packet CRC calculation
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@param lctl The lctl to use for per packet CRC calculation
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@param hctl The hctl to use for per packet CRC calculation
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*/
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void calculate_crc1(sc_bv<32> dword,bool lctl, bool hctl);
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///Update the CRC2 value
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/**
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@param dword The dword to use for per packet CRC calculation
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@param lctl The lctl to use for per packet CRC calculation
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@param hctl The hctl to use for per packet CRC calculation
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*/
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void calculate_crc2(sc_bv<32> dword,bool lctl, bool hctl);
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///Update per packet CRC with the data
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/**
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@param crc The crc value to update
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@param data The combined dword and CTL vector to use for calculations
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*/
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void calculate_crc(unsigned &crc,sc_bv<34> &data);
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};
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#endif
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