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acastong |
//main.cpp for vc_ht_tunnel_l1 testbench
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/* ***** BEGIN LICENSE BLOCK *****
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* Version: MPL 1.1
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*
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* The contents of this file are subject to the Mozilla Public License Version
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* 1.1 (the "License"); you may not use this file except in compliance with
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* the License. You may obtain a copy of the License at
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* http://www.mozilla.org/MPL/
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*
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* Software distributed under the License is distributed on an "AS IS" basis,
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* WITHOUT WARRANTY OF ANY KIND, either express or implied. See the License
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* for the specific language governing rights and limitations under the
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* License.
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*
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* The Original Code is HyperTransport Tunnel IP Core.
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*
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* The Initial Developer of the Original Code is
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* Ecole Polytechnique de Montreal.
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* Portions created by the Initial Developer are Copyright (C) 2005
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* the Initial Developer. All Rights Reserved.
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*
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* Contributor(s):
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* Ami Castonguay <acastong@grm.polymtl.ca>
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*
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* Alternatively, the contents of this file may be used under the terms
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* of the Polytechnique HyperTransport Tunnel IP Core Source Code License
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* (the "PHTICSCL License", see the file PHTICSCL.txt), in which case the
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* provisions of PHTICSCL License are applicable instead of those
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* above. If you wish to allow use of your version of this file only
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* under the terms of the PHTICSCL License and not to allow others to use
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* your version of this file under the MPL, indicate your decision by
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* deleting the provisions above and replace them with the notice and
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* other provisions required by the PHTICSCL License. If you do not delete
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* the provisions above, a recipient may use your version of this file
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* under either the MPL or the PHTICSCL License."
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*
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* ***** END LICENSE BLOCK ***** */
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#ifdef MTI_SYSTEMC
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//For ModelSim simulation, top simulation must be contained within
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//a module instanciated in a .h
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#include "main.h"
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//Directive to mark the top level of the simulated design
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SC_MODULE_EXPORT(top);
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//MTI_SYSTEMC does not work on all version of ModelSim, this is a fallback
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#elif MTI2_SYSTEMC
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//For ModelSim simulation, top simulation must be contained within
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//a module instanciated in a .h
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#include "main.h"
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//Directive to mark the top level of the simulated design
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SC_MODULE_EXPORT(top);
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//If not in ModelSim simulation, proceed with the standard procedure
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#else
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#include "../../rtl/systemc/core_synth/synth_datatypes.h"
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#include <iostream>
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#include <string>
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#include <sstream>
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#include <iomanip>
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#include <ctime>
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#include "../../rtl/systemc/vc_ht_tunnel_l1/vc_ht_tunnel_l1.h"
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#include "../../rtl/systemc/flow_control_l2/user_fifo_l3.h"
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#include "../../rtl/systemc/flow_control_l2/history_buffer_l3.h"
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#include "vc_ht_tunnel_l1_tb.h"
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using namespace std;
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// Main fonction
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int sc_main( int argc, char* argv[] )
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{
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sc_clock clk("CLOCK",1,SC_NS);
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//------------------------------------------
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// Instanciation de FLOW CONTROL
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//------------------------------------------
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vc_ht_tunnel_l1* the_ht_tunnel = new vc_ht_tunnel_l1("the_ht_tunnel");
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vc_ht_tunnel_l1_tb * tb = new vc_ht_tunnel_l1_tb("vc_ht_tunnel_l1_tb");
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// ***************************************************
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// Signals
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// ***************************************************
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/// The Clock, LDTSTOP and reset signals
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sc_signal<bool> resetx;
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sc_signal<bool> pwrok;
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sc_signal<bool> ldtstopx;
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//Link0 signals
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//sc_signal<bool > receive_clk0;
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sc_signal<bool> phy0_available_lk0;
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sc_signal<sc_bv<CAD_IN_DEPTH> > phy0_ctl_lk0;
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sc_signal<sc_bv<CAD_IN_DEPTH> > phy0_cad_lk0[CAD_IN_WIDTH];
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//sc_signal< bool > transmit_clk0;
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sc_signal<sc_bv<CAD_OUT_DEPTH> > lk0_ctl_phy0;
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sc_signal<sc_bv<CAD_OUT_DEPTH> > lk0_cad_phy0[CAD_OUT_WIDTH];
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sc_signal<bool> phy0_consume_lk0;
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sc_signal<bool> lk0_disable_drivers_phy0;
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sc_signal<bool> lk0_disable_receivers_phy0;
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acastong |
sc_signal<sc_bv<4> > link_frequency0_phy;
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acastong |
#ifndef INTERNAL_SHIFTER_ALIGNMENT
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///High speed deserializer should stall shifting bits for lk_deser_stall_cycles_phy cycles
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/** Cannot be asserted with a lk_deser_stall_cycles_phy value of 0*/
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sc_signal<bool > lk0_deser_stall_phy0;
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///Number of bit times to stall deserializing incoming data when lk_deser_stall_phy is asserted
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sc_signal<sc_uint<LOG2_CAD_IN_DEPTH> > lk0_deser_stall_cycles_phy0;
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#endif
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//Link1 signals
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//sc_signal<bool > receive_clk1;
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sc_signal<bool> phy1_available_lk1;
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sc_signal<sc_bv<CAD_IN_DEPTH> > phy1_ctl_lk1;
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sc_signal<sc_bv<CAD_IN_DEPTH> > phy1_cad_lk1[CAD_IN_WIDTH];
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//sc_signal< bool > transmit_clk0;
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sc_signal<sc_bv<CAD_OUT_DEPTH> > lk1_ctl_phy1;
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sc_signal<sc_bv<CAD_OUT_DEPTH> > lk1_cad_phy1[CAD_OUT_WIDTH];
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sc_signal<bool> phy1_consume_lk1;
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sc_signal<bool> lk1_disable_drivers_phy1;
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sc_signal<bool> lk1_disable_receivers_phy1;
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acastong |
sc_signal<sc_bv<4> > link_frequency1_phy;
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2 |
acastong |
#ifndef INTERNAL_SHIFTER_ALIGNMENT
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///High speed deserializer should stall shifting bits for lk_deser_stall_cycles_phy cycles
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/** Cannot be asserted with a lk_deser_stall_cycles_phy value of 0*/
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sc_signal<bool > lk1_deser_stall_phy1;
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///Number of bit times to stall deserializing incoming data when lk_deser_stall_phy is asserted
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sc_signal<sc_uint<LOG2_CAD_IN_DEPTH> > lk1_deser_stall_cycles_phy1;
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#endif
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/////////////////////////////////////////////////////
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// Interface to UserInterface memory - synchronous
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/////////////////////////////////////////////////////
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sc_signal<bool> ui_memory_write0;
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sc_signal<bool> ui_memory_write1;//20
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sc_signal<sc_bv<USER_MEMORY_ADDRESS_WIDTH> > ui_memory_write_address;
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sc_signal<sc_bv<32> > ui_memory_write_data;
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sc_signal<sc_bv<USER_MEMORY_ADDRESS_WIDTH> > ui_memory_read_address0;
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sc_signal<sc_bv<USER_MEMORY_ADDRESS_WIDTH> > ui_memory_read_address1;
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sc_signal<sc_bv<32> > ui_memory_read_data0;
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sc_signal<sc_bv<32> > ui_memory_read_data1;
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#ifdef RETRY_MODE_ENABLED
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//////////////////////////////////////////
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// Memory interface flowcontrol0- synchronous
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/////////////////////////////////////////
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sc_signal<bool> history_memory_write0;
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sc_signal<sc_uint<LOG2_HISTORY_MEMORY_SIZE> > history_memory_write_address0;
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sc_signal<sc_bv<32> > history_memory_write_data0;
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sc_signal<sc_uint<LOG2_HISTORY_MEMORY_SIZE> > history_memory_read_address0;//30
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sc_signal<sc_bv<32> > history_memory_output0;
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//////////////////////////////////////////
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// Memory interface flowcontrol1- synchronous
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/////////////////////////////////////////
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sc_signal<bool> history_memory_write1;
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sc_signal<sc_uint<LOG2_HISTORY_MEMORY_SIZE> > history_memory_write_address1;
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sc_signal<sc_bv<32> > history_memory_write_data1;
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sc_signal<sc_uint<LOG2_HISTORY_MEMORY_SIZE> > history_memory_read_address1;
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sc_signal<sc_bv<32> > history_memory_output1;
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#endif
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////////////////////////////////////
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// Memory interface databuffer0 - synchronous
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////////////////////////////////////
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sc_signal<bool> memory_write0;
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sc_signal<sc_uint<2> > memory_write_address_vc0;
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sc_signal<sc_uint<BUFFERS_ADDRESS_WIDTH> > memory_write_address_buffer0;
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sc_signal<sc_uint<4> > memory_write_address_pos0;//40
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sc_signal<sc_bv<32> > memory_write_data0;
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sc_signal<sc_uint<2> > memory_read_address_vc0[2];
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sc_signal<sc_uint<BUFFERS_ADDRESS_WIDTH> >memory_read_address_buffer0[2];
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sc_signal<sc_uint<4> > memory_read_address_pos0[2];//50
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sc_signal<sc_bv<32> > memory_output0[2];
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//////////////////////////////////////
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// Memory interface databuffer1 - synchronous
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////////////////////////////////////
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sc_signal<bool> memory_write1;
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sc_signal<sc_uint<2> > memory_write_address_vc1;
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sc_signal<sc_uint<BUFFERS_ADDRESS_WIDTH> > memory_write_address_buffer1;
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sc_signal<sc_uint<4> > memory_write_address_pos1;
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sc_signal<sc_bv<32> > memory_write_data1;
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sc_signal<sc_uint<2> > memory_read_address_vc1[2];
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sc_signal<sc_uint<BUFFERS_ADDRESS_WIDTH> >memory_read_address_buffer1[2];
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sc_signal<sc_uint<4> > memory_read_address_pos1[2];
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sc_signal<sc_bv<32> > memory_output1[2];
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///////////////////////////////////////
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// Interface to command memory 0
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///////////////////////////////////////
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sc_signal<sc_bv<CMD_BUFFER_MEM_WIDTH> > ro0_command_packet_wr_data;
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sc_signal<bool > ro0_command_packet_write;
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sc_signal<sc_uint<LOG2_NB_OF_BUFFERS+2> > ro0_command_packet_wr_addr;
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sc_signal<sc_uint<LOG2_NB_OF_BUFFERS+2> > ro0_command_packet_rd_addr[2];
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sc_signal<sc_bv<CMD_BUFFER_MEM_WIDTH> > command_packet_rd_data_ro0[2];
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///////////////////////////////////////
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// Interface to command memory 1
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///////////////////////////////////////
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sc_signal<sc_bv<CMD_BUFFER_MEM_WIDTH> > ro1_command_packet_wr_data;
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sc_signal<bool > ro1_command_packet_write;
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sc_signal<sc_uint<LOG2_NB_OF_BUFFERS+2> > ro1_command_packet_wr_addr;
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sc_signal<sc_uint<LOG2_NB_OF_BUFFERS+2> > ro1_command_packet_rd_addr[2];
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sc_signal<sc_bv<CMD_BUFFER_MEM_WIDTH> > command_packet_rd_data_ro1[2];
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//************************************
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// Reset generated by link
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//************************************
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//sc_signal<bool> warmrstx;
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//sc_signal<bool> coldrstx;
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//sc_signal<bool> dummy_warmrstx;
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//sc_signal<bool> dummy_coldrstx;
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//******************************************
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// Signals to User
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//******************************************
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//------------------------------------------
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// Signals to send received packets to User
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//------------------------------------------
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/**The actual control/data packet to the user*/
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sc_signal<sc_bv<64> > ui_packet_usr;
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/**The virtual channel of the ctl/data packet*/
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sc_signal<VirtualChannel> ui_vc_usr;
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/**The side from which came the packet*/
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sc_signal< bool > ui_side_usr;
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/**If the packet is a direct_route packet - only valid for
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requests (posted and non-posted) */
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sc_signal<bool> ui_directroute_usr;
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/**If this is the last part of the packet*/
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sc_signal< bool > ui_eop_usr;
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/**If there is another packet available*/
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sc_signal< bool > ui_available_usr;
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/**If what is read is 64 bits or 32 bits*/
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sc_signal< bool > ui_output_64bits_usr;
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/**To allow the user to consume the packets*/
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sc_signal< bool > usr_consume_ui;
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//------------------------------------------
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// Signals to allow the User to send packets
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//------------------------------------------
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/**The actual control/data packet from the user*/
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sc_signal<sc_bv<64> > usr_packet_ui;
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/**If there is another packet available*/
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sc_signal< bool > usr_available_ui;
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/**
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The side to send the packet if it is a response
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This bit is ignored if the packet is not a response
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since the side to send a request is determined automatically
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taking in acount DirectRoute functionnality.
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*/
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sc_signal< bool > usr_side_ui;
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/**If the packet is trying to be sent to a VC that is full,
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We let the user know that he is doing something illegal
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Packet is not consumed if this is 1
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*/
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//sc_signal < bool > ui_invalid_usr;
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/**Which what type of ctl packets can be sent to side0*/
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sc_signal<sc_bv<6> > ui_freevc0_usr;
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/**Which what type of ctl packets can be sent to side0*/
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sc_signal<sc_bv<6> > ui_freevc1_usr;
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//-----------------------------------------------
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// Content of CSR that might be useful to user
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//-----------------------------------------------
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/** Signals table containing all 40 bits Base Addresses from BARs implemented */
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sc_signal<sc_bv<40> > csr_bar[NbRegsBars];
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/** Signal from register Interface->Command->csr_unit_id */
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sc_signal<sc_bv<5> > csr_unit_id;
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| 308 |
|
|
|
| 309 |
|
|
//------------------------------------------
|
| 310 |
|
|
// Signals to affect CSR
|
| 311 |
|
|
//------------------------------------------
|
| 312 |
|
|
sc_signal<bool> usr_receivedResponseError_csr;
|
| 313 |
|
|
|
| 314 |
|
|
//--------------------------------------------------------
|
| 315 |
|
|
// Interface for having registers outside CSR if necessary
|
| 316 |
|
|
//--------------------------------------------------------
|
| 317 |
|
|
|
| 318 |
|
|
///Signals to allow external registers with minimal logic
|
| 319 |
|
|
/**
|
| 320 |
|
|
Connect usr_read_data_csr to zeroes if not used!
|
| 321 |
|
|
*/
|
| 322 |
|
|
//@{
|
| 323 |
|
|
sc_signal<sc_uint<6> > csr_read_addr_usr;
|
| 324 |
|
|
sc_signal<sc_bv<32> > usr_read_data_csr;
|
| 325 |
|
|
sc_signal<bool > csr_write_usr;
|
| 326 |
|
|
sc_signal<sc_uint<6> > csr_write_addr_usr;
|
| 327 |
|
|
sc_signal<sc_bv<32> > csr_write_data_usr;
|
| 328 |
|
|
/**Every bit is a byte mask for the dword to write*/
|
| 329 |
|
|
sc_signal<sc_bv<4> > csr_write_mask_usr;
|
| 330 |
|
|
//@}
|
| 331 |
|
|
|
| 332 |
|
|
// ***************************************************
|
| 333 |
|
|
// LINKING DUT
|
| 334 |
|
|
// ***************************************************
|
| 335 |
|
|
|
| 336 |
|
|
the_ht_tunnel->clk(clk);
|
| 337 |
|
|
the_ht_tunnel->resetx(resetx);
|
| 338 |
|
|
the_ht_tunnel->pwrok(pwrok);
|
| 339 |
|
|
the_ht_tunnel->ldtstopx(ldtstopx);
|
| 340 |
|
|
|
| 341 |
|
|
the_ht_tunnel->phy0_available_lk0(phy0_available_lk0);
|
| 342 |
|
|
the_ht_tunnel->phy0_ctl_lk0(phy0_ctl_lk0);
|
| 343 |
|
|
|
| 344 |
|
|
for(int n = 0; n < CAD_IN_WIDTH; n++){
|
| 345 |
|
|
the_ht_tunnel->phy0_cad_lk0[n](phy0_cad_lk0[n]);
|
| 346 |
|
|
the_ht_tunnel->lk0_cad_phy0[n](lk0_cad_phy0[n]);
|
| 347 |
|
|
the_ht_tunnel->phy1_cad_lk1[n](phy1_cad_lk1[n]);
|
| 348 |
|
|
the_ht_tunnel->lk1_cad_phy1[n](lk1_cad_phy1[n]);
|
| 349 |
|
|
}
|
| 350 |
|
|
|
| 351 |
|
|
the_ht_tunnel->lk0_ctl_phy0(lk0_ctl_phy0);
|
| 352 |
|
|
the_ht_tunnel->phy0_consume_lk0(phy0_consume_lk0);
|
| 353 |
|
|
|
| 354 |
|
|
the_ht_tunnel->lk0_disable_drivers_phy0(lk0_disable_drivers_phy0);
|
| 355 |
|
|
the_ht_tunnel->lk0_disable_receivers_phy0(lk0_disable_receivers_phy0);
|
| 356 |
6 |
acastong |
the_ht_tunnel->link_frequency0_phy(link_frequency0_phy);
|
| 357 |
2 |
acastong |
|
| 358 |
|
|
#ifndef INTERNAL_SHIFTER_ALIGNMENT
|
| 359 |
|
|
the_ht_tunnel->lk0_deser_stall_phy0(lk0_deser_stall_phy0);
|
| 360 |
|
|
the_ht_tunnel->lk0_deser_stall_cycles_phy0(lk0_deser_stall_cycles_phy0);
|
| 361 |
|
|
#endif
|
| 362 |
|
|
|
| 363 |
|
|
the_ht_tunnel->phy1_available_lk1(phy1_available_lk1);
|
| 364 |
|
|
the_ht_tunnel->phy1_ctl_lk1(phy1_ctl_lk1);
|
| 365 |
|
|
|
| 366 |
|
|
the_ht_tunnel->lk1_ctl_phy1(lk1_ctl_phy1);
|
| 367 |
|
|
the_ht_tunnel->phy1_consume_lk1(phy1_consume_lk1);
|
| 368 |
|
|
|
| 369 |
|
|
the_ht_tunnel->lk1_disable_drivers_phy1(lk1_disable_drivers_phy1);
|
| 370 |
|
|
the_ht_tunnel->lk1_disable_receivers_phy1(lk1_disable_receivers_phy1);
|
| 371 |
6 |
acastong |
the_ht_tunnel->link_frequency1_phy(link_frequency1_phy);
|
| 372 |
2 |
acastong |
|
| 373 |
|
|
#ifndef INTERNAL_SHIFTER_ALIGNMENT
|
| 374 |
|
|
the_ht_tunnel->lk1_deser_stall_phy1(lk1_deser_stall_phy1);
|
| 375 |
|
|
the_ht_tunnel->lk1_deser_stall_cycles_phy1(lk1_deser_stall_cycles_phy1);
|
| 376 |
|
|
#endif
|
| 377 |
|
|
|
| 378 |
|
|
the_ht_tunnel->ui_memory_write0(ui_memory_write0);
|
| 379 |
|
|
the_ht_tunnel->ui_memory_write1(ui_memory_write1);//20
|
| 380 |
|
|
the_ht_tunnel->ui_memory_write_address(ui_memory_write_address);
|
| 381 |
|
|
the_ht_tunnel->ui_memory_write_data(ui_memory_write_data);
|
| 382 |
|
|
|
| 383 |
|
|
the_ht_tunnel->ui_memory_read_address0(ui_memory_read_address0);
|
| 384 |
|
|
the_ht_tunnel->ui_memory_read_address1(ui_memory_read_address1);
|
| 385 |
|
|
the_ht_tunnel->ui_memory_read_data0(ui_memory_read_data0);
|
| 386 |
|
|
the_ht_tunnel->ui_memory_read_data1(ui_memory_read_data1);
|
| 387 |
|
|
|
| 388 |
|
|
#ifdef RETRY_MODE_ENABLED
|
| 389 |
|
|
the_ht_tunnel->history_memory_write0(history_memory_write0);
|
| 390 |
|
|
the_ht_tunnel->history_memory_write_address0(history_memory_write_address0);
|
| 391 |
|
|
the_ht_tunnel->history_memory_write_data0(history_memory_write_data0);
|
| 392 |
|
|
the_ht_tunnel->history_memory_read_address0(history_memory_read_address0);//30
|
| 393 |
|
|
the_ht_tunnel->history_memory_output0(history_memory_output0);
|
| 394 |
|
|
|
| 395 |
|
|
the_ht_tunnel->history_memory_write1(history_memory_write1);
|
| 396 |
|
|
the_ht_tunnel->history_memory_write_address1(history_memory_write_address1);
|
| 397 |
|
|
the_ht_tunnel->history_memory_write_data1(history_memory_write_data1);
|
| 398 |
|
|
the_ht_tunnel->history_memory_read_address1(history_memory_read_address1);
|
| 399 |
|
|
the_ht_tunnel->history_memory_output1(history_memory_output1);
|
| 400 |
|
|
|
| 401 |
|
|
#endif
|
| 402 |
|
|
|
| 403 |
|
|
|
| 404 |
|
|
the_ht_tunnel->memory_write0(memory_write0);
|
| 405 |
|
|
the_ht_tunnel->memory_write_address_vc0(memory_write_address_vc0);
|
| 406 |
|
|
the_ht_tunnel->memory_write_address_buffer0(memory_write_address_buffer0);
|
| 407 |
|
|
the_ht_tunnel->memory_write_address_pos0(memory_write_address_pos0);//40
|
| 408 |
|
|
the_ht_tunnel->memory_write_data0(memory_write_data0);
|
| 409 |
|
|
|
| 410 |
|
|
the_ht_tunnel->memory_read_address_vc0[0](memory_read_address_vc0[0]);
|
| 411 |
|
|
the_ht_tunnel->memory_read_address_buffer0[0](memory_read_address_buffer0[0]);
|
| 412 |
|
|
the_ht_tunnel->memory_read_address_pos0[0](memory_read_address_pos0[0]);//50
|
| 413 |
|
|
the_ht_tunnel->memory_output0[0](memory_output0[0]);
|
| 414 |
|
|
|
| 415 |
|
|
the_ht_tunnel->memory_read_address_vc0[1](memory_read_address_vc0[1]);
|
| 416 |
|
|
the_ht_tunnel->memory_read_address_buffer0[1](memory_read_address_buffer0[1]);
|
| 417 |
|
|
the_ht_tunnel->memory_read_address_pos0[1](memory_read_address_pos0[1]);//50
|
| 418 |
|
|
the_ht_tunnel->memory_output0[1](memory_output0[1]);
|
| 419 |
|
|
|
| 420 |
|
|
|
| 421 |
|
|
the_ht_tunnel->memory_write1(memory_write1);
|
| 422 |
|
|
the_ht_tunnel->memory_write_address_vc1(memory_write_address_vc1);
|
| 423 |
|
|
the_ht_tunnel->memory_write_address_buffer1(memory_write_address_buffer1);
|
| 424 |
|
|
the_ht_tunnel->memory_write_address_pos1(memory_write_address_pos1);
|
| 425 |
|
|
the_ht_tunnel->memory_write_data1(memory_write_data1);
|
| 426 |
|
|
|
| 427 |
|
|
the_ht_tunnel->memory_read_address_vc1[0](memory_read_address_vc1[0]);
|
| 428 |
|
|
the_ht_tunnel->memory_read_address_buffer1[0](memory_read_address_buffer1[0]);
|
| 429 |
|
|
the_ht_tunnel->memory_read_address_pos1[0](memory_read_address_pos1[0]);
|
| 430 |
|
|
the_ht_tunnel->memory_output1[0](memory_output1[0]);
|
| 431 |
|
|
|
| 432 |
|
|
the_ht_tunnel->memory_read_address_vc1[1](memory_read_address_vc1[1]);
|
| 433 |
|
|
the_ht_tunnel->memory_read_address_buffer1[1](memory_read_address_buffer1[1]);
|
| 434 |
|
|
the_ht_tunnel->memory_read_address_pos1[1](memory_read_address_pos1[1]);
|
| 435 |
|
|
the_ht_tunnel->memory_output1[1](memory_output1[1]);
|
| 436 |
|
|
|
| 437 |
|
|
the_ht_tunnel->ro0_command_packet_wr_data(ro0_command_packet_wr_data);
|
| 438 |
|
|
the_ht_tunnel->ro0_command_packet_write(ro0_command_packet_write);
|
| 439 |
|
|
the_ht_tunnel->ro0_command_packet_wr_addr(ro0_command_packet_wr_addr);
|
| 440 |
|
|
the_ht_tunnel->ro0_command_packet_rd_addr[0](ro0_command_packet_rd_addr[0]);
|
| 441 |
|
|
the_ht_tunnel->command_packet_rd_data_ro0[0](command_packet_rd_data_ro0[0]);
|
| 442 |
|
|
the_ht_tunnel->ro0_command_packet_rd_addr[1](ro0_command_packet_rd_addr[1]);
|
| 443 |
|
|
the_ht_tunnel->command_packet_rd_data_ro0[1](command_packet_rd_data_ro0[1]);
|
| 444 |
|
|
|
| 445 |
|
|
the_ht_tunnel->ro1_command_packet_wr_data(ro1_command_packet_wr_data);
|
| 446 |
|
|
the_ht_tunnel->ro1_command_packet_write(ro1_command_packet_write);
|
| 447 |
|
|
the_ht_tunnel->ro1_command_packet_wr_addr(ro1_command_packet_wr_addr);
|
| 448 |
|
|
the_ht_tunnel->ro1_command_packet_rd_addr[0](ro1_command_packet_rd_addr[0]);
|
| 449 |
|
|
the_ht_tunnel->command_packet_rd_data_ro1[0](command_packet_rd_data_ro1[0]);
|
| 450 |
|
|
the_ht_tunnel->ro1_command_packet_rd_addr[1](ro1_command_packet_rd_addr[1]);
|
| 451 |
|
|
the_ht_tunnel->command_packet_rd_data_ro1[1](command_packet_rd_data_ro1[1]);
|
| 452 |
|
|
|
| 453 |
|
|
the_ht_tunnel->ui_packet_usr(ui_packet_usr);
|
| 454 |
|
|
the_ht_tunnel->ui_vc_usr(ui_vc_usr);
|
| 455 |
|
|
the_ht_tunnel->ui_side_usr(ui_side_usr);
|
| 456 |
|
|
#ifdef ENABLE_DIRECTROUTE
|
| 457 |
|
|
the_ht_tunnel->ui_directroute_usr(ui_directroute_usr);
|
| 458 |
|
|
#endif
|
| 459 |
|
|
the_ht_tunnel->ui_eop_usr(ui_eop_usr);
|
| 460 |
|
|
the_ht_tunnel->ui_available_usr(ui_available_usr);
|
| 461 |
|
|
the_ht_tunnel->ui_output_64bits_usr(ui_output_64bits_usr);
|
| 462 |
|
|
the_ht_tunnel->usr_consume_ui(usr_consume_ui);
|
| 463 |
|
|
the_ht_tunnel->usr_packet_ui(usr_packet_ui);
|
| 464 |
|
|
the_ht_tunnel->usr_available_ui(usr_available_ui);
|
| 465 |
|
|
the_ht_tunnel->usr_side_ui(usr_side_ui);
|
| 466 |
|
|
the_ht_tunnel->ui_freevc0_usr(ui_freevc0_usr);
|
| 467 |
|
|
the_ht_tunnel->ui_freevc1_usr(ui_freevc1_usr);
|
| 468 |
|
|
for(int n = 0; n < NbRegsBars; n++)
|
| 469 |
|
|
the_ht_tunnel->csr_bar[n](csr_bar[n]);
|
| 470 |
|
|
the_ht_tunnel->csr_unit_id(csr_unit_id);
|
| 471 |
|
|
the_ht_tunnel->usr_receivedResponseError_csr(usr_receivedResponseError_csr);
|
| 472 |
|
|
|
| 473 |
|
|
the_ht_tunnel->csr_read_addr_usr(csr_read_addr_usr);
|
| 474 |
|
|
the_ht_tunnel->usr_read_data_csr(usr_read_data_csr);
|
| 475 |
|
|
the_ht_tunnel->csr_write_usr(csr_write_usr);
|
| 476 |
|
|
the_ht_tunnel->csr_write_addr_usr(csr_write_addr_usr);
|
| 477 |
|
|
the_ht_tunnel->csr_write_data_usr(csr_write_data_usr);
|
| 478 |
|
|
the_ht_tunnel->csr_write_mask_usr(csr_write_mask_usr);
|
| 479 |
|
|
|
| 480 |
|
|
// ***************************************************
|
| 481 |
|
|
// LINKING TB
|
| 482 |
|
|
// ***************************************************
|
| 483 |
|
|
|
| 484 |
|
|
tb->clk(clk);
|
| 485 |
|
|
tb->resetx(resetx);
|
| 486 |
|
|
tb->pwrok(pwrok);
|
| 487 |
|
|
tb->ldtstopx(ldtstopx);
|
| 488 |
|
|
|
| 489 |
|
|
tb->phy0_available_lk0(phy0_available_lk0);
|
| 490 |
|
|
tb->phy0_ctl_lk0(phy0_ctl_lk0);
|
| 491 |
|
|
|
| 492 |
|
|
for(int n = 0; n < CAD_IN_WIDTH; n++){
|
| 493 |
|
|
tb->phy0_cad_lk0[n](phy0_cad_lk0[n]);
|
| 494 |
|
|
tb->lk0_cad_phy0[n](lk0_cad_phy0[n]);
|
| 495 |
|
|
tb->phy1_cad_lk1[n](phy1_cad_lk1[n]);
|
| 496 |
|
|
tb->lk1_cad_phy1[n](lk1_cad_phy1[n]);
|
| 497 |
|
|
}
|
| 498 |
|
|
|
| 499 |
|
|
tb->lk0_ctl_phy0(lk0_ctl_phy0);
|
| 500 |
|
|
tb->phy0_consume_lk0(phy0_consume_lk0);
|
| 501 |
|
|
|
| 502 |
|
|
tb->lk0_disable_drivers_phy0(lk0_disable_drivers_phy0);
|
| 503 |
|
|
tb->lk0_disable_receivers_phy0(lk0_disable_receivers_phy0);
|
| 504 |
|
|
|
| 505 |
|
|
tb->phy1_available_lk1(phy1_available_lk1);
|
| 506 |
|
|
tb->phy1_ctl_lk1(phy1_ctl_lk1);
|
| 507 |
|
|
|
| 508 |
|
|
tb->lk1_ctl_phy1(lk1_ctl_phy1);
|
| 509 |
|
|
tb->phy1_consume_lk1(phy1_consume_lk1);
|
| 510 |
|
|
|
| 511 |
|
|
tb->lk1_disable_drivers_phy1(lk1_disable_drivers_phy1);
|
| 512 |
|
|
tb->lk1_disable_receivers_phy1(lk1_disable_receivers_phy1);
|
| 513 |
|
|
|
| 514 |
|
|
tb->ui_memory_write0(ui_memory_write0);
|
| 515 |
|
|
tb->ui_memory_write1(ui_memory_write1);//20
|
| 516 |
|
|
tb->ui_memory_write_address(ui_memory_write_address);
|
| 517 |
|
|
tb->ui_memory_write_data(ui_memory_write_data);
|
| 518 |
|
|
|
| 519 |
|
|
tb->ui_memory_read_address0(ui_memory_read_address0);
|
| 520 |
|
|
tb->ui_memory_read_address1(ui_memory_read_address1);
|
| 521 |
|
|
tb->ui_memory_read_data0(ui_memory_read_data0);
|
| 522 |
|
|
tb->ui_memory_read_data1(ui_memory_read_data1);
|
| 523 |
|
|
|
| 524 |
|
|
#ifdef RETRY_MODE_ENABLED
|
| 525 |
|
|
tb->history_memory_write0(history_memory_write0);
|
| 526 |
|
|
tb->history_memory_write_address0(history_memory_write_address0);
|
| 527 |
|
|
tb->history_memory_write_data0(history_memory_write_data0);
|
| 528 |
|
|
tb->history_memory_read_address0(history_memory_read_address0);//30
|
| 529 |
|
|
tb->history_memory_output0(history_memory_output0);
|
| 530 |
|
|
|
| 531 |
|
|
tb->history_memory_write1(history_memory_write1);
|
| 532 |
|
|
tb->history_memory_write_address1(history_memory_write_address1);
|
| 533 |
|
|
tb->history_memory_write_data1(history_memory_write_data1);
|
| 534 |
|
|
tb->history_memory_read_address1(history_memory_read_address1);
|
| 535 |
|
|
tb->history_memory_output1(history_memory_output1);
|
| 536 |
|
|
|
| 537 |
|
|
#endif
|
| 538 |
|
|
|
| 539 |
|
|
|
| 540 |
|
|
tb->memory_write0(memory_write0);
|
| 541 |
|
|
tb->memory_write_address_vc0(memory_write_address_vc0);
|
| 542 |
|
|
tb->memory_write_address_buffer0(memory_write_address_buffer0);
|
| 543 |
|
|
tb->memory_write_address_pos0(memory_write_address_pos0);//40
|
| 544 |
|
|
tb->memory_write_data0(memory_write_data0);
|
| 545 |
|
|
|
| 546 |
|
|
tb->memory_read_address_vc0[0](memory_read_address_vc0[0]);
|
| 547 |
|
|
tb->memory_read_address_buffer0[0](memory_read_address_buffer0[0]);
|
| 548 |
|
|
tb->memory_read_address_pos0[0](memory_read_address_pos0[0]);//50
|
| 549 |
|
|
tb->memory_output0[0](memory_output0[0]);
|
| 550 |
|
|
|
| 551 |
|
|
tb->memory_read_address_vc0[1](memory_read_address_vc0[1]);
|
| 552 |
|
|
tb->memory_read_address_buffer0[1](memory_read_address_buffer0[1]);
|
| 553 |
|
|
tb->memory_read_address_pos0[1](memory_read_address_pos0[1]);//50
|
| 554 |
|
|
tb->memory_output0[1](memory_output0[1]);
|
| 555 |
|
|
|
| 556 |
|
|
|
| 557 |
|
|
tb->memory_write1(memory_write1);
|
| 558 |
|
|
tb->memory_write_address_vc1(memory_write_address_vc1);
|
| 559 |
|
|
tb->memory_write_address_buffer1(memory_write_address_buffer1);
|
| 560 |
|
|
tb->memory_write_address_pos1(memory_write_address_pos1);
|
| 561 |
|
|
tb->memory_write_data1(memory_write_data1);
|
| 562 |
|
|
|
| 563 |
|
|
tb->memory_read_address_vc1[0](memory_read_address_vc1[0]);
|
| 564 |
|
|
tb->memory_read_address_buffer1[0](memory_read_address_buffer1[0]);
|
| 565 |
|
|
tb->memory_read_address_pos1[0](memory_read_address_pos1[0]);
|
| 566 |
|
|
tb->memory_output1[0](memory_output1[0]);
|
| 567 |
|
|
|
| 568 |
|
|
tb->memory_read_address_vc1[1](memory_read_address_vc1[1]);
|
| 569 |
|
|
tb->memory_read_address_buffer1[1](memory_read_address_buffer1[1]);
|
| 570 |
|
|
tb->memory_read_address_pos1[1](memory_read_address_pos1[1]);
|
| 571 |
|
|
tb->memory_output1[1](memory_output1[1]);
|
| 572 |
|
|
|
| 573 |
|
|
tb->ro0_command_packet_wr_data(ro0_command_packet_wr_data);
|
| 574 |
|
|
tb->ro0_command_packet_write(ro0_command_packet_write);
|
| 575 |
|
|
tb->ro0_command_packet_wr_addr(ro0_command_packet_wr_addr);
|
| 576 |
|
|
tb->ro0_command_packet_rd_addr[0](ro0_command_packet_rd_addr[0]);
|
| 577 |
|
|
tb->command_packet_rd_data_ro0[0](command_packet_rd_data_ro0[0]);
|
| 578 |
|
|
tb->ro0_command_packet_rd_addr[1](ro0_command_packet_rd_addr[1]);
|
| 579 |
|
|
tb->command_packet_rd_data_ro0[1](command_packet_rd_data_ro0[1]);
|
| 580 |
|
|
|
| 581 |
|
|
tb->ro1_command_packet_wr_data(ro1_command_packet_wr_data);
|
| 582 |
|
|
tb->ro1_command_packet_write(ro1_command_packet_write);
|
| 583 |
|
|
tb->ro1_command_packet_wr_addr(ro1_command_packet_wr_addr);
|
| 584 |
|
|
tb->ro1_command_packet_rd_addr[0](ro1_command_packet_rd_addr[0]);
|
| 585 |
|
|
tb->command_packet_rd_data_ro1[0](command_packet_rd_data_ro1[0]);
|
| 586 |
|
|
tb->ro1_command_packet_rd_addr[1](ro1_command_packet_rd_addr[1]);
|
| 587 |
|
|
tb->command_packet_rd_data_ro1[1](command_packet_rd_data_ro1[1]);
|
| 588 |
|
|
|
| 589 |
|
|
tb->ui_packet_usr(ui_packet_usr);
|
| 590 |
|
|
tb->ui_vc_usr(ui_vc_usr);
|
| 591 |
|
|
tb->ui_side_usr(ui_side_usr);
|
| 592 |
|
|
tb->ui_directroute_usr(ui_directroute_usr);
|
| 593 |
|
|
tb->ui_eop_usr(ui_eop_usr);
|
| 594 |
|
|
tb->ui_available_usr(ui_available_usr);
|
| 595 |
|
|
tb->ui_output_64bits_usr(ui_output_64bits_usr);
|
| 596 |
|
|
tb->usr_consume_ui(usr_consume_ui);
|
| 597 |
|
|
tb->usr_packet_ui(usr_packet_ui);
|
| 598 |
|
|
tb->usr_available_ui(usr_available_ui);
|
| 599 |
|
|
tb->usr_side_ui(usr_side_ui);
|
| 600 |
|
|
tb->ui_freevc0_usr(ui_freevc0_usr);
|
| 601 |
|
|
tb->ui_freevc1_usr(ui_freevc1_usr);
|
| 602 |
|
|
tb->usr_receivedResponseError_csr(usr_receivedResponseError_csr);
|
| 603 |
|
|
|
| 604 |
|
|
|
| 605 |
|
|
// ***************************************************
|
| 606 |
|
|
// Tracing signals
|
| 607 |
|
|
// ***************************************************
|
| 608 |
|
|
|
| 609 |
|
|
sc_trace_file *tf = sc_create_vcd_trace_file("sim_vc_ht_tunnel_l1");
|
| 610 |
|
|
|
| 611 |
|
|
sc_trace(tf,clk,"clk");
|
| 612 |
|
|
sc_trace(tf,resetx,"resetx");
|
| 613 |
|
|
sc_trace(tf,pwrok,"pwrok");
|
| 614 |
|
|
sc_trace(tf,ldtstopx,"ldtstopx");
|
| 615 |
|
|
|
| 616 |
|
|
sc_trace(tf,phy0_available_lk0,"phy0_available_lk0");
|
| 617 |
|
|
sc_trace(tf,phy0_ctl_lk0,"phy0_ctl_lk0");
|
| 618 |
|
|
|
| 619 |
|
|
for(int n = 0; n < CAD_IN_WIDTH; n++){
|
| 620 |
|
|
ostringstream o;
|
| 621 |
|
|
o << "phy0_cad_lk0(" << n << ")";
|
| 622 |
|
|
sc_trace(tf,phy0_cad_lk0[n],o.str().c_str());
|
| 623 |
|
|
o.str("");
|
| 624 |
|
|
o << "lk0_cad_phy0(" << n << ")";
|
| 625 |
|
|
sc_trace(tf,lk0_cad_phy0[n],o.str().c_str());
|
| 626 |
|
|
o.str("");
|
| 627 |
|
|
o << "phy1_cad_lk1(" << n << ")";
|
| 628 |
|
|
sc_trace(tf,phy1_cad_lk1[n],o.str().c_str());
|
| 629 |
|
|
o.str("");
|
| 630 |
|
|
o << "lk1_cad_phy1(" << n << ")";
|
| 631 |
|
|
sc_trace(tf,lk1_cad_phy1[n],o.str().c_str());
|
| 632 |
|
|
}
|
| 633 |
|
|
|
| 634 |
|
|
sc_trace(tf,lk0_ctl_phy0,"lk0_ctl_phy0");
|
| 635 |
|
|
sc_trace(tf,phy0_consume_lk0,"phy0_consume_lk0");
|
| 636 |
|
|
|
| 637 |
|
|
sc_trace(tf,lk0_disable_drivers_phy0,"lk0_disable_drivers_phy0");
|
| 638 |
|
|
sc_trace(tf,lk0_disable_receivers_phy0,"lk0_disable_receivers_phy0");
|
| 639 |
|
|
|
| 640 |
|
|
sc_trace(tf,phy1_available_lk1,"phy1_available_lk1");
|
| 641 |
|
|
sc_trace(tf,phy1_ctl_lk1,"phy1_ctl_lk1");
|
| 642 |
|
|
|
| 643 |
|
|
sc_trace(tf,lk1_ctl_phy1,"lk1_ctl_phy1");
|
| 644 |
|
|
sc_trace(tf,phy1_consume_lk1,"phy1_consume_lk1");
|
| 645 |
|
|
|
| 646 |
|
|
sc_trace(tf,lk1_disable_drivers_phy1,"lk1_disable_drivers_phy1");
|
| 647 |
|
|
sc_trace(tf,lk1_disable_receivers_phy1,"lk1_disable_receivers_phy1");
|
| 648 |
|
|
|
| 649 |
|
|
|
| 650 |
|
|
/* sc_trace(tf,ui_memory_write0,"ui_memory_write0");
|
| 651 |
|
|
sc_trace(tf,ui_memory_write1,"ui_memory_write1");
|
| 652 |
|
|
sc_trace(tf,ui_memory_write_address,"ui_memory_write_address");
|
| 653 |
|
|
sc_trace(tf,ui_memory_write_data,"ui_memory_write_data");
|
| 654 |
|
|
|
| 655 |
|
|
sc_trace(tf,ui_memory_read_address0,"ui_memory_read_address0");
|
| 656 |
|
|
sc_trace(tf,ui_memory_read_address1,"ui_memory_read_address1");
|
| 657 |
|
|
sc_trace(tf,ui_memory_read_data0,"ui_memory_read_data0");
|
| 658 |
|
|
sc_trace(tf,ui_memory_read_data1,"ui_memory_read_data1");
|
| 659 |
|
|
*/
|
| 660 |
|
|
|
| 661 |
|
|
#ifdef RETRY_MODE_ENABLED
|
| 662 |
|
|
/*
|
| 663 |
|
|
sc_trace(tf,history_memory_write0,"history_memory_write0");
|
| 664 |
|
|
sc_trace(tf,history_memory_write_address0,"history_memory_write_address0");
|
| 665 |
|
|
sc_trace(tf,history_memory_write_data0,"history_memory_write_data0");
|
| 666 |
|
|
sc_trace(tf,history_memory_read_address0,"history_memory_read_address0");
|
| 667 |
|
|
sc_trace(tf,history_memory_output0,"history_memory_output0");*/
|
| 668 |
|
|
|
| 669 |
|
|
/* sc_trace(tf,history_memory_write1,"history_memory_write1");
|
| 670 |
|
|
sc_trace(tf,history_memory_write_address1,"history_memory_write_address1");
|
| 671 |
|
|
sc_trace(tf,history_memory_write_data1,"history_memory_write_data1");
|
| 672 |
|
|
sc_trace(tf,history_memory_read_address1,"history_memory_read_address1");
|
| 673 |
|
|
sc_trace(tf,history_memory_output1,"history_memory_output1");
|
| 674 |
|
|
*/
|
| 675 |
|
|
#endif
|
| 676 |
|
|
|
| 677 |
|
|
sc_trace(tf,memory_write0,"memory_write0");
|
| 678 |
|
|
sc_trace(tf,memory_write_address_vc0,"memory_write_address_vc0");
|
| 679 |
|
|
sc_trace(tf,memory_write_address_buffer0,"memory_write_address_buffer0");
|
| 680 |
|
|
sc_trace(tf,memory_write_address_pos0,"memory_write_address_pos0");
|
| 681 |
|
|
sc_trace(tf,memory_write_data0,"memory_write_data0");
|
| 682 |
|
|
|
| 683 |
|
|
sc_trace(tf,memory_read_address_vc0[0],"memory_read_address_vc0(0)");
|
| 684 |
|
|
sc_trace(tf,memory_read_address_buffer0[0],"memory_read_address_buffer0(0)");
|
| 685 |
|
|
sc_trace(tf,memory_read_address_pos0[0],"memory_read_address_pos0(0)");
|
| 686 |
|
|
sc_trace(tf,memory_output0[0],"memory_output0(0)");
|
| 687 |
|
|
|
| 688 |
|
|
/*
|
| 689 |
|
|
sc_trace(tf,memory_read_address_vc0[1],"memory_read_address_vc0(1)");
|
| 690 |
|
|
sc_trace(tf,memory_read_address_buffer0[1],"memory_read_address_buffer0(1)");
|
| 691 |
|
|
sc_trace(tf,memory_read_address_pos0[1],"memory_read_address_pos0(1)");
|
| 692 |
|
|
sc_trace(tf,memory_output0[1],"memory_output0(1)");
|
| 693 |
|
|
|
| 694 |
|
|
|
| 695 |
|
|
sc_trace(tf,memory_write1,"memory_write1");
|
| 696 |
|
|
sc_trace(tf,memory_write_address_vc1,"memory_write_address_vc1");
|
| 697 |
|
|
sc_trace(tf,memory_write_address_buffer1,"memory_write_address_buffer1");
|
| 698 |
|
|
sc_trace(tf,memory_write_address_pos1,"memory_write_address_pos1");
|
| 699 |
|
|
sc_trace(tf,memory_write_data1,"memory_write_data1");
|
| 700 |
|
|
|
| 701 |
|
|
sc_trace(tf,memory_read_address_vc1[0],"memory_read_address_vc1(0)");
|
| 702 |
|
|
sc_trace(tf,memory_read_address_buffer1[0],"memory_read_address_buffer1(0)");
|
| 703 |
|
|
sc_trace(tf,memory_read_address_pos1[0],"memory_read_address_pos1(0)");
|
| 704 |
|
|
sc_trace(tf,memory_output1[0],"memory_output1(0)");
|
| 705 |
|
|
|
| 706 |
|
|
sc_trace(tf,memory_read_address_vc1[1],"memory_read_address_vc1(1)");
|
| 707 |
|
|
sc_trace(tf,memory_read_address_buffer1[1],"memory_read_address_buffer1(1)");
|
| 708 |
|
|
sc_trace(tf,memory_read_address_pos1[1],"memory_read_address_pos1(1)");
|
| 709 |
|
|
sc_trace(tf,memory_output1[1],"memory_output1(1)");
|
| 710 |
|
|
|
| 711 |
|
|
*/
|
| 712 |
|
|
sc_trace(tf,ui_packet_usr,"ui_packet_usr");
|
| 713 |
|
|
sc_trace(tf,ui_vc_usr,"ui_vc_usr");
|
| 714 |
|
|
sc_trace(tf,ui_side_usr,"ui_side_usr");
|
| 715 |
|
|
sc_trace(tf,ui_directroute_usr,"ui_directroute_usr");
|
| 716 |
|
|
sc_trace(tf,ui_eop_usr,"ui_eop_usr");
|
| 717 |
|
|
sc_trace(tf,ui_available_usr,"ui_available_usr");
|
| 718 |
|
|
sc_trace(tf,ui_output_64bits_usr,"ui_output_64bits_usr");
|
| 719 |
|
|
sc_trace(tf,usr_consume_ui,"usr_consume_ui");
|
| 720 |
|
|
sc_trace(tf,usr_packet_ui,"usr_packet_ui");
|
| 721 |
|
|
sc_trace(tf,usr_available_ui,"usr_available_ui");
|
| 722 |
|
|
sc_trace(tf,usr_side_ui,"usr_side_ui");
|
| 723 |
|
|
sc_trace(tf,ui_freevc0_usr,"ui_freevc0_usr");
|
| 724 |
|
|
sc_trace(tf,ui_freevc1_usr,"ui_freevc1_usr");
|
| 725 |
|
|
sc_trace(tf,usr_receivedResponseError_csr,"usr_receivedResponseError_csr");
|
| 726 |
|
|
|
| 727 |
|
|
sc_trace(tf,the_ht_tunnel->the_decoder0_l2->cd_datalen_db,"DECODER.cd_datalen_db");
|
| 728 |
|
|
sc_trace(tf,the_ht_tunnel->the_decoder0_l2->cd_data_db,"DECODER.cd_data_db");
|
| 729 |
|
|
#ifdef RETRY_MODE_ENABLED
|
| 730 |
|
|
sc_trace(tf,the_ht_tunnel->the_decoder0_l2->cd_drop_db,"DECODER.cd_drop_db");
|
| 731 |
|
|
sc_trace(tf,the_ht_tunnel->the_decoder0_l2->csr_retry,"DECODER.csr_retry");
|
| 732 |
|
|
#endif
|
| 733 |
|
|
sc_trace(tf,the_ht_tunnel->the_decoder0_l2->cd_getaddr_db,"DECODER.cd_getaddr_db");
|
| 734 |
|
|
sc_trace(tf,the_ht_tunnel->the_decoder0_l2->cd_vctype_db,"DECODER.cd_vctype_db");
|
| 735 |
|
|
sc_trace(tf,the_ht_tunnel->the_decoder0_l2->cd_write_db,"DECODER.cd_write_db");
|
| 736 |
|
|
sc_trace(tf,the_ht_tunnel->the_decoder0_l2->cd_protocol_error_csr,"DECODER.cd_protocol_error_csr");
|
| 737 |
|
|
sc_trace(tf,the_ht_tunnel->the_decoder0_l2->lk_available_cd,"DECODER.lk_available_cd");
|
| 738 |
|
|
sc_trace(tf,the_ht_tunnel->the_decoder0_l2->lk_dword_cd,"DECODER.lk_dword_cd");
|
| 739 |
|
|
sc_trace(tf,the_ht_tunnel->the_decoder0_l2->lk_lctl_cd,"DECODER.lk_lctl_cd");
|
| 740 |
|
|
sc_trace(tf,the_ht_tunnel->the_decoder0_l2->lk_hctl_cd,"DECODER.lk_hctl_cd");
|
| 741 |
|
|
sc_trace(tf,the_ht_tunnel->the_decoder0_l2->cd_available_ro,"DECODER.cd_available_ro");
|
| 742 |
|
|
sc_trace(tf,the_ht_tunnel->the_decoder0_l2->cd_packet_ro,"DECODER.cd_packet_ro");
|
| 743 |
|
|
|
| 744 |
|
|
#ifdef RETRY_MODE_ENABLED
|
| 745 |
|
|
sc_trace(tf,the_ht_tunnel->the_link0_l2->cd_initiate_retry_disconnect,"LINK.cd_initiate_retry_disconnect");
|
| 746 |
|
|
sc_trace(tf,the_ht_tunnel->the_link0_l2->lk_initiate_retry_disconnect,"LINK.lk_initiate_retry_disconnect");
|
| 747 |
|
|
#endif
|
| 748 |
|
|
sc_trace(tf,the_ht_tunnel->the_link0_l2->cd_initiate_nonretry_disconnect_lk,"LINK.cd_initiate_nonretry_disconnect_lk");
|
| 749 |
|
|
sc_trace(tf,the_ht_tunnel->the_link0_l2->tx_crc_count,"LINK.tx_crc_count");
|
| 750 |
|
|
|
| 751 |
|
|
sc_trace(tf,the_ht_tunnel->the_csr_l2->csr_unit_id,"CSR.csr_unit_id");
|
| 752 |
|
|
sc_trace(tf,the_ht_tunnel->the_csr_l2->csr_bar[0],"CSR.csr_bar0");
|
| 753 |
|
|
sc_trace(tf,the_ht_tunnel->the_csr_l2->csr_io_space_enable,"CSR.csr_io_space_enable");
|
| 754 |
|
|
sc_trace(tf,the_ht_tunnel->the_csr_l2->csr_memory_space_enable,"CSR.csr_memory_space_enable");
|
| 755 |
|
|
sc_trace(tf,the_ht_tunnel->the_csr_l2->csr_request_databuffer0_access_ui,"CSR.csr_request_databuffer0_access_ui");
|
| 756 |
|
|
sc_trace(tf,the_ht_tunnel->the_csr_l2->ro0_available_csr,"CSR.ro0_available_csr");
|
| 757 |
|
|
sc_trace(tf,the_ht_tunnel->the_csr_l2->csr_ack_ro0,"CSR.csr_ack_ro0");
|
| 758 |
|
|
#ifdef RETRY_MODE_ENABLED
|
| 759 |
|
|
sc_trace(tf,the_ht_tunnel->the_csr_l2->csr_retry0,"CSR.csr_retry0");
|
| 760 |
|
|
sc_trace(tf,the_ht_tunnel->the_csr_l2->csr_retry1,"CSR.csr_retry1");
|
| 761 |
|
|
#endif
|
| 762 |
|
|
sc_trace(tf,the_ht_tunnel->the_csr_l2->csr_erase_db0,"CSR.csr_erase_db0");
|
| 763 |
|
|
sc_trace(tf,the_ht_tunnel->the_csr_l2->csr_read_db0,"CSR.csr_read_db0");
|
| 764 |
|
|
sc_trace(tf,the_ht_tunnel->the_csr_l2->csr_address_db0,"CSR.csr_address_db0");
|
| 765 |
|
|
sc_trace(tf,the_ht_tunnel->the_csr_l2->csr_vctype_db0,"CSR.csr_vctype_db0");
|
| 766 |
|
|
|
| 767 |
|
|
sc_trace(tf,the_ht_tunnel->the_csr_l2->csr_extented_ctl_lk0,"CSR.csr_extented_ctl_lk0");
|
| 768 |
|
|
sc_trace(tf,the_ht_tunnel->the_csr_l2->csr_available_fc0,"CSR.csr_available_fc0");
|
| 769 |
|
|
sc_trace(tf,the_ht_tunnel->the_csr_l2->csr_dword_fc0,"CSR.csr_dword_fc0");
|
| 770 |
|
|
sc_trace(tf,the_ht_tunnel->the_csr_l2->fc0_ack_csr,"CSR.fc0_ack_csr");
|
| 771 |
|
|
|
| 772 |
|
|
sc_trace(tf,the_ht_tunnel->the_csr_l2->csr_extented_ctl_lk1,"CSR.csr_extented_ctl_lk1");
|
| 773 |
|
|
sc_trace(tf,the_ht_tunnel->the_csr_l2->csr_available_fc1,"CSR.csr_available_fc1");
|
| 774 |
|
|
sc_trace(tf,the_ht_tunnel->the_csr_l2->csr_dword_fc1,"CSR.csr_dword_fc1");
|
| 775 |
|
|
sc_trace(tf,the_ht_tunnel->the_csr_l2->fc1_ack_csr,"CSR.fc1_ack_csr");
|
| 776 |
|
|
|
| 777 |
|
|
|
| 778 |
|
|
sc_trace(tf,the_ht_tunnel->the_userinterface_l2->ro0_available_ui,"UI.ro0_available_ui");
|
| 779 |
|
|
sc_trace(tf,the_ht_tunnel->the_userinterface_l2->ro0_packet_ui,"UI.ro0_packet_ui");
|
| 780 |
|
|
sc_trace(tf,the_ht_tunnel->the_userinterface_l2->ui_ack_ro0,"UI.ui_ack_ro0");
|
| 781 |
|
|
sc_trace(tf,the_ht_tunnel->the_userinterface_l2->ui_available_fc0,"UI.ui_available_fc0");
|
| 782 |
|
|
sc_trace(tf,the_ht_tunnel->the_userinterface_l2->fc0_consume_data_ui,"UI.fc0_consume_data_ui");
|
| 783 |
|
|
|
| 784 |
|
|
sc_trace(tf,the_ht_tunnel->the_userinterface_l2->ui_read_db0,"UI.ui_read_db0");
|
| 785 |
|
|
sc_trace(tf,the_ht_tunnel->the_userinterface_l2->ui_erase_db0,"UI.ui_erase_db0");
|
| 786 |
|
|
sc_trace(tf,the_ht_tunnel->the_userinterface_l2->ui_address_db0,"UI.ui_address_db0");
|
| 787 |
|
|
sc_trace(tf,the_ht_tunnel->the_userinterface_l2->ui_vctype_db0,"UI.ui_vctype_db0");
|
| 788 |
|
|
sc_trace(tf,the_ht_tunnel->the_userinterface_l2->db0_data_ui,"UI.db0_data_ui");
|
| 789 |
|
|
|
| 790 |
|
|
#ifdef RETRY_MODE_ENABLED
|
| 791 |
|
|
sc_trace(tf,the_ht_tunnel->the_flow_control0_l2->the_history_buffer->history_playback_done,"HISTORY.history_playback_done");
|
| 792 |
|
|
sc_trace(tf,the_ht_tunnel->the_flow_control0_l2->the_history_buffer->begin_history_playback,"HISTORY.begin_history_playback");
|
| 793 |
|
|
sc_trace(tf,the_ht_tunnel->the_flow_control0_l2->the_history_buffer->stop_history_playback,"HISTORY.stop_history_playback");
|
| 794 |
|
|
sc_trace(tf,the_ht_tunnel->the_flow_control0_l2->the_history_buffer->history_playback_ready,"HISTORY.history_playback_ready");
|
| 795 |
|
|
sc_trace(tf,the_ht_tunnel->the_flow_control0_l2->the_history_buffer->consume_history,"HISTORY.consume_history");
|
| 796 |
|
|
sc_trace(tf,the_ht_tunnel->the_flow_control0_l2->the_history_buffer->room_available_in_history,"HISTORY.room_available_in_history");
|
| 797 |
|
|
sc_trace(tf,the_ht_tunnel->the_flow_control0_l2->the_history_buffer->add_to_history,"HISTORY.add_to_history");
|
| 798 |
|
|
sc_trace(tf,the_ht_tunnel->the_flow_control0_l2->the_history_buffer->new_history_entry,"HISTORY.new_history_entry");
|
| 799 |
|
|
sc_trace(tf,the_ht_tunnel->the_flow_control0_l2->the_history_buffer->new_history_entry_size_m1,"HISTORY.new_history_entry_size_m1");
|
| 800 |
|
|
sc_trace(tf,the_ht_tunnel->the_flow_control0_l2->the_history_buffer->fc_dword_lk,"HISTORY.fc_dword_lk");
|
| 801 |
|
|
sc_trace(tf,the_ht_tunnel->the_flow_control0_l2->the_history_buffer->nop_received,"HISTORY.nop_received");
|
| 802 |
|
|
sc_trace(tf,the_ht_tunnel->the_flow_control0_l2->the_history_buffer->ack_value,"HISTORY.ack_value");
|
| 803 |
|
|
#endif
|
| 804 |
|
|
|
| 805 |
|
|
sc_trace(tf,the_ht_tunnel->the_errorhandler0_l2->ro_available_fwd,"ERROR.ro_available_fwd");
|
| 806 |
|
|
sc_trace(tf,the_ht_tunnel->the_errorhandler0_l2->ro_packet_fwd,"ERROR.ro_packet_fwd");
|
| 807 |
|
|
sc_trace(tf,the_ht_tunnel->the_errorhandler0_l2->eh_ack_ro,"ERROR.eh_ack_ro");
|
| 808 |
|
|
sc_trace(tf,the_ht_tunnel->the_errorhandler0_l2->eh_available_fc,"ERROR.eh_available_fc");
|
| 809 |
|
|
|
| 810 |
|
|
sc_trace(tf,the_ht_tunnel->the_flow_control0_l2->the_user_fifo->fifo_user_available,
|
| 811 |
|
|
"FIFO.fifo_user_available");
|
| 812 |
|
|
sc_trace(tf,the_ht_tunnel->the_flow_control0_l2->the_user_fifo->ui_available_fc,
|
| 813 |
|
|
"FIFO.ui_available_fc");
|
| 814 |
|
|
sc_trace(tf,the_ht_tunnel->the_flow_control0_l2->the_user_fifo->consume_user_fifo,
|
| 815 |
|
|
"FIFO.consume_user_fifo");
|
| 816 |
|
|
sc_trace(tf,the_ht_tunnel->the_flow_control0_l2->the_user_fifo->buffer_count_posted,
|
| 817 |
|
|
"FIFO.buffer_count_posted");
|
| 818 |
|
|
sc_trace(tf,the_ht_tunnel->the_flow_control0_l2->the_user_fifo->buffer_count_nposted,
|
| 819 |
|
|
"FIFO.buffer_count_nposted");
|
| 820 |
|
|
|
| 821 |
|
|
sc_trace(tf,the_ht_tunnel->the_reordering0_l2->ro_available_fwd,"REORDERING.ro_available_fwd");
|
| 822 |
|
|
sc_trace(tf,the_ht_tunnel->the_reordering0_l2->ro_packet_fwd,"REORDERING.ro_packet_fwd");
|
| 823 |
|
|
|
| 824 |
|
|
|
| 825 |
|
|
/*sc_trace(tf,the_ht_tunnel->the_flow_control1_l2->eh_available_fc,"FLOW1.eh_available_fc");
|
| 826 |
|
|
sc_trace(tf,the_ht_tunnel->the_flow_control1_l2->ui_available_fc,"FLOW1.ui_available_fc");
|
| 827 |
|
|
sc_trace(tf,the_ht_tunnel->the_flow_control1_l2->csr_available_fc,"FLOW1.csr_available_fc");
|
| 828 |
|
|
sc_trace(tf,the_ht_tunnel->the_flow_control1_l2->ro_available_fwd,"FLOW1.ro_available_fwd");
|
| 829 |
|
|
sc_trace(tf,the_ht_tunnel->the_flow_control1_l2->fc_dword_lk,"FLOW1.fc_dword_lk");*/
|
| 830 |
|
|
sc_trace(tf,the_ht_tunnel->the_flow_control0_l2->lk_consume_fc,"FLOW0.lk_consume_fc");
|
| 831 |
|
|
sc_trace(tf,the_ht_tunnel->the_flow_control0_l2->fc_dword_lk,"FLOW0.fc_dword_lk");
|
| 832 |
|
|
|
| 833 |
|
|
sc_trace(tf,the_ht_tunnel->the_flow_control0_l2->ro_available_fwd,"FLOW0.ro_available_fwd");
|
| 834 |
|
|
sc_trace(tf,the_ht_tunnel->the_flow_control0_l2->ro_packet_fwd,"FLOW0.ro_packet_fwd");
|
| 835 |
|
|
sc_trace(tf,the_ht_tunnel->the_flow_control0_l2->fwd_ack_ro,"FLOW0.fwd_ack_ro");
|
| 836 |
|
|
|
| 837 |
|
|
sc_trace(tf,the_ht_tunnel->the_flow_control0_l2->eh_available_fc,"FLOW0.eh_available_fc");
|
| 838 |
|
|
sc_trace(tf,the_ht_tunnel->the_flow_control0_l2->fc_ack_eh,"FLOW0.fc_ack_eh");
|
| 839 |
|
|
|
| 840 |
|
|
sc_trace(tf,the_ht_tunnel->the_flow_control0_l2->csr_available_fc,"FLOW0.csr_available_fc");
|
| 841 |
|
|
sc_trace(tf,the_ht_tunnel->the_flow_control0_l2->fc_ack_csr,"FLOW0.fc_ack_csr");
|
| 842 |
|
|
sc_trace(tf,the_ht_tunnel->the_flow_control0_l2->csr_dword_fc,"FLOW0.csr_dword_fc");
|
| 843 |
|
|
|
| 844 |
|
|
sc_trace(tf,the_ht_tunnel->the_flow_control0_l2->fc_nop_sent,"FLOW0.fc_nop_sent");
|
| 845 |
|
|
sc_trace(tf,the_ht_tunnel->the_flow_control0_l2->db_nop_req_fc,"FLOW0.db_nop_req_fc");
|
| 846 |
|
|
sc_trace(tf,the_ht_tunnel->the_flow_control0_l2->ro_nop_req_fc,"FLOW0.ro_nop_req_fc");
|
| 847 |
|
|
|
| 848 |
|
|
#ifdef RETRY_MODE_ENABLED
|
| 849 |
|
|
sc_trace(tf,the_ht_tunnel->the_flow_control0_l2->fc_disconnect_lk,"FLOW0.fc_disconnect_lk");
|
| 850 |
|
|
sc_trace(tf,the_ht_tunnel->the_flow_control0_l2->lk_rx_connected,"FLOW0.lk_rx_connected");
|
| 851 |
|
|
#endif
|
| 852 |
|
|
|
| 853 |
|
|
//------------------------------------------
|
| 854 |
|
|
// start the simulation
|
| 855 |
|
|
//------------------------------------------
|
| 856 |
|
|
|
| 857 |
|
|
cout << "Starting simulation" << endl;
|
| 858 |
|
|
|
| 859 |
|
|
int sim_time = 1200;
|
| 860 |
|
|
|
| 861 |
|
|
sc_start(sim_time);
|
| 862 |
|
|
|
| 863 |
|
|
printf("End of simulation\n");
|
| 864 |
|
|
sc_close_vcd_trace_file(tf);
|
| 865 |
|
|
|
| 866 |
|
|
delete the_ht_tunnel;
|
| 867 |
|
|
return 0;
|
| 868 |
|
|
}
|
| 869 |
|
|
|
| 870 |
|
|
#endif
|
