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[/] [ht_tunnel/] [trunk/] [bench/] [vc_ht_tunnel_l1_tb/] [main.h] - Blame information for rev 19

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1 2 acastong
//main.h for vc_ht_tunnel_l1 testbench in ModelSim
2
 
3
/* ***** BEGIN LICENSE BLOCK *****
4
 * Version: MPL 1.1
5
 *
6
 * The contents of this file are subject to the Mozilla Public License Version
7
 * 1.1 (the "License"); you may not use this file except in compliance with
8
 * the License. You may obtain a copy of the License at
9
 * http://www.mozilla.org/MPL/
10
 *
11
 * Software distributed under the License is distributed on an "AS IS" basis,
12
 * WITHOUT WARRANTY OF ANY KIND, either express or implied. See the License
13
 * for the specific language governing rights and limitations under the
14
 * License.
15
 *
16
 * The Original Code is HyperTransport Tunnel IP Core.
17
 *
18
 * The Initial Developer of the Original Code is
19
 * Ecole Polytechnique de Montreal.
20
 * Portions created by the Initial Developer are Copyright (C) 2005
21
 * the Initial Developer. All Rights Reserved.
22
 *
23
 * Contributor(s):
24
 *   Ami Castonguay <acastong@grm.polymtl.ca>
25
 *
26
 * Alternatively, the contents of this file may be used under the terms
27
 * of the Polytechnique HyperTransport Tunnel IP Core Source Code License
28
 * (the  "PHTICSCL License", see the file PHTICSCL.txt), in which case the
29
 * provisions of PHTICSCL License are applicable instead of those
30
 * above. If you wish to allow use of your version of this file only
31
 * under the terms of the PHTICSCL License and not to allow others to use
32
 * your version of this file under the MPL, indicate your decision by
33
 * deleting the provisions above and replace them with the notice and
34
 * other provisions required by the PHTICSCL License. If you do not delete
35
 * the provisions above, a recipient may use your version of this file
36
 * under either the MPL or the PHTICSCL License."
37
 *
38
 * ***** END LICENSE BLOCK ***** */
39
 
40
#ifndef MTI2_SYSTEMC
41
#error The file main.h must not be included in a normal compilation
42
#endif
43
 
44
/**
45
        @file main.h
46
        @author Ami Castonguay
47
        @description This file is to be used exclusively to do simulation with
48
                ModelSim.  It should not be included in normal compilation.
49
*/
50
 
51 13 acastong
#include "../../rtl/systemc/core_synth/synth_datatypes.h"
52 2 acastong
 
53
#include <iostream>
54
#include <string>
55
#include <sstream>
56
#include <iomanip>
57
 
58 13 acastong
#include "../../rtl/systemc/vc_ht_tunnel_l1/vc_ht_tunnel_l1.h"
59
#include "../../rtl/systemc/flow_control_l2/user_fifo_l3.h"
60
#include "../../rtl/systemc/flow_control_l2/history_buffer_l3.h"
61 2 acastong
#include "vc_ht_tunnel_l1_tb.h"
62
 
63
using namespace std;
64
 
65
///Top simulation module for Tunnel simulation with ModelSim
66
class top : public sc_module{
67
 
68
public:
69
 
70
        sc_clock clk;
71
 
72
        //------------------------------------------
73
        // Instanciation de FLOW CONTROL
74
        //------------------------------------------
75
        vc_ht_tunnel_l1 the_ht_tunnel;
76
        vc_ht_tunnel_l1_tb tb;
77
 
78
        // ***************************************************
79
        //  Signals
80
        // ***************************************************  
81
        /// The Clock, LDTSTOP and reset signals
82
        sc_signal<bool>                 resetx;
83
        sc_signal<bool>                 pwrok;
84
        sc_signal<bool>                 ldtstopx;
85
 
86
        //Link0 signals
87
        //sc_signal<bool >              receive_clk0;
88
        sc_signal<bool>                                         phy0_available_lk0;
89
        sc_signal<sc_bv<CAD_IN_DEPTH> >         phy0_ctl_lk0;
90
        sc_signal<sc_bv<CAD_IN_DEPTH> >         phy0_cad_lk0[CAD_IN_WIDTH];
91
 
92
        //sc_signal< bool >     transmit_clk0;
93
        sc_signal<sc_bv<CAD_OUT_DEPTH> >        lk0_ctl_phy0;
94
        sc_signal<sc_bv<CAD_OUT_DEPTH> >        lk0_cad_phy0[CAD_OUT_WIDTH];
95
        sc_signal<bool>                                         phy0_consume_lk0;
96
 
97
        sc_signal<bool>                 lk0_disable_drivers_phy0;
98
        sc_signal<bool>                 lk0_disable_receivers_phy0;
99
 
100
        //Link1 signals
101
        //sc_signal<bool >              receive_clk1;
102
        sc_signal<bool>                                         phy1_available_lk1;
103
        sc_signal<sc_bv<CAD_IN_DEPTH> >         phy1_ctl_lk1;
104
        sc_signal<sc_bv<CAD_IN_DEPTH> >         phy1_cad_lk1[CAD_IN_WIDTH];
105
 
106
        //sc_signal< bool >     transmit_clk0;
107
        sc_signal<sc_bv<CAD_OUT_DEPTH> >        lk1_ctl_phy1;
108
        sc_signal<sc_bv<CAD_OUT_DEPTH> >        lk1_cad_phy1[CAD_OUT_WIDTH];
109
        sc_signal<bool>                                         phy1_consume_lk1;
110
 
111
        sc_signal<bool>                 lk1_disable_drivers_phy1;
112
        sc_signal<bool>                 lk1_disable_receivers_phy1;
113
 
114
        /////////////////////////////////////////////////////
115
        // Interface to UserInterface memory - synchronous
116
        /////////////////////////////////////////////////////
117
 
118
        sc_signal<bool> ui_memory_write0;
119
        sc_signal<bool> ui_memory_write1;//20
120
        sc_signal<sc_bv<USER_MEMORY_ADDRESS_WIDTH> > ui_memory_write_address;
121
        sc_signal<sc_bv<32> > ui_memory_write_data;
122
 
123
        sc_signal<sc_bv<USER_MEMORY_ADDRESS_WIDTH> > ui_memory_read_address0;
124
        sc_signal<sc_bv<USER_MEMORY_ADDRESS_WIDTH> > ui_memory_read_address1;
125
        sc_signal<sc_bv<32> > ui_memory_read_data0;
126
        sc_signal<sc_bv<32> > ui_memory_read_data1;
127
 
128
#ifdef RETRY_MODE_ENABLED
129
        //////////////////////////////////////////
130
        //      Memory interface flowcontrol0- synchronous
131
        /////////////////////////////////////////
132
        sc_signal<bool> history_memory_write0;
133
        sc_signal<sc_uint<LOG2_HISTORY_MEMORY_SIZE> > history_memory_write_address0;
134
        sc_signal<sc_bv<32> > history_memory_write_data0;
135
        sc_signal<sc_uint<LOG2_HISTORY_MEMORY_SIZE> > history_memory_read_address0;//30
136
        sc_signal<sc_bv<32> > history_memory_output0;
137
 
138
        //////////////////////////////////////////
139
        //      Memory interface flowcontrol1- synchronous
140
        /////////////////////////////////////////
141
        sc_signal<bool> history_memory_write1;
142
        sc_signal<sc_uint<LOG2_HISTORY_MEMORY_SIZE> > history_memory_write_address1;
143
        sc_signal<sc_bv<32> > history_memory_write_data1;
144
        sc_signal<sc_uint<LOG2_HISTORY_MEMORY_SIZE> > history_memory_read_address1;
145
        sc_signal<sc_bv<32> > history_memory_output1;
146
 
147
#endif
148
 
149
        ////////////////////////////////////
150
        // Memory interface databuffer0 - synchronous
151
        ////////////////////////////////////
152
 
153
        sc_signal<bool> memory_write0;
154
        sc_signal<sc_uint<2> > memory_write_address_vc0;
155
        sc_signal<sc_uint<BUFFERS_ADDRESS_WIDTH> > memory_write_address_buffer0;
156 13 acastong
        sc_signal<sc_uint<4> > memory_write_address_pos0;//40
157 2 acastong
        sc_signal<sc_bv<32> > memory_write_data0;
158
 
159
        sc_signal<sc_uint<2> > memory_read_address_vc0[2];
160
        sc_signal<sc_uint<BUFFERS_ADDRESS_WIDTH> >memory_read_address_buffer0[2];
161 13 acastong
        sc_signal<sc_uint<4> > memory_read_address_pos0[2];//50
162 2 acastong
 
163
        sc_signal<sc_bv<32> > memory_output0[2];
164
 
165
        //////////////////////////////////////
166
        // Memory interface databuffer1 - synchronous
167
        ////////////////////////////////////
168
 
169
        sc_signal<bool> memory_write1;
170
        sc_signal<sc_uint<2> > memory_write_address_vc1;
171
        sc_signal<sc_uint<BUFFERS_ADDRESS_WIDTH> > memory_write_address_buffer1;
172 13 acastong
        sc_signal<sc_uint<4> > memory_write_address_pos1;
173 2 acastong
        sc_signal<sc_bv<32> > memory_write_data1;
174
 
175
        sc_signal<sc_uint<2> > memory_read_address_vc1[2];
176
        sc_signal<sc_uint<BUFFERS_ADDRESS_WIDTH> >memory_read_address_buffer1[2];
177 13 acastong
        sc_signal<sc_uint<4> > memory_read_address_pos1[2];
178 2 acastong
 
179
        sc_signal<sc_bv<32> > memory_output1[2];
180
 
181
 
182
        //************************************
183
        // Reset generated by link
184
        //************************************
185
        //sc_signal<bool>               warmrstx;
186
        //sc_signal<bool>               coldrstx;
187
 
188
        //sc_signal<bool>               dummy_warmrstx;
189
        //sc_signal<bool>               dummy_coldrstx;
190
 
191
        //******************************************
192
        //                      Signals to User
193
        //******************************************
194
        //------------------------------------------
195
        // Signals to send received packets to User
196
        //------------------------------------------
197
 
198
 
199
        /**The actual control/data packet to the user*/
200
        sc_signal<sc_bv<64> >           ui_packet_usr;
201
 
202
        /**The virtual channel of the ctl/data packet*/
203
        sc_signal<VirtualChannel>       ui_vc_usr;
204
 
205
        /**The side from which came the packet*/
206
        sc_signal< bool >                       ui_side_usr;
207
 
208
        /**If the packet is a direct_route packet - only valid for
209
           requests (posted and non-posted) */
210
        sc_signal<bool>                 ui_directroute_usr;
211
 
212
        /**If this is the last part of the packet*/
213
        sc_signal< bool >                       ui_eop_usr;
214
 
215
        /**If there is another packet available*/
216
        sc_signal< bool >                       ui_available_usr;
217
 
218
        /**If what is read is 64 bits or 32 bits*/
219
        sc_signal< bool >                       ui_output_64bits_usr;
220
 
221
        /**To allow the user to consume the packets*/
222
        sc_signal< bool >                       usr_consume_ui;
223
 
224
 
225
        //------------------------------------------
226
        // Signals to allow the User to send packets
227
        //------------------------------------------
228
 
229
        /**The actual control/data packet from the user*/
230
        sc_signal<sc_bv<64> >           usr_packet_ui;
231
 
232
        /**If there is another packet available*/
233
        sc_signal< bool >                       usr_available_ui;
234
 
235
        /**
236
        The side to send the packet if it is a response
237
        This bit is ignored if the packet is not a response
238
        since the side to send a request is determined automatically
239
        taking in acount DirectRoute functionnality.
240
        */
241
        sc_signal< bool >                       usr_side_ui;
242
 
243
        /**If the packet is trying to be sent to a VC that is full,
244
        We let the user know that he is doing something illegal
245
        Packet is not consumed if this is 1
246
        */
247
        //sc_signal < bool >            ui_invalid_usr;
248
 
249
        /**Which what type of ctl packets can be sent to side0*/
250
        sc_signal<sc_bv<6> >            ui_freevc0_usr;
251
        /**Which what type of ctl packets can be sent to side0*/
252
        sc_signal<sc_bv<6> >            ui_freevc1_usr;
253
 
254
        //-----------------------------------------------
255
        // Content of CSR that might be useful to user
256
        //-----------------------------------------------
257
        /** Signals table containing all 40 bits Base Addresses from BARs implemented */
258
        sc_signal<sc_bv<40> > csr_bar[NbRegsBars];
259
        /** Signal from register Interface->Command->csr_unit_id */
260
        sc_signal<sc_bv<5> > csr_unit_id;
261
 
262
        //------------------------------------------
263
        // Signals to affect CSR
264
        //------------------------------------------
265
        sc_signal<bool> usr_receivedResponseError_csr;
266
 
267
        //--------------------------------------------------------
268
        // Interface for having registers outside CSR if necessary
269
        //--------------------------------------------------------
270
 
271
        ///Signals to allow external registers with minimal logic
272
        /**
273
                Connect usr_read_data_csr to zeroes if not used!
274
        */
275
        //@{
276
        sc_signal<sc_uint<6> >  csr_read_addr_usr;
277
        sc_signal<sc_bv<32> >   usr_read_data_csr;
278
        sc_signal<bool >        csr_write_usr;
279
        sc_signal<sc_uint<6> >  csr_write_addr_usr;
280
        sc_signal<sc_bv<32> >   csr_write_data_usr;
281
        /**Every bit is a byte mask for the dword to write*/
282
        sc_signal<sc_bv<4> >    csr_write_mask_usr;
283
        //@}
284
 
285
 
286
 
287
 
288
        top(sc_module_name name) : sc_module(name),
289
                        clk("CLOCK",10,SC_NS,0.5),the_ht_tunnel("dut"),
290
                        tb("tb")
291
        {
292
 
293
                // ***************************************************
294
                //  LINKING DUT
295
                // ***************************************************  
296
                the_ht_tunnel.clk(clk);
297
                the_ht_tunnel.resetx(resetx);
298
                the_ht_tunnel.pwrok(pwrok);
299
                the_ht_tunnel.ldtstopx(ldtstopx);
300
 
301
                the_ht_tunnel.phy0_available_lk0(phy0_available_lk0);
302
                the_ht_tunnel.phy0_ctl_lk0(phy0_ctl_lk0);
303
 
304
                for(int n = 0; n < CAD_IN_WIDTH; n++){
305
                        the_ht_tunnel.phy0_cad_lk0[n](phy0_cad_lk0[n]);
306
                        the_ht_tunnel.lk0_cad_phy0[n](lk0_cad_phy0[n]);
307
                        the_ht_tunnel.phy1_cad_lk1[n](phy1_cad_lk1[n]);
308
                        the_ht_tunnel.lk1_cad_phy1[n](lk1_cad_phy1[n]);
309
                }
310
 
311
                the_ht_tunnel.lk0_ctl_phy0(lk0_ctl_phy0);
312
                the_ht_tunnel.phy0_consume_lk0(phy0_consume_lk0);
313
 
314
                the_ht_tunnel.lk0_disable_drivers_phy0(lk0_disable_drivers_phy0);
315
                the_ht_tunnel.lk0_disable_receivers_phy0(lk0_disable_receivers_phy0);
316
 
317
                the_ht_tunnel.phy1_available_lk1(phy1_available_lk1);
318
                the_ht_tunnel.phy1_ctl_lk1(phy1_ctl_lk1);
319
 
320
                the_ht_tunnel.lk1_ctl_phy1(lk1_ctl_phy1);
321
                the_ht_tunnel.phy1_consume_lk1(phy1_consume_lk1);
322
 
323
                the_ht_tunnel.lk1_disable_drivers_phy1(lk1_disable_drivers_phy1);
324
                the_ht_tunnel.lk1_disable_receivers_phy1(lk1_disable_receivers_phy1);
325
 
326
                the_ht_tunnel.ui_memory_write0(ui_memory_write0);
327
                the_ht_tunnel.ui_memory_write1(ui_memory_write1);//20
328
                the_ht_tunnel.ui_memory_write_address(ui_memory_write_address);
329
                the_ht_tunnel.ui_memory_write_data(ui_memory_write_data);
330
 
331
                the_ht_tunnel.ui_memory_read_address0(ui_memory_read_address0);
332
                the_ht_tunnel.ui_memory_read_address1(ui_memory_read_address1);
333
                the_ht_tunnel.ui_memory_read_data0(ui_memory_read_data0);
334
                the_ht_tunnel.ui_memory_read_data1(ui_memory_read_data1);
335
 
336
        #ifdef RETRY_MODE_ENABLED
337
                the_ht_tunnel.history_memory_write0(history_memory_write0);
338
                the_ht_tunnel.history_memory_write_address0(history_memory_write_address0);
339
                the_ht_tunnel.history_memory_write_data0(history_memory_write_data0);
340
                the_ht_tunnel.history_memory_read_address0(history_memory_read_address0);//30
341
                the_ht_tunnel.history_memory_output0(history_memory_output0);
342
 
343
                the_ht_tunnel.history_memory_write1(history_memory_write1);
344
                the_ht_tunnel.history_memory_write_address1(history_memory_write_address1);
345
                the_ht_tunnel.history_memory_write_data1(history_memory_write_data1);
346
                the_ht_tunnel.history_memory_read_address1(history_memory_read_address1);
347
                the_ht_tunnel.history_memory_output1(history_memory_output1);
348
 
349
        #endif
350
 
351
 
352
                the_ht_tunnel.memory_write0(memory_write0);
353
                the_ht_tunnel.memory_write_address_vc0(memory_write_address_vc0);
354
                the_ht_tunnel.memory_write_address_buffer0(memory_write_address_buffer0);
355
                the_ht_tunnel.memory_write_address_pos0(memory_write_address_pos0);//40
356
                the_ht_tunnel.memory_write_data0(memory_write_data0);
357
 
358
                the_ht_tunnel.memory_read_address_vc0[0](memory_read_address_vc0[0]);
359
                the_ht_tunnel.memory_read_address_buffer0[0](memory_read_address_buffer0[0]);
360
                the_ht_tunnel.memory_read_address_pos0[0](memory_read_address_pos0[0]);//50
361
                the_ht_tunnel.memory_output0[0](memory_output0[0]);
362
 
363
                the_ht_tunnel.memory_read_address_vc0[1](memory_read_address_vc0[1]);
364
                the_ht_tunnel.memory_read_address_buffer0[1](memory_read_address_buffer0[1]);
365
                the_ht_tunnel.memory_read_address_pos0[1](memory_read_address_pos0[1]);//50
366
                the_ht_tunnel.memory_output0[1](memory_output0[1]);
367
 
368
 
369
                the_ht_tunnel.memory_write1(memory_write1);
370
                the_ht_tunnel.memory_write_address_vc1(memory_write_address_vc1);
371
                the_ht_tunnel.memory_write_address_buffer1(memory_write_address_buffer1);
372
                the_ht_tunnel.memory_write_address_pos1(memory_write_address_pos1);
373
                the_ht_tunnel.memory_write_data1(memory_write_data1);
374
 
375
                the_ht_tunnel.memory_read_address_vc1[0](memory_read_address_vc1[0]);
376
                the_ht_tunnel.memory_read_address_buffer1[0](memory_read_address_buffer1[0]);
377
                the_ht_tunnel.memory_read_address_pos1[0](memory_read_address_pos1[0]);
378
                the_ht_tunnel.memory_output1[0](memory_output1[0]);
379
 
380
                the_ht_tunnel.memory_read_address_vc1[1](memory_read_address_vc1[1]);
381
                the_ht_tunnel.memory_read_address_buffer1[1](memory_read_address_buffer1[1]);
382
                the_ht_tunnel.memory_read_address_pos1[1](memory_read_address_pos1[1]);
383
                the_ht_tunnel.memory_output1[1](memory_output1[1]);
384
 
385
 
386
                the_ht_tunnel.ui_packet_usr(ui_packet_usr);
387
                the_ht_tunnel.ui_vc_usr(ui_vc_usr);
388
                the_ht_tunnel.ui_side_usr(ui_side_usr);
389
                the_ht_tunnel.ui_directroute_usr(ui_directroute_usr);
390
                the_ht_tunnel.ui_eop_usr(ui_eop_usr);
391
                the_ht_tunnel.ui_available_usr(ui_available_usr);
392
                the_ht_tunnel.ui_output_64bits_usr(ui_output_64bits_usr);
393
                the_ht_tunnel.usr_consume_ui(usr_consume_ui);
394
                the_ht_tunnel.usr_packet_ui(usr_packet_ui);
395
                the_ht_tunnel.usr_available_ui(usr_available_ui);
396
                the_ht_tunnel.usr_side_ui(usr_side_ui);
397
                the_ht_tunnel.ui_freevc0_usr(ui_freevc0_usr);
398
                the_ht_tunnel.ui_freevc1_usr(ui_freevc1_usr);
399
                for(int n = 0; n < NbRegsBars; n++)
400
                        the_ht_tunnel.csr_bar[n](csr_bar[n]);
401
                the_ht_tunnel.csr_unit_id(csr_unit_id);
402
                the_ht_tunnel.usr_receivedResponseError_csr(usr_receivedResponseError_csr);
403
 
404
                the_ht_tunnel.csr_read_addr_usr(csr_read_addr_usr);
405
                the_ht_tunnel.usr_read_data_csr(usr_read_data_csr);
406
                the_ht_tunnel.csr_write_usr(csr_write_usr);
407
                the_ht_tunnel.csr_write_addr_usr(csr_write_addr_usr);
408
                the_ht_tunnel.csr_write_data_usr(csr_write_data_usr);
409
                the_ht_tunnel.csr_write_mask_usr(csr_write_mask_usr);
410
 
411
                // ***************************************************
412
                //  LINKING TB
413
                // ***************************************************  
414
 
415
                tb.clk(clk);
416
                tb.resetx(resetx);
417
                tb.pwrok(pwrok);
418
                tb.ldtstopx(ldtstopx);
419
 
420
                tb.phy0_available_lk0(phy0_available_lk0);
421
                tb.phy0_ctl_lk0(phy0_ctl_lk0);
422
 
423
                for(int n = 0; n < CAD_IN_WIDTH; n++){
424
                        tb.phy0_cad_lk0[n](phy0_cad_lk0[n]);
425
                        tb.lk0_cad_phy0[n](lk0_cad_phy0[n]);
426
                        tb.phy1_cad_lk1[n](phy1_cad_lk1[n]);
427
                        tb.lk1_cad_phy1[n](lk1_cad_phy1[n]);
428
                }
429
 
430
                tb.lk0_ctl_phy0(lk0_ctl_phy0);
431
                tb.phy0_consume_lk0(phy0_consume_lk0);
432
 
433
                tb.lk0_disable_drivers_phy0(lk0_disable_drivers_phy0);
434
                tb.lk0_disable_receivers_phy0(lk0_disable_receivers_phy0);
435
 
436
                tb.phy1_available_lk1(phy1_available_lk1);
437
                tb.phy1_ctl_lk1(phy1_ctl_lk1);
438
 
439
                tb.lk1_ctl_phy1(lk1_ctl_phy1);
440
                tb.phy1_consume_lk1(phy1_consume_lk1);
441
 
442
                tb.lk1_disable_drivers_phy1(lk1_disable_drivers_phy1);
443
                tb.lk1_disable_receivers_phy1(lk1_disable_receivers_phy1);
444
 
445
                tb.ui_memory_write0(ui_memory_write0);
446
                tb.ui_memory_write1(ui_memory_write1);//20
447
                tb.ui_memory_write_address(ui_memory_write_address);
448
                tb.ui_memory_write_data(ui_memory_write_data);
449
 
450
                tb.ui_memory_read_address0(ui_memory_read_address0);
451
                tb.ui_memory_read_address1(ui_memory_read_address1);
452
                tb.ui_memory_read_data0(ui_memory_read_data0);
453
                tb.ui_memory_read_data1(ui_memory_read_data1);
454
 
455
        #ifdef RETRY_MODE_ENABLED
456
                tb.history_memory_write0(history_memory_write0);
457
                tb.history_memory_write_address0(history_memory_write_address0);
458
                tb.history_memory_write_data0(history_memory_write_data0);
459
                tb.history_memory_read_address0(history_memory_read_address0);//30
460
                tb.history_memory_output0(history_memory_output0);
461
 
462
                tb.history_memory_write1(history_memory_write1);
463
                tb.history_memory_write_address1(history_memory_write_address1);
464
                tb.history_memory_write_data1(history_memory_write_data1);
465
                tb.history_memory_read_address1(history_memory_read_address1);
466
                tb.history_memory_output1(history_memory_output1);
467
 
468
        #endif
469
 
470
 
471
                tb.memory_write0(memory_write0);
472
                tb.memory_write_address_vc0(memory_write_address_vc0);
473
                tb.memory_write_address_buffer0(memory_write_address_buffer0);
474
                tb.memory_write_address_pos0(memory_write_address_pos0);//40
475
                tb.memory_write_data0(memory_write_data0);
476
 
477
                tb.memory_read_address_vc0[0](memory_read_address_vc0[0]);
478
                tb.memory_read_address_buffer0[0](memory_read_address_buffer0[0]);
479
                tb.memory_read_address_pos0[0](memory_read_address_pos0[0]);//50
480
                tb.memory_output0[0](memory_output0[0]);
481
 
482
                tb.memory_read_address_vc0[1](memory_read_address_vc0[1]);
483
                tb.memory_read_address_buffer0[1](memory_read_address_buffer0[1]);
484
                tb.memory_read_address_pos0[1](memory_read_address_pos0[1]);//50
485
                tb.memory_output0[1](memory_output0[1]);
486
 
487
 
488
                tb.memory_write1(memory_write1);
489
                tb.memory_write_address_vc1(memory_write_address_vc1);
490
                tb.memory_write_address_buffer1(memory_write_address_buffer1);
491
                tb.memory_write_address_pos1(memory_write_address_pos1);
492
                tb.memory_write_data1(memory_write_data1);
493
 
494
                tb.memory_read_address_vc1[0](memory_read_address_vc1[0]);
495
                tb.memory_read_address_buffer1[0](memory_read_address_buffer1[0]);
496
                tb.memory_read_address_pos1[0](memory_read_address_pos1[0]);
497
                tb.memory_output1[0](memory_output1[0]);
498
 
499
                tb.memory_read_address_vc1[1](memory_read_address_vc1[1]);
500
                tb.memory_read_address_buffer1[1](memory_read_address_buffer1[1]);
501
                tb.memory_read_address_pos1[1](memory_read_address_pos1[1]);
502
                tb.memory_output1[1](memory_output1[1]);
503
 
504
 
505
                tb.ui_packet_usr(ui_packet_usr);
506
                tb.ui_vc_usr(ui_vc_usr);
507
                tb.ui_side_usr(ui_side_usr);
508
                tb.ui_directroute_usr(ui_directroute_usr);
509
                tb.ui_eop_usr(ui_eop_usr);
510
                tb.ui_available_usr(ui_available_usr);
511
                tb.ui_output_64bits_usr(ui_output_64bits_usr);
512
                tb.usr_consume_ui(usr_consume_ui);
513
                tb.usr_packet_ui(usr_packet_ui);
514
                tb.usr_available_ui(usr_available_ui);
515
                tb.usr_side_ui(usr_side_ui);
516
                tb.ui_freevc0_usr(ui_freevc0_usr);
517
                tb.ui_freevc1_usr(ui_freevc1_usr);
518
                tb.usr_receivedResponseError_csr(usr_receivedResponseError_csr);
519
        }
520
};
521
 

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