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acastong |
//main.h for vc_ht_tunnel_l1 testbench in ModelSim
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/* ***** BEGIN LICENSE BLOCK *****
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* Version: MPL 1.1
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*
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* The contents of this file are subject to the Mozilla Public License Version
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* 1.1 (the "License"); you may not use this file except in compliance with
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* the License. You may obtain a copy of the License at
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* http://www.mozilla.org/MPL/
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*
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* Software distributed under the License is distributed on an "AS IS" basis,
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* WITHOUT WARRANTY OF ANY KIND, either express or implied. See the License
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* for the specific language governing rights and limitations under the
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* License.
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*
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* The Original Code is HyperTransport Tunnel IP Core.
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*
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* The Initial Developer of the Original Code is
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* Ecole Polytechnique de Montreal.
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* Portions created by the Initial Developer are Copyright (C) 2005
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* the Initial Developer. All Rights Reserved.
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*
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* Contributor(s):
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* Ami Castonguay <acastong@grm.polymtl.ca>
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*
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* Alternatively, the contents of this file may be used under the terms
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* of the Polytechnique HyperTransport Tunnel IP Core Source Code License
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* (the "PHTICSCL License", see the file PHTICSCL.txt), in which case the
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* provisions of PHTICSCL License are applicable instead of those
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* above. If you wish to allow use of your version of this file only
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* under the terms of the PHTICSCL License and not to allow others to use
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* your version of this file under the MPL, indicate your decision by
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* deleting the provisions above and replace them with the notice and
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* other provisions required by the PHTICSCL License. If you do not delete
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* the provisions above, a recipient may use your version of this file
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* under either the MPL or the PHTICSCL License."
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*
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* ***** END LICENSE BLOCK ***** */
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#ifndef MTI2_SYSTEMC
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#error The file main.h must not be included in a normal compilation
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#endif
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/**
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@file main.h
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@author Ami Castonguay
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@description This file is to be used exclusively to do simulation with
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ModelSim. It should not be included in normal compilation.
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*/
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#include "../../core_synth/synth_datatypes.h"
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#include <iostream>
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#include <string>
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#include <sstream>
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#include <iomanip>
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#include "../../vc_ht_tunnel_l1/vc_ht_tunnel_l1.h"
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#include "../../flow_control_l2/user_fifo_l3.h"
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#include "../../flow_control_l2/history_buffer_l3.h"
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#include "vc_ht_tunnel_l1_tb.h"
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using namespace std;
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///Top simulation module for Tunnel simulation with ModelSim
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class top : public sc_module{
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public:
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sc_clock clk;
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//------------------------------------------
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// Instanciation de FLOW CONTROL
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//------------------------------------------
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vc_ht_tunnel_l1 the_ht_tunnel;
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vc_ht_tunnel_l1_tb tb;
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// ***************************************************
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// Signals
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// ***************************************************
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/// The Clock, LDTSTOP and reset signals
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sc_signal<bool> resetx;
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sc_signal<bool> pwrok;
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sc_signal<bool> ldtstopx;
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//Link0 signals
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//sc_signal<bool > receive_clk0;
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sc_signal<bool> phy0_available_lk0;
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sc_signal<sc_bv<CAD_IN_DEPTH> > phy0_ctl_lk0;
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sc_signal<sc_bv<CAD_IN_DEPTH> > phy0_cad_lk0[CAD_IN_WIDTH];
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//sc_signal< bool > transmit_clk0;
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sc_signal<sc_bv<CAD_OUT_DEPTH> > lk0_ctl_phy0;
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sc_signal<sc_bv<CAD_OUT_DEPTH> > lk0_cad_phy0[CAD_OUT_WIDTH];
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sc_signal<bool> phy0_consume_lk0;
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sc_signal<bool> lk0_disable_drivers_phy0;
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sc_signal<bool> lk0_disable_receivers_phy0;
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//Link1 signals
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//sc_signal<bool > receive_clk1;
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sc_signal<bool> phy1_available_lk1;
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sc_signal<sc_bv<CAD_IN_DEPTH> > phy1_ctl_lk1;
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sc_signal<sc_bv<CAD_IN_DEPTH> > phy1_cad_lk1[CAD_IN_WIDTH];
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//sc_signal< bool > transmit_clk0;
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sc_signal<sc_bv<CAD_OUT_DEPTH> > lk1_ctl_phy1;
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sc_signal<sc_bv<CAD_OUT_DEPTH> > lk1_cad_phy1[CAD_OUT_WIDTH];
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sc_signal<bool> phy1_consume_lk1;
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sc_signal<bool> lk1_disable_drivers_phy1;
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sc_signal<bool> lk1_disable_receivers_phy1;
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/////////////////////////////////////////////////////
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// Interface to UserInterface memory - synchronous
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/////////////////////////////////////////////////////
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sc_signal<bool> ui_memory_write0;
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sc_signal<bool> ui_memory_write1;//20
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sc_signal<sc_bv<USER_MEMORY_ADDRESS_WIDTH> > ui_memory_write_address;
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sc_signal<sc_bv<32> > ui_memory_write_data;
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sc_signal<sc_bv<USER_MEMORY_ADDRESS_WIDTH> > ui_memory_read_address0;
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sc_signal<sc_bv<USER_MEMORY_ADDRESS_WIDTH> > ui_memory_read_address1;
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sc_signal<sc_bv<32> > ui_memory_read_data0;
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sc_signal<sc_bv<32> > ui_memory_read_data1;
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#ifdef RETRY_MODE_ENABLED
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//////////////////////////////////////////
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// Memory interface flowcontrol0- synchronous
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/////////////////////////////////////////
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sc_signal<bool> history_memory_write0;
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sc_signal<sc_uint<LOG2_HISTORY_MEMORY_SIZE> > history_memory_write_address0;
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sc_signal<sc_bv<32> > history_memory_write_data0;
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sc_signal<sc_uint<LOG2_HISTORY_MEMORY_SIZE> > history_memory_read_address0;//30
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sc_signal<sc_bv<32> > history_memory_output0;
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//////////////////////////////////////////
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// Memory interface flowcontrol1- synchronous
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/////////////////////////////////////////
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sc_signal<bool> history_memory_write1;
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sc_signal<sc_uint<LOG2_HISTORY_MEMORY_SIZE> > history_memory_write_address1;
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sc_signal<sc_bv<32> > history_memory_write_data1;
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sc_signal<sc_uint<LOG2_HISTORY_MEMORY_SIZE> > history_memory_read_address1;
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sc_signal<sc_bv<32> > history_memory_output1;
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#endif
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////////////////////////////////////
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// Memory interface databuffer0 - synchronous
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////////////////////////////////////
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sc_signal<bool> memory_write0;
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sc_signal<sc_uint<2> > memory_write_address_vc0;
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sc_signal<sc_uint<BUFFERS_ADDRESS_WIDTH> > memory_write_address_buffer0;
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sc_signal<sc_uint<DATABUFFER_LOG2_MAX_DATA_PER_BUFFER> > memory_write_address_pos0;//40
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sc_signal<sc_bv<32> > memory_write_data0;
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sc_signal<sc_uint<2> > memory_read_address_vc0[2];
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sc_signal<sc_uint<BUFFERS_ADDRESS_WIDTH> >memory_read_address_buffer0[2];
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sc_signal<sc_uint<DATABUFFER_LOG2_MAX_DATA_PER_BUFFER> > memory_read_address_pos0[2];//50
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sc_signal<sc_bv<32> > memory_output0[2];
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//////////////////////////////////////
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// Memory interface databuffer1 - synchronous
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////////////////////////////////////
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sc_signal<bool> memory_write1;
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sc_signal<sc_uint<2> > memory_write_address_vc1;
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sc_signal<sc_uint<BUFFERS_ADDRESS_WIDTH> > memory_write_address_buffer1;
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sc_signal<sc_uint<DATABUFFER_LOG2_MAX_DATA_PER_BUFFER> > memory_write_address_pos1;
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sc_signal<sc_bv<32> > memory_write_data1;
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sc_signal<sc_uint<2> > memory_read_address_vc1[2];
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sc_signal<sc_uint<BUFFERS_ADDRESS_WIDTH> >memory_read_address_buffer1[2];
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sc_signal<sc_uint<DATABUFFER_LOG2_MAX_DATA_PER_BUFFER> > memory_read_address_pos1[2];
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sc_signal<sc_bv<32> > memory_output1[2];
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//************************************
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// Reset generated by link
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//************************************
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//sc_signal<bool> warmrstx;
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//sc_signal<bool> coldrstx;
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//sc_signal<bool> dummy_warmrstx;
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//sc_signal<bool> dummy_coldrstx;
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//******************************************
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// Signals to User
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//******************************************
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//------------------------------------------
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// Signals to send received packets to User
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//------------------------------------------
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/**The actual control/data packet to the user*/
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sc_signal<sc_bv<64> > ui_packet_usr;
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/**The virtual channel of the ctl/data packet*/
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sc_signal<VirtualChannel> ui_vc_usr;
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/**The side from which came the packet*/
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sc_signal< bool > ui_side_usr;
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/**If the packet is a direct_route packet - only valid for
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requests (posted and non-posted) */
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sc_signal<bool> ui_directroute_usr;
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/**If this is the last part of the packet*/
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sc_signal< bool > ui_eop_usr;
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/**If there is another packet available*/
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sc_signal< bool > ui_available_usr;
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/**If what is read is 64 bits or 32 bits*/
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sc_signal< bool > ui_output_64bits_usr;
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/**To allow the user to consume the packets*/
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sc_signal< bool > usr_consume_ui;
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//------------------------------------------
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// Signals to allow the User to send packets
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//------------------------------------------
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/**The actual control/data packet from the user*/
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sc_signal<sc_bv<64> > usr_packet_ui;
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/**If there is another packet available*/
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sc_signal< bool > usr_available_ui;
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/**
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The side to send the packet if it is a response
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This bit is ignored if the packet is not a response
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since the side to send a request is determined automatically
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taking in acount DirectRoute functionnality.
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*/
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sc_signal< bool > usr_side_ui;
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/**If the packet is trying to be sent to a VC that is full,
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We let the user know that he is doing something illegal
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Packet is not consumed if this is 1
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*/
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//sc_signal < bool > ui_invalid_usr;
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/**Which what type of ctl packets can be sent to side0*/
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sc_signal<sc_bv<6> > ui_freevc0_usr;
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/**Which what type of ctl packets can be sent to side0*/
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sc_signal<sc_bv<6> > ui_freevc1_usr;
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//-----------------------------------------------
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// Content of CSR that might be useful to user
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//-----------------------------------------------
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/** Signals table containing all 40 bits Base Addresses from BARs implemented */
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sc_signal<sc_bv<40> > csr_bar[NbRegsBars];
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/** Signal from register Interface->Command->csr_unit_id */
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sc_signal<sc_bv<5> > csr_unit_id;
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//------------------------------------------
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// Signals to affect CSR
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//------------------------------------------
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sc_signal<bool> usr_receivedResponseError_csr;
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//--------------------------------------------------------
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// Interface for having registers outside CSR if necessary
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//--------------------------------------------------------
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///Signals to allow external registers with minimal logic
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/**
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Connect usr_read_data_csr to zeroes if not used!
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*/
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//@{
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sc_signal<sc_uint<6> > csr_read_addr_usr;
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sc_signal<sc_bv<32> > usr_read_data_csr;
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sc_signal<bool > csr_write_usr;
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sc_signal<sc_uint<6> > csr_write_addr_usr;
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sc_signal<sc_bv<32> > csr_write_data_usr;
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/**Every bit is a byte mask for the dword to write*/
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sc_signal<sc_bv<4> > csr_write_mask_usr;
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//@}
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top(sc_module_name name) : sc_module(name),
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clk("CLOCK",10,SC_NS,0.5),the_ht_tunnel("dut"),
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tb("tb")
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{
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// ***************************************************
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// LINKING DUT
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// ***************************************************
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the_ht_tunnel.clk(clk);
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the_ht_tunnel.resetx(resetx);
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the_ht_tunnel.pwrok(pwrok);
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the_ht_tunnel.ldtstopx(ldtstopx);
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the_ht_tunnel.phy0_available_lk0(phy0_available_lk0);
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the_ht_tunnel.phy0_ctl_lk0(phy0_ctl_lk0);
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for(int n = 0; n < CAD_IN_WIDTH; n++){
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the_ht_tunnel.phy0_cad_lk0[n](phy0_cad_lk0[n]);
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the_ht_tunnel.lk0_cad_phy0[n](lk0_cad_phy0[n]);
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the_ht_tunnel.phy1_cad_lk1[n](phy1_cad_lk1[n]);
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the_ht_tunnel.lk1_cad_phy1[n](lk1_cad_phy1[n]);
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}
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the_ht_tunnel.lk0_ctl_phy0(lk0_ctl_phy0);
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the_ht_tunnel.phy0_consume_lk0(phy0_consume_lk0);
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the_ht_tunnel.lk0_disable_drivers_phy0(lk0_disable_drivers_phy0);
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the_ht_tunnel.lk0_disable_receivers_phy0(lk0_disable_receivers_phy0);
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the_ht_tunnel.phy1_available_lk1(phy1_available_lk1);
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the_ht_tunnel.phy1_ctl_lk1(phy1_ctl_lk1);
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the_ht_tunnel.lk1_ctl_phy1(lk1_ctl_phy1);
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the_ht_tunnel.phy1_consume_lk1(phy1_consume_lk1);
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the_ht_tunnel.lk1_disable_drivers_phy1(lk1_disable_drivers_phy1);
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the_ht_tunnel.lk1_disable_receivers_phy1(lk1_disable_receivers_phy1);
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the_ht_tunnel.ui_memory_write0(ui_memory_write0);
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327 |
|
|
the_ht_tunnel.ui_memory_write1(ui_memory_write1);//20
|
328 |
|
|
the_ht_tunnel.ui_memory_write_address(ui_memory_write_address);
|
329 |
|
|
the_ht_tunnel.ui_memory_write_data(ui_memory_write_data);
|
330 |
|
|
|
331 |
|
|
the_ht_tunnel.ui_memory_read_address0(ui_memory_read_address0);
|
332 |
|
|
the_ht_tunnel.ui_memory_read_address1(ui_memory_read_address1);
|
333 |
|
|
the_ht_tunnel.ui_memory_read_data0(ui_memory_read_data0);
|
334 |
|
|
the_ht_tunnel.ui_memory_read_data1(ui_memory_read_data1);
|
335 |
|
|
|
336 |
|
|
#ifdef RETRY_MODE_ENABLED
|
337 |
|
|
the_ht_tunnel.history_memory_write0(history_memory_write0);
|
338 |
|
|
the_ht_tunnel.history_memory_write_address0(history_memory_write_address0);
|
339 |
|
|
the_ht_tunnel.history_memory_write_data0(history_memory_write_data0);
|
340 |
|
|
the_ht_tunnel.history_memory_read_address0(history_memory_read_address0);//30
|
341 |
|
|
the_ht_tunnel.history_memory_output0(history_memory_output0);
|
342 |
|
|
|
343 |
|
|
the_ht_tunnel.history_memory_write1(history_memory_write1);
|
344 |
|
|
the_ht_tunnel.history_memory_write_address1(history_memory_write_address1);
|
345 |
|
|
the_ht_tunnel.history_memory_write_data1(history_memory_write_data1);
|
346 |
|
|
the_ht_tunnel.history_memory_read_address1(history_memory_read_address1);
|
347 |
|
|
the_ht_tunnel.history_memory_output1(history_memory_output1);
|
348 |
|
|
|
349 |
|
|
#endif
|
350 |
|
|
|
351 |
|
|
|
352 |
|
|
the_ht_tunnel.memory_write0(memory_write0);
|
353 |
|
|
the_ht_tunnel.memory_write_address_vc0(memory_write_address_vc0);
|
354 |
|
|
the_ht_tunnel.memory_write_address_buffer0(memory_write_address_buffer0);
|
355 |
|
|
the_ht_tunnel.memory_write_address_pos0(memory_write_address_pos0);//40
|
356 |
|
|
the_ht_tunnel.memory_write_data0(memory_write_data0);
|
357 |
|
|
|
358 |
|
|
the_ht_tunnel.memory_read_address_vc0[0](memory_read_address_vc0[0]);
|
359 |
|
|
the_ht_tunnel.memory_read_address_buffer0[0](memory_read_address_buffer0[0]);
|
360 |
|
|
the_ht_tunnel.memory_read_address_pos0[0](memory_read_address_pos0[0]);//50
|
361 |
|
|
the_ht_tunnel.memory_output0[0](memory_output0[0]);
|
362 |
|
|
|
363 |
|
|
the_ht_tunnel.memory_read_address_vc0[1](memory_read_address_vc0[1]);
|
364 |
|
|
the_ht_tunnel.memory_read_address_buffer0[1](memory_read_address_buffer0[1]);
|
365 |
|
|
the_ht_tunnel.memory_read_address_pos0[1](memory_read_address_pos0[1]);//50
|
366 |
|
|
the_ht_tunnel.memory_output0[1](memory_output0[1]);
|
367 |
|
|
|
368 |
|
|
|
369 |
|
|
the_ht_tunnel.memory_write1(memory_write1);
|
370 |
|
|
the_ht_tunnel.memory_write_address_vc1(memory_write_address_vc1);
|
371 |
|
|
the_ht_tunnel.memory_write_address_buffer1(memory_write_address_buffer1);
|
372 |
|
|
the_ht_tunnel.memory_write_address_pos1(memory_write_address_pos1);
|
373 |
|
|
the_ht_tunnel.memory_write_data1(memory_write_data1);
|
374 |
|
|
|
375 |
|
|
the_ht_tunnel.memory_read_address_vc1[0](memory_read_address_vc1[0]);
|
376 |
|
|
the_ht_tunnel.memory_read_address_buffer1[0](memory_read_address_buffer1[0]);
|
377 |
|
|
the_ht_tunnel.memory_read_address_pos1[0](memory_read_address_pos1[0]);
|
378 |
|
|
the_ht_tunnel.memory_output1[0](memory_output1[0]);
|
379 |
|
|
|
380 |
|
|
the_ht_tunnel.memory_read_address_vc1[1](memory_read_address_vc1[1]);
|
381 |
|
|
the_ht_tunnel.memory_read_address_buffer1[1](memory_read_address_buffer1[1]);
|
382 |
|
|
the_ht_tunnel.memory_read_address_pos1[1](memory_read_address_pos1[1]);
|
383 |
|
|
the_ht_tunnel.memory_output1[1](memory_output1[1]);
|
384 |
|
|
|
385 |
|
|
|
386 |
|
|
the_ht_tunnel.ui_packet_usr(ui_packet_usr);
|
387 |
|
|
the_ht_tunnel.ui_vc_usr(ui_vc_usr);
|
388 |
|
|
the_ht_tunnel.ui_side_usr(ui_side_usr);
|
389 |
|
|
the_ht_tunnel.ui_directroute_usr(ui_directroute_usr);
|
390 |
|
|
the_ht_tunnel.ui_eop_usr(ui_eop_usr);
|
391 |
|
|
the_ht_tunnel.ui_available_usr(ui_available_usr);
|
392 |
|
|
the_ht_tunnel.ui_output_64bits_usr(ui_output_64bits_usr);
|
393 |
|
|
the_ht_tunnel.usr_consume_ui(usr_consume_ui);
|
394 |
|
|
the_ht_tunnel.usr_packet_ui(usr_packet_ui);
|
395 |
|
|
the_ht_tunnel.usr_available_ui(usr_available_ui);
|
396 |
|
|
the_ht_tunnel.usr_side_ui(usr_side_ui);
|
397 |
|
|
the_ht_tunnel.ui_freevc0_usr(ui_freevc0_usr);
|
398 |
|
|
the_ht_tunnel.ui_freevc1_usr(ui_freevc1_usr);
|
399 |
|
|
for(int n = 0; n < NbRegsBars; n++)
|
400 |
|
|
the_ht_tunnel.csr_bar[n](csr_bar[n]);
|
401 |
|
|
the_ht_tunnel.csr_unit_id(csr_unit_id);
|
402 |
|
|
the_ht_tunnel.usr_receivedResponseError_csr(usr_receivedResponseError_csr);
|
403 |
|
|
|
404 |
|
|
the_ht_tunnel.csr_read_addr_usr(csr_read_addr_usr);
|
405 |
|
|
the_ht_tunnel.usr_read_data_csr(usr_read_data_csr);
|
406 |
|
|
the_ht_tunnel.csr_write_usr(csr_write_usr);
|
407 |
|
|
the_ht_tunnel.csr_write_addr_usr(csr_write_addr_usr);
|
408 |
|
|
the_ht_tunnel.csr_write_data_usr(csr_write_data_usr);
|
409 |
|
|
the_ht_tunnel.csr_write_mask_usr(csr_write_mask_usr);
|
410 |
|
|
|
411 |
|
|
// ***************************************************
|
412 |
|
|
// LINKING TB
|
413 |
|
|
// ***************************************************
|
414 |
|
|
|
415 |
|
|
tb.clk(clk);
|
416 |
|
|
tb.resetx(resetx);
|
417 |
|
|
tb.pwrok(pwrok);
|
418 |
|
|
tb.ldtstopx(ldtstopx);
|
419 |
|
|
|
420 |
|
|
tb.phy0_available_lk0(phy0_available_lk0);
|
421 |
|
|
tb.phy0_ctl_lk0(phy0_ctl_lk0);
|
422 |
|
|
|
423 |
|
|
for(int n = 0; n < CAD_IN_WIDTH; n++){
|
424 |
|
|
tb.phy0_cad_lk0[n](phy0_cad_lk0[n]);
|
425 |
|
|
tb.lk0_cad_phy0[n](lk0_cad_phy0[n]);
|
426 |
|
|
tb.phy1_cad_lk1[n](phy1_cad_lk1[n]);
|
427 |
|
|
tb.lk1_cad_phy1[n](lk1_cad_phy1[n]);
|
428 |
|
|
}
|
429 |
|
|
|
430 |
|
|
tb.lk0_ctl_phy0(lk0_ctl_phy0);
|
431 |
|
|
tb.phy0_consume_lk0(phy0_consume_lk0);
|
432 |
|
|
|
433 |
|
|
tb.lk0_disable_drivers_phy0(lk0_disable_drivers_phy0);
|
434 |
|
|
tb.lk0_disable_receivers_phy0(lk0_disable_receivers_phy0);
|
435 |
|
|
|
436 |
|
|
tb.phy1_available_lk1(phy1_available_lk1);
|
437 |
|
|
tb.phy1_ctl_lk1(phy1_ctl_lk1);
|
438 |
|
|
|
439 |
|
|
tb.lk1_ctl_phy1(lk1_ctl_phy1);
|
440 |
|
|
tb.phy1_consume_lk1(phy1_consume_lk1);
|
441 |
|
|
|
442 |
|
|
tb.lk1_disable_drivers_phy1(lk1_disable_drivers_phy1);
|
443 |
|
|
tb.lk1_disable_receivers_phy1(lk1_disable_receivers_phy1);
|
444 |
|
|
|
445 |
|
|
tb.ui_memory_write0(ui_memory_write0);
|
446 |
|
|
tb.ui_memory_write1(ui_memory_write1);//20
|
447 |
|
|
tb.ui_memory_write_address(ui_memory_write_address);
|
448 |
|
|
tb.ui_memory_write_data(ui_memory_write_data);
|
449 |
|
|
|
450 |
|
|
tb.ui_memory_read_address0(ui_memory_read_address0);
|
451 |
|
|
tb.ui_memory_read_address1(ui_memory_read_address1);
|
452 |
|
|
tb.ui_memory_read_data0(ui_memory_read_data0);
|
453 |
|
|
tb.ui_memory_read_data1(ui_memory_read_data1);
|
454 |
|
|
|
455 |
|
|
#ifdef RETRY_MODE_ENABLED
|
456 |
|
|
tb.history_memory_write0(history_memory_write0);
|
457 |
|
|
tb.history_memory_write_address0(history_memory_write_address0);
|
458 |
|
|
tb.history_memory_write_data0(history_memory_write_data0);
|
459 |
|
|
tb.history_memory_read_address0(history_memory_read_address0);//30
|
460 |
|
|
tb.history_memory_output0(history_memory_output0);
|
461 |
|
|
|
462 |
|
|
tb.history_memory_write1(history_memory_write1);
|
463 |
|
|
tb.history_memory_write_address1(history_memory_write_address1);
|
464 |
|
|
tb.history_memory_write_data1(history_memory_write_data1);
|
465 |
|
|
tb.history_memory_read_address1(history_memory_read_address1);
|
466 |
|
|
tb.history_memory_output1(history_memory_output1);
|
467 |
|
|
|
468 |
|
|
#endif
|
469 |
|
|
|
470 |
|
|
|
471 |
|
|
tb.memory_write0(memory_write0);
|
472 |
|
|
tb.memory_write_address_vc0(memory_write_address_vc0);
|
473 |
|
|
tb.memory_write_address_buffer0(memory_write_address_buffer0);
|
474 |
|
|
tb.memory_write_address_pos0(memory_write_address_pos0);//40
|
475 |
|
|
tb.memory_write_data0(memory_write_data0);
|
476 |
|
|
|
477 |
|
|
tb.memory_read_address_vc0[0](memory_read_address_vc0[0]);
|
478 |
|
|
tb.memory_read_address_buffer0[0](memory_read_address_buffer0[0]);
|
479 |
|
|
tb.memory_read_address_pos0[0](memory_read_address_pos0[0]);//50
|
480 |
|
|
tb.memory_output0[0](memory_output0[0]);
|
481 |
|
|
|
482 |
|
|
tb.memory_read_address_vc0[1](memory_read_address_vc0[1]);
|
483 |
|
|
tb.memory_read_address_buffer0[1](memory_read_address_buffer0[1]);
|
484 |
|
|
tb.memory_read_address_pos0[1](memory_read_address_pos0[1]);//50
|
485 |
|
|
tb.memory_output0[1](memory_output0[1]);
|
486 |
|
|
|
487 |
|
|
|
488 |
|
|
tb.memory_write1(memory_write1);
|
489 |
|
|
tb.memory_write_address_vc1(memory_write_address_vc1);
|
490 |
|
|
tb.memory_write_address_buffer1(memory_write_address_buffer1);
|
491 |
|
|
tb.memory_write_address_pos1(memory_write_address_pos1);
|
492 |
|
|
tb.memory_write_data1(memory_write_data1);
|
493 |
|
|
|
494 |
|
|
tb.memory_read_address_vc1[0](memory_read_address_vc1[0]);
|
495 |
|
|
tb.memory_read_address_buffer1[0](memory_read_address_buffer1[0]);
|
496 |
|
|
tb.memory_read_address_pos1[0](memory_read_address_pos1[0]);
|
497 |
|
|
tb.memory_output1[0](memory_output1[0]);
|
498 |
|
|
|
499 |
|
|
tb.memory_read_address_vc1[1](memory_read_address_vc1[1]);
|
500 |
|
|
tb.memory_read_address_buffer1[1](memory_read_address_buffer1[1]);
|
501 |
|
|
tb.memory_read_address_pos1[1](memory_read_address_pos1[1]);
|
502 |
|
|
tb.memory_output1[1](memory_output1[1]);
|
503 |
|
|
|
504 |
|
|
|
505 |
|
|
tb.ui_packet_usr(ui_packet_usr);
|
506 |
|
|
tb.ui_vc_usr(ui_vc_usr);
|
507 |
|
|
tb.ui_side_usr(ui_side_usr);
|
508 |
|
|
tb.ui_directroute_usr(ui_directroute_usr);
|
509 |
|
|
tb.ui_eop_usr(ui_eop_usr);
|
510 |
|
|
tb.ui_available_usr(ui_available_usr);
|
511 |
|
|
tb.ui_output_64bits_usr(ui_output_64bits_usr);
|
512 |
|
|
tb.usr_consume_ui(usr_consume_ui);
|
513 |
|
|
tb.usr_packet_ui(usr_packet_ui);
|
514 |
|
|
tb.usr_available_ui(usr_available_ui);
|
515 |
|
|
tb.usr_side_ui(usr_side_ui);
|
516 |
|
|
tb.ui_freevc0_usr(ui_freevc0_usr);
|
517 |
|
|
tb.ui_freevc1_usr(ui_freevc1_usr);
|
518 |
|
|
tb.usr_receivedResponseError_csr(usr_receivedResponseError_csr);
|
519 |
|
|
}
|
520 |
|
|
};
|
521 |
|
|
|