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acastong |
//ht_errorHandler.cpp
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/* ***** BEGIN LICENSE BLOCK *****
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* Version: MPL 1.1
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*
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* The contents of this file are subject to the Mozilla Public License Version
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* 1.1 (the "License"); you may not use this file except in compliance with
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* the License. You may obtain a copy of the License at
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* http://www.mozilla.org/MPL/
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*
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* Software distributed under the License is distributed on an "AS IS" basis,
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* WITHOUT WARRANTY OF ANY KIND, either express or implied. See the License
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* for the specific language governing rights and limitations under the
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* License.
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*
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* The Original Code is HyperTransport Tunnel IP Core.
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*
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* The Initial Developer of the Original Code is
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* Ecole Polytechnique de Montreal.
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* Portions created by the Initial Developer are Copyright (C) 2005
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* the Initial Developer. All Rights Reserved.
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*
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* Contributor(s):
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* Martin Corriveau
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* Ami Castonguay <acastong@grm.polymtl.ca>
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*
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* Alternatively, the contents of this file may be used under the terms
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* of the Polytechnique HyperTransport Tunnel IP Core Source Code License
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* (the "PHTICSCL License", see the file PHTICSCL.txt), in which case the
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* provisions of PHTICSCL License are applicable instead of those
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* above. If you wish to allow use of your version of this file only
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* under the terms of the PHTICSCL License and not to allow others to use
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* your version of this file under the MPL, indicate your decision by
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* deleting the provisions above and replace them with the notice and
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* other provisions required by the PHTICSCL License. If you do not delete
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* the provisions above, a recipient may use your version of this file
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* under either the MPL or the PHTICSCL License."
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*
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* ***** END LICENSE BLOCK ***** */
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#include "errorhandler_l2.h"
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errorhandler_l2::errorhandler_l2( sc_module_name name) :sc_module(name)
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{
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//This is combinatory to it's sensitive to all the variables read by the process
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SC_METHOD(stateMachine);
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sensitive << csr_end_of_chain << csr_initcomplete << csr_drop_uninit_link << csr_unit_id <<
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ro_available_fwd << ro_packet_fwd <<
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fc_ack_eh << inputRegister << eh_cmd_data_fc << eh_available_fc << dataLeftToSendm1 << state;
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//This represents registers, so it's only sensitive to clk and reset
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SC_METHOD(clockAndReset);
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sensitive_neg << resetx;
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sensitive_pos << clk;
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}
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void errorhandler_l2::clockAndReset(){
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if(resetx.read() == false){
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//We have no data to send
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dataLeftToSendm1 = 0;
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//Go back to idle state
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state = IdleState;
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eh_cmd_data_fc = 0;
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eh_available_fc = false;
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syn_ControlPacketComplete defaultPkt;
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initialize_syn_ControlPacketComplete(defaultPkt);
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inputRegister = defaultPkt;
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}
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else{
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eh_available_fc = next_outputReq;
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dataLeftToSendm1 = next_dataLeftToSendm1;
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state = next_state;
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eh_cmd_data_fc = next_outputData;
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inputRegister = next_inputRegister;
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}
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}
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bool errorhandler_l2::checkEOCError() const
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{
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/**
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End of chain can happen for two reasons :
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- csr_end_of_chain is asserted, either because we truly are
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the last element of the chain or because it is set by
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software
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- The link is not initialized yet and csr_drop_uninit_link is
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set.
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*/
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if( csr_end_of_chain.read() == true ||
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( csr_initcomplete.read() == false &&
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csr_drop_uninit_link.read() == true ) )
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{
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return true;
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}
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return false;
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}
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#ifdef SYSTEMC_SIM
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/// Trace external function
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void
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sc_trace( sc_trace_file *tf, const errorhandler_l2& v,
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const sc_string& NAME )
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{
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sc_trace(tf,v.clk, NAME + ".clk");
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sc_trace(tf,v.ro_packet_fwd, NAME + ".ro_packet_fwd");
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sc_trace(tf,v.ro_available_fwd, NAME + ".ro_available_fwd");
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sc_trace(tf,v.eh_ack_ro, NAME + ".eh_ack_ro");
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sc_trace(tf,v.fc_ack_eh, NAME + ".fc_ack_eh");
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sc_trace(tf,v.eh_cmd_data_fc, NAME + ".eh_cmd_data_fc");
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sc_trace(tf,v.eh_available_fc, NAME + ".eh_available_fc");
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sc_trace(tf,v.eh_address_db, NAME + ".eh_address_db");
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sc_trace(tf,v.eh_erase_db, NAME + ".eh_erase_db");
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sc_trace(tf,v.eh_vctype_db, NAME + ".eh_vctype_db");
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sc_trace(tf,v.csr_end_of_chain, NAME + ".csr_end_of_chain");
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sc_trace(tf,v.csr_initcomplete, NAME + ".csr_initcomplete");
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sc_trace(tf,v.csr_drop_uninit_link, NAME + ".csr_drop_uninit_link");
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sc_trace(tf,v.resetx, NAME + ".resetx");
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sc_trace(tf,v.dataLeftToSendm1, NAME + ".dataLeftToSendm1");
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}
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#endif
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void errorhandler_l2::stateMachine(){
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///////////////////////////////////////////////
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// Default outputs
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///////////////////////////////////////////////
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eh_ack_ro = false;
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next_dataLeftToSendm1 = 0;
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//All 1's because response packets for end of chain errors must only contain 1's
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next_outputData = "11111111111111111111111111111111";
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next_outputReq = false;
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next_state = IdleState;
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next_inputRegister = ro_packet_fwd.read();
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eh_address_db.write( 0 );
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eh_vctype_db.write( VC_NONE );
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eh_erase_db = false;
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//No need for this, reading the packet at the input is a signal that we
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//received a eoc packet, so no need for an extra signal.
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//eh_received_eoc_error_csr = false;
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//General variables that can be used in multiple states
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sc_bv<64> input_register_pkt = inputRegister.read().packet;
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PacketCommand input_register_cmd = getPacketCommand(input_register_pkt.range(5,0));
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VirtualChannel input_register_vc = getVirtualChannel(input_register_pkt,input_register_cmd);
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bool dataAssociated = hasDataAssociated(input_register_cmd);
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switch(state){
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///////////////////////////////////////////////
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// IDLE STATE
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///////////////////////////////////////////////
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case IdleState :
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/**If there is a packet and it is a an end of chain error
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The same packets "signal" goes to both the flow control and
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the error handler. What dicates who consumes that packet
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is if we are currently in a end of chain states
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*/
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if((checkEOCError() || ro_packet_fwd.read().error64BitExtension)
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&& ro_available_fwd == true){
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next_state = AnalyzePacketStateOutputFree;
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eh_ack_ro = true;
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}
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break;
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///////////////////////////////////////////////
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// AnalyzePacketStateOutputLoaded STATE
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///////////////////////////////////////////////
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/** This state means that we have a new packet to analyze in the
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input buffer but that there is also data in the output buffer
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waiting to be sent
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*/
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case AnalyzePacketStateOutputLoaded :
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next_outputReq = true;
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next_outputData = eh_cmd_data_fc.read();
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next_state = AnalyzePacketStateOutputLoaded;
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//This state does roughly he same thing as the next state, but can only
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//update the output buffers if the FC acks what in the output buffer
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//If there is no ack, we stop right here and wait for the ack.
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if(fc_ack_eh.read() == false) break;
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/** This state means that we have a new packet to analyze in the
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input buffer and that we can output data to the flow control
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immediately.
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*/
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///////////////////////////////////////////////
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// AnalyzePacketStateOutputFree STATE
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///////////////////////////////////////////////
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case AnalyzePacketStateOutputFree :
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//When we reveice non posted packets, we generate a response with
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//the MASTER_ABORT bit on
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if(input_register_vc == VC_NON_POSTED ){
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// Construct Response Packet and activate the sending process
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bool passPW = getPassPW(input_register_pkt);
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sc_uint<5> dataLengthm1 = getDataLengthm1(input_register_pkt);
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//sc_uint<5> dataLength = dataLengthm1 + 1;
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sc_bv<5> reqUID = getUnitID(input_register_pkt);
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sc_bv<5> srcTag = request_getSrcTag(input_register_pkt);
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switch( input_register_cmd ){
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case READ:
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case ATOMIC:
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{
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/**
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In the case we received READ or ATOMIC request, we must
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reply with a response that has the right amount of data
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requested.
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*/
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sc_bv<32> readResponse = generateReadResponse( csr_unit_id.read(),
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srcTag,
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reqUID.range(1,0),
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dataLengthm1,
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false,
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RE_MASTER_ABORT,
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passPW,
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false);
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next_outputData = readResponse;
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next_outputReq = true;
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next_dataLeftToSendm1 = dataLengthm1;
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next_state = SendingDataStateInputFree;
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}
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break;
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//case WRITE:
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default:
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{
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/**
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In the case of a WRITE, we simply respond with a
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TargetDone
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*/
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next_outputData = generateTargetDone( csr_unit_id.read(),
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srcTag,
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reqUID.range(1,0),
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false,
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RE_MASTER_ABORT,
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passPW,
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false);
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next_outputReq = true;
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next_state = InputFreeOutputLoaded;
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}
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break;
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}
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}
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//In the case of POSTED and RESPONSE vc's, we can't response
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//We simply flag a bit in the CSR saying that we received an error.
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else if(input_register_cmd != BROADCAST){
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//eh_received_eoc_error_csr = true;
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}
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/** If the received packet contained data, we drop it */
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if(dataAssociated){
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eh_address_db.write( inputRegister.read().data_address );
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eh_vctype_db.write( input_register_vc);
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eh_erase_db = true;
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}
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break;
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///////////////////////////////////////////////
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// SendingDataStateInputFree STATE
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///////////////////////////////////////////////
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case SendingDataStateInputFree :
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next_outputReq = true;
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next_dataLeftToSendm1 = dataLeftToSendm1;
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next_state = SendingDataStateInputFree;
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//If there is a new packet at the input
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if((checkEOCError() || ro_packet_fwd.read().error64BitExtension)
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&& ro_available_fwd == true){
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//If we only have one more data to send and the current data
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//is being read, load the last data and analyze the new packet
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if(dataLeftToSendm1.read() == 0 && fc_ack_eh.read() == true) {
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next_state = AnalyzePacketStateOutputLoaded;
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}
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//If we only have one more data to send and the current data
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//is not being read, we stay
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else if(dataLeftToSendm1.read() == 0){
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next_state = SendingDataStateInputLoaded;
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next_outputData = eh_cmd_data_fc.read();
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}
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else {
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next_state = SendingDataStateInputLoaded;
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297 |
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if(fc_ack_eh.read() == true){
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298 |
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next_dataLeftToSendm1 = dataLeftToSendm1.read() - 1;
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299 |
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}
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else{
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next_outputData = eh_cmd_data_fc.read();
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}
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}
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eh_ack_ro = true;
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}
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else if(fc_ack_eh.read() == true){
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307 |
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if(dataLeftToSendm1.read() == 0){
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308 |
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next_state = InputFreeOutputLoaded;
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}
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else{
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311 |
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next_dataLeftToSendm1 = dataLeftToSendm1.read() - 1;
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312 |
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}
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313 |
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}
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314 |
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else{
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315 |
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next_outputData = eh_cmd_data_fc.read();
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316 |
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}
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317 |
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318 |
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break;
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319 |
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320 |
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///////////////////////////////////////////////
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321 |
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// SendingDataStateInputLoaded STATE
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322 |
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///////////////////////////////////////////////
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323 |
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case SendingDataStateInputLoaded :
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next_outputReq = true;
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next_dataLeftToSendm1 = dataLeftToSendm1;
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next_state = SendingDataStateInputLoaded;
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next_inputRegister = inputRegister;
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328 |
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329 |
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if(fc_ack_eh.read() == true){
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330 |
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if(dataLeftToSendm1.read() == 0) next_state = AnalyzePacketStateOutputLoaded;
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else next_dataLeftToSendm1 = dataLeftToSendm1.read() - 1;
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332 |
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}
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333 |
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else{
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next_outputData = eh_cmd_data_fc.read();
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335 |
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}
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336 |
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break;
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337 |
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338 |
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///////////////////////////////////////////////
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339 |
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// InputFreeOutputLoaded STATE
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340 |
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///////////////////////////////////////////////
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341 |
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case InputFreeOutputLoaded :
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342 |
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next_outputData = eh_cmd_data_fc.read();
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343 |
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next_outputReq = true;
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344 |
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345 |
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if((checkEOCError() || ro_packet_fwd.read().error64BitExtension)
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346 |
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&& ro_available_fwd == true){
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347 |
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if(fc_ack_eh.read() == true){
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348 |
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next_state = AnalyzePacketStateOutputFree;
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349 |
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next_outputReq = false;
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350 |
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|
}
|
351 |
|
|
else{
|
352 |
|
|
next_state = AnalyzePacketStateOutputLoaded;
|
353 |
|
|
next_outputData = eh_cmd_data_fc.read();
|
354 |
|
|
}
|
355 |
|
|
}
|
356 |
|
|
else if(fc_ack_eh.read() == true){
|
357 |
|
|
next_state = IdleState;
|
358 |
|
|
next_outputReq = false;
|
359 |
|
|
}
|
360 |
|
|
else{
|
361 |
|
|
next_state = InputFreeOutputLoaded;
|
362 |
|
|
next_outputData = eh_cmd_data_fc.read();
|
363 |
|
|
}
|
364 |
|
|
break;
|
365 |
|
|
|
366 |
|
|
}
|
367 |
|
|
}
|
368 |
|
|
|
369 |
|
|
#ifndef SYSTEMC_SIM
|
370 |
|
|
#include "../core_synth/synth_control_packet.cpp"
|
371 |
|
|
#endif
|
372 |
|
|
|
373 |
|
|
|