| 1 |
2 |
kavi |
----==============================================================----
|
| 2 |
|
|
---- ----
|
| 3 |
|
|
---- Filename: csa8.vhd ----
|
| 4 |
|
|
---- Module description: Top-level module of 8-bit carry-select ----
|
| 5 |
|
|
---- adder ----
|
| 6 |
|
|
---- ----
|
| 7 |
|
|
---- Author: Nikolaos Kavvadias ----
|
| 8 |
|
|
---- nkavv@skiathos.physics.auth.gr ----
|
| 9 |
|
|
---- ----
|
| 10 |
|
|
---- ----
|
| 11 |
|
|
---- Downloaded from: http://wwww.opencores.org/cores/hwlu ----
|
| 12 |
|
|
---- ----
|
| 13 |
|
|
---- To Do: ----
|
| 14 |
|
|
---- Probably remains as current ----
|
| 15 |
|
|
---- (to promote as stable version) ----
|
| 16 |
|
|
---- ----
|
| 17 |
|
|
---- Author: Nikolaos Kavvadias ----
|
| 18 |
|
|
---- nkavv@skiathos.physics.auth.gr ----
|
| 19 |
|
|
---- ----
|
| 20 |
|
|
----==============================================================----
|
| 21 |
|
|
---- ----
|
| 22 |
|
|
---- Copyright (C) 2004 Nikolaos Kavvadias ----
|
| 23 |
|
|
---- nick-kavi.8m.com ----
|
| 24 |
|
|
---- nkavv@skiathos.physics.auth.gr ----
|
| 25 |
|
|
---- nick_ka_vi@hotmail.com ----
|
| 26 |
|
|
---- ----
|
| 27 |
|
|
---- This source file may be used and distributed without ----
|
| 28 |
|
|
---- restriction provided that this copyright statement is not ----
|
| 29 |
|
|
---- removed from the file and that any derivative work contains ----
|
| 30 |
|
|
---- the original copyright notice and the associated disclaimer. ----
|
| 31 |
|
|
---- ----
|
| 32 |
|
|
---- This source file is free software; you can redistribute it ----
|
| 33 |
|
|
---- and/or modify it under the terms of the GNU Lesser General ----
|
| 34 |
|
|
---- Public License as published by the Free Software Foundation; ----
|
| 35 |
|
|
---- either version 2.1 of the License, or (at your option) any ----
|
| 36 |
|
|
---- later version. ----
|
| 37 |
|
|
---- ----
|
| 38 |
|
|
---- This source is distributed in the hope that it will be ----
|
| 39 |
|
|
---- useful, but WITHOUT ANY WARRANTY; without even the implied ----
|
| 40 |
|
|
---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ----
|
| 41 |
|
|
---- PURPOSE. See the GNU Lesser General Public License for more ----
|
| 42 |
|
|
---- details. ----
|
| 43 |
|
|
---- ----
|
| 44 |
|
|
---- You should have received a copy of the GNU Lesser General ----
|
| 45 |
|
|
---- Public License along with this source; if not, download it ----
|
| 46 |
|
|
---- from <http://www.opencores.org/lgpl.shtml> ----
|
| 47 |
|
|
---- ----
|
| 48 |
|
|
----==============================================================----
|
| 49 |
|
|
--
|
| 50 |
|
|
-- CVS Revision History
|
| 51 |
|
|
--
|
| 52 |
|
|
|
| 53 |
|
|
library IEEE;
|
| 54 |
|
|
use IEEE.std_logic_1164.all;
|
| 55 |
|
|
|
| 56 |
|
|
|
| 57 |
|
|
entity add is
|
| 58 |
|
|
generic (
|
| 59 |
|
|
DW : integer := 8
|
| 60 |
|
|
);
|
| 61 |
|
|
port (
|
| 62 |
|
|
a : in std_logic_vector(DW-1 downto 0);
|
| 63 |
|
|
b : in std_logic_vector(DW-1 downto 0);
|
| 64 |
|
|
sum : out std_logic_vector(DW-1 downto 0)
|
| 65 |
|
|
);
|
| 66 |
|
|
end add;
|
| 67 |
|
|
|
| 68 |
|
|
architecture structural of add is
|
| 69 |
|
|
-- Component declarations
|
| 70 |
|
|
component fa
|
| 71 |
|
|
port (
|
| 72 |
|
|
a : in std_logic;
|
| 73 |
|
|
b : in std_logic;
|
| 74 |
|
|
ci : in std_logic;
|
| 75 |
|
|
s : out std_logic;
|
| 76 |
|
|
co : out std_logic
|
| 77 |
|
|
);
|
| 78 |
|
|
end component;
|
| 79 |
|
|
--
|
| 80 |
|
|
component fa_nc
|
| 81 |
|
|
port (
|
| 82 |
|
|
a : in std_logic;
|
| 83 |
|
|
b : in std_logic;
|
| 84 |
|
|
ci : in std_logic;
|
| 85 |
|
|
s : out std_logic
|
| 86 |
|
|
);
|
| 87 |
|
|
end component;
|
| 88 |
|
|
--
|
| 89 |
|
|
component mux2_1
|
| 90 |
|
|
generic (
|
| 91 |
|
|
DW : integer := 8
|
| 92 |
|
|
);
|
| 93 |
|
|
port (
|
| 94 |
|
|
in0 : in std_logic_vector(DW-1 downto 0);
|
| 95 |
|
|
in1 : in std_logic_vector(DW-1 downto 0);
|
| 96 |
|
|
sel : in std_logic;
|
| 97 |
|
|
mout : out std_logic_vector(DW-1 downto 0)
|
| 98 |
|
|
);
|
| 99 |
|
|
end component;
|
| 100 |
|
|
--
|
| 101 |
|
|
-- Signal declarations
|
| 102 |
|
|
signal carry : std_logic_vector(4 downto 0);
|
| 103 |
|
|
signal s_up_ci0 : std_logic_vector(3 downto 0);
|
| 104 |
|
|
signal s_up_ci1 : std_logic_vector(3 downto 0);
|
| 105 |
|
|
signal zero_1b, one_1b : std_logic;
|
| 106 |
|
|
begin
|
| 107 |
|
|
|
| 108 |
|
|
carry(0) <= '0';
|
| 109 |
|
|
--
|
| 110 |
|
|
zero_1b <= '0';
|
| 111 |
|
|
one_1b <= '1';
|
| 112 |
|
|
|
| 113 |
|
|
U_fa0_3_cells : for i in 0 to 3 generate
|
| 114 |
|
|
U_fa : fa
|
| 115 |
|
|
port map (
|
| 116 |
|
|
a => a(i),
|
| 117 |
|
|
b => b(i),
|
| 118 |
|
|
ci => carry(i),
|
| 119 |
|
|
s => sum(i),
|
| 120 |
|
|
co => carry(i+1)
|
| 121 |
|
|
);
|
| 122 |
|
|
end generate U_fa0_3_cells;
|
| 123 |
|
|
|
| 124 |
|
|
U_fa4_7_ci0_cells : for i in 0 to 3 generate
|
| 125 |
|
|
U_fa_nc : fa_nc
|
| 126 |
|
|
port map (
|
| 127 |
|
|
a => a(i+4),
|
| 128 |
|
|
b => b(i+4),
|
| 129 |
|
|
ci => zero_1b,
|
| 130 |
|
|
s => s_up_ci0(i)
|
| 131 |
|
|
);
|
| 132 |
|
|
end generate U_fa4_7_ci0_cells;
|
| 133 |
|
|
|
| 134 |
|
|
U_fa4_7_ci1_cells : for i in 0 to 3 generate
|
| 135 |
|
|
U_fa_nc : fa_nc
|
| 136 |
|
|
port map (
|
| 137 |
|
|
a => a(i+4),
|
| 138 |
|
|
b => b(i+4),
|
| 139 |
|
|
ci => one_1b,
|
| 140 |
|
|
s => s_up_ci1(i)
|
| 141 |
|
|
);
|
| 142 |
|
|
end generate U_fa4_7_ci1_cells;
|
| 143 |
|
|
|
| 144 |
|
|
U_mux_s_up : mux2_1
|
| 145 |
|
|
generic map (
|
| 146 |
|
|
DW => 4
|
| 147 |
|
|
)
|
| 148 |
|
|
port map (
|
| 149 |
|
|
in0 => s_up_ci0(3 downto 0),
|
| 150 |
|
|
in1 => s_up_ci1(3 downto 0),
|
| 151 |
|
|
sel => carry(4),
|
| 152 |
|
|
mout => sum(7 downto 4)
|
| 153 |
|
|
);
|
| 154 |
|
|
|
| 155 |
|
|
end structural;
|
