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kavi |
----==============================================================----
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---- ----
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---- Filename: hw_loops5_top.vhd ----
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---- Module description: Top-level file for the hw_looping unit. ----
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---- Also implements input and output ----
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---- wrapping operations. ----
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---- ----
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---- Author: Nikolaos Kavvadias ----
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---- nkavv@physics.auth.gr ----
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---- ----
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---- ----
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---- Part of the hwlu OPENCORES project generated automatically ----
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---- with the use of the "gen_hw_looping" tool ----
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---- ----
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---- To Do: ----
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---- Considered stable for the time being ----
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---- ----
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---- Author: Nikolaos Kavvadias ----
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---- nkavv@physics.auth.gr ----
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---- ----
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----==============================================================----
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---- ----
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---- Copyright (C) 2004-2010 Nikolaos Kavvadias ----
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---- nkavv@uop.gr ----
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---- nkavv@physics.auth.gr ----
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---- nikolaos.kavvadias@gmail.com ----
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---- ----
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---- This source file may be used and distributed without ----
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---- restriction provided that this copyright statement is not ----
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---- removed from the file and that any derivative work contains ----
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---- the original copyright notice and the associated disclaimer. ----
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---- ----
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---- This source file is free software; you can redistribute it ----
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---- and/or modify it under the terms of the GNU Lesser General ----
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---- Public License as published by the Free Software Foundation; ----
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---- either version 2.1 of the License, or (at your option) any ----
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---- later version. ----
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---- ----
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---- This source is distributed in the hope that it will be ----
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---- useful, but WITHOUT ANY WARRANTY; without even the implied ----
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---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ----
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---- PURPOSE. See the GNU Lesser General Public License for more ----
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---- details. ----
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---- ----
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---- You should have received a copy of the GNU Lesser General ----
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---- Public License along with this source; if not, download it ----
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---- from <http://www.opencores.org/lgpl.shtml> ----
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---- ----
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----==============================================================----
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--
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-- CVS Revision History
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--
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library IEEE;
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use IEEE.std_logic_1164.all;
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entity hw_looping is
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generic (
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NLP : integer := 5;
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DW : integer := 8
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);
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port (
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clk : in std_logic;
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reset : in std_logic;
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task_loop5_end : in std_logic;
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loop1_count : in std_logic_vector(DW-1 downto 0);
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loop2_count : in std_logic_vector(DW-1 downto 0);
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loop3_count : in std_logic_vector(DW-1 downto 0);
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loop4_count : in std_logic_vector(DW-1 downto 0);
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loop5_count : in std_logic_vector(DW-1 downto 0);
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index1 : out std_logic_vector(DW-1 downto 0);
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index2 : out std_logic_vector(DW-1 downto 0);
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index3 : out std_logic_vector(DW-1 downto 0);
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index4 : out std_logic_vector(DW-1 downto 0);
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index5 : out std_logic_vector(DW-1 downto 0);
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loops_end : out std_logic
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);
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end hw_looping;
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architecture structural of hw_looping is
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--
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-- Component declarations
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component cmpeq
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generic (
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DW : integer := 8
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);
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port (
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a : in std_logic_vector(DW-1 downto 0);
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b : in std_logic_vector(DW-1 downto 0);
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reset : in std_logic;
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a_eq_b : out std_logic
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);
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end component;
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--
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component index_inc
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generic (
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DW : integer := 8
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);
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port (
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clk : in std_logic;
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reset : in std_logic;
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inc_en : in std_logic;
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index_plus_one : out std_logic_vector(DW-1 downto 0);
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index_out : out std_logic_vector(DW-1 downto 0)
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);
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end component;
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--
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component priority_encoder
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generic (
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NLP : integer := 5
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);
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port (
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flag : in std_logic_vector(NLP-1 downto 0);
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task_loop5_end : in std_logic;
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incl : out std_logic_vector(NLP-1 downto 0);
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reset_vct : out std_logic_vector(NLP-1 downto 0);
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loops_end : out std_logic
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);
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end component;
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--
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-- Signal declarations
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signal flag : std_logic_vector(NLP-1 downto 0);
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signal incl : std_logic_vector(NLP-1 downto 0);
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signal temp_loop_count : std_logic_vector(NLP*DW-1 downto 0);
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signal temp_index : std_logic_vector(NLP*DW-1 downto 0);
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signal temp_index_plus_one : std_logic_vector(NLP*DW-1 downto 0);
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signal reset_vct_penc : std_logic_vector(NLP-1 downto 0);
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signal reset_vct_ix : std_logic_vector(NLP-1 downto 0);
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--
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begin
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temp_loop_count( ((NLP-0)*DW-1) downto ((NLP-1)*DW) ) <= loop1_count;
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temp_loop_count( ((NLP-1)*DW-1) downto ((NLP-2)*DW) ) <= loop2_count;
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temp_loop_count( ((NLP-2)*DW-1) downto ((NLP-3)*DW) ) <= loop3_count;
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temp_loop_count( ((NLP-3)*DW-1) downto ((NLP-4)*DW) ) <= loop4_count;
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temp_loop_count( ((NLP-4)*DW-1) downto ((NLP-5)*DW) ) <= loop5_count;
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GEN_COMPARATORS: for i in 0 to NLP-1 generate
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U_cmp : cmpeq
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generic map (
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DW => DW
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)
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port map (
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a => temp_index_plus_one( ((i+1)*DW-1) downto (i*DW) ),
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b => temp_loop_count( ((i+1)*DW-1) downto (i*DW) ),
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reset => reset,
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a_eq_b => flag(i)
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);
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end generate GEN_COMPARATORS;
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U_priority_enc : priority_encoder
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generic map (
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NLP => NLP
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)
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port map (
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flag => flag,
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task_loop5_end => task_loop5_end,
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incl => incl,
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reset_vct => reset_vct_penc,
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loops_end => loops_end
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);
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GEN_RESET_SEL: for i in 0 to NLP-1 generate
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reset_vct_ix(i) <= reset_vct_penc(i) or reset;
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end generate GEN_RESET_SEL;
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GEN_INC_IX: for i in 0 to NLP-1 generate
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U_inc_ix1 : index_inc
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generic map (
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DW => DW
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)
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port map (
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clk => clk,
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reset => reset_vct_ix(i),
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inc_en => incl(i),
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index_plus_one => temp_index_plus_one( ((i+1)*DW-1) downto (i*DW) ),
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index_out => temp_index( ((i+1)*DW-1) downto (i*DW) )
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);
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end generate GEN_INC_IX;
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index1 <= temp_index( ((NLP-0)*DW-1) downto ((NLP-1)*DW) );
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index2 <= temp_index( ((NLP-1)*DW-1) downto ((NLP-2)*DW) );
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index3 <= temp_index( ((NLP-2)*DW-1) downto ((NLP-3)*DW) );
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index4 <= temp_index( ((NLP-3)*DW-1) downto ((NLP-4)*DW) );
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index5 <= temp_index( ((NLP-4)*DW-1) downto ((NLP-5)*DW) );
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end structural;
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