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kavi |
----==============================================================----
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---- ----
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---- Filename: index_inc.vhd ----
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---- Module description: Index increment-by-one unit ----
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---- ----
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---- Author: Nikolaos Kavvadias ----
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---- nkavv@skiathos.physics.auth.gr ----
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---- ----
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---- ----
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---- Downloaded from: http://wwww.opencores.org/cores/hwlu ----
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---- ----
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---- To Do: ----
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---- Probably remains as current ----
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---- (to promote as stable version) ----
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---- ----
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---- Author: Nikolaos Kavvadias ----
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---- nkavv@skiathos.physics.auth.gr ----
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---- ----
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----==============================================================----
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---- ----
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---- Copyright (C) 2004 Nikolaos Kavvadias ----
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---- nick-kavi.8m.com ----
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---- nkavv@skiathos.physics.auth.gr ----
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---- nick_ka_vi@hotmail.com ----
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---- ----
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---- This source file may be used and distributed without ----
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---- restriction provided that this copyright statement is not ----
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---- removed from the file and that any derivative work contains ----
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---- the original copyright notice and the associated disclaimer. ----
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---- ----
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---- This source file is free software; you can redistribute it ----
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---- and/or modify it under the terms of the GNU Lesser General ----
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---- Public License as published by the Free Software Foundation; ----
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---- either version 2.1 of the License, or (at your option) any ----
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---- later version. ----
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---- ----
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---- This source is distributed in the hope that it will be ----
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---- useful, but WITHOUT ANY WARRANTY; without even the implied ----
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---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ----
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---- PURPOSE. See the GNU Lesser General Public License for more ----
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---- details. ----
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---- ----
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---- You should have received a copy of the GNU Lesser General ----
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---- Public License along with this source; if not, download it ----
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---- from <http://www.opencores.org/lgpl.shtml> ----
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---- ----
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----==============================================================----
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--
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-- CVS Revision History
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--
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library IEEE;
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use IEEE.std_logic_1164.all;
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use IEEE.std_logic_unsigned.all;
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use IEEE.std_logic_arith.all;
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entity index_inc is
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generic (
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DW : integer := 8
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);
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port (
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clk : in std_logic;
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reset : in std_logic;
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inc_en : in std_logic;
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index_plus_one : out std_logic_vector(Dw-1 downto 0);
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index_out : out std_logic_vector(DW-1 downto 0)
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);
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end index_inc;
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architecture rtl of index_inc is
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--
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-- Component declarations
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component add
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generic (
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DW : integer := 8
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);
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port (
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a : in std_logic_vector(DW-1 downto 0);
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b : in std_logic_vector(DW-1 downto 0);
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sum : out std_logic_vector(DW-1 downto 0)
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);
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end component;
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--
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component reg_dw
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generic (
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DW : integer := 8
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);
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port (
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clk : in std_logic;
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reset : in std_logic;
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load : in std_logic;
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d : in std_logic_vector(DW-1 downto 0);
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q : out std_logic_vector(DW-1 downto 0)
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);
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end component;
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--
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-- Constant declarations
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constant one_dw : std_logic_vector(DW-1 downto 0) := conv_std_logic_vector(1,DW);
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--
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-- Signal declarations
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signal index_rin, index_r : std_logic_vector(DW-1 downto 0);
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--
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begin
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U_adder : add
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generic map (
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DW => DW
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)
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port map (
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a => index_r,
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b => one_dw,
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sum => index_rin
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);
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U_reg_dw : reg_dw
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generic map (
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DW => DW
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)
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port map (
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clk => clk,
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reset => reset,
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load => inc_en,
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d => index_rin,
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q => index_r
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);
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index_out <= index_r;
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index_plus_one <= index_rin;
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end rtl;
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