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[/] [hwlu/] [trunk/] [sw/] [gen_hw_looping.c] - Blame information for rev 12

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1 12 kavi 
/********************************************************************/
2 
/* Filename   : gen_hw_looping.c                                    */
3 
/* Description: Generates top-level module for the hw_looping unit. */
4 
/* Author     : Nikolaos Kavvadias, <nkavv@physics.auth.gr>         */
5 
/* Date       : Friday, 09/04/2004                                  */
6 
/* Revision   : 09/02/2010: Created common.[c|h].                   */
7 
/********************************************************************/
8 
 
9 
#include <stdio.h>
10 
#include <stdlib.h>
11 
#include <time.h>
12 
#include "common.h"
13 
 
14 
#define PRINT_DEBUG
15 
 
16 
 
17 
// FUNCTION PROTOTYPES
18 
void write_file_hw_looping(FILE *outfile);
19 
 
20 
FILE *file_hw_looping; /* VHDL source for the top-level module of the
21 
                        * hw_looping unit (hw_looping.vhd) */
22 
 
23 
char hw_looping_file_name[32];
24 
int enable_nlp=0, enable_nodistrib=0;
25 
int nlp=1;
26 
time_t t;
27 
 
28 
 
29 
int main(int argc, char **argv)
30 
{
31 
  int i;
32 
  int gen_hw_looping_file;
33 
  char nlp_s[3];
34 
 
35 
  gen_hw_looping_file = 0;
36 
 
37 
  // Read input arguments
38 
  if (argc < 3)
39 
  {
40 
    printf("Usage: gen_hw_looping -nlp <num loops> [-nodistrib] <output base>\n");
41 
    printf("where:\n");
42 
    printf("-nlp <num>    = give number of supported loops (default = 1).\n");
43 
    printf("-nodistrib    = use vectors for data input ports.\n");
44 
    printf("<output base> = output file base name. The generated files will be named:\n");
45 
    printf("              \"<output base>_top.vhd\" for the top-level module.\n");
46 
    printf("\n");
47 
    exit(1);
48 
  }
49 
 
50 
  for (i = 1; i < argc; i++)
51 
  {
52 
    if (strcmp("-nodistrib",argv[i]) == 0)
53 
    {
54 
      enable_nodistrib = 1;
55 
    }
56 
    else if (strcmp("-nlp",argv[i]) == 0)
57 
    {
58 
      enable_nlp = 1;
59 
      if ((i+1) < argc)
60 
      {
61 
        i++;
62 
        nlp = atoi(argv[i]);
63 
      }
64 
    }
65 
    else //if (strcmp("-o",argv[i]) == 0)
66 
    {
67 
      if (i < argc)
68 
      {
69 
        sprintf(hw_looping_file_name,"%s_loops%d%s", argv[i], nlp, "_top.vhd");
70 
        gen_hw_looping_file = 1;
71 
      }
72 
    }
73 
  }
74 
 
75 
  // DEBUG OUTPUT
76 
#ifdef PRINT_DEBUG
77 
  printf("\n");
78 
  //
79 
  printf("nlp = %d\n",nlp);
80 
  printf("hw_looping_file_name = %s\n", hw_looping_file_name);
81 
  //
82 
#endif
83 
 
84 
  /*************************************************************/
85 
  /* Generate VHDL source for the top-level unit of hw_looping */
86 
  /*************************************************************/
87 
  if (gen_hw_looping_file == 1)
88 
  {
89 
    file_hw_looping = fopen(hw_looping_file_name,"w");
90 
    write_file_hw_looping(file_hw_looping);
91 
    fclose(file_hw_looping);
92 
  }
93 
 
94 
  return 0;
95 
}
96 
 
97 
void write_file_hw_looping(FILE *outfile)
98 
{
99 
  unsigned int i;
100 
 
101 
  // Get current time
102 
  time(&t);
103 
 
104 
  /* Generate interface for the VHDL file */
105 
  fprintf(outfile,"----==============================================================----\n");
106 
  fprintf(outfile,"----                                                              ----\n");
107 
  fprintf(outfile,"---- Filename: %s                                  ----\n", hw_looping_file_name);
108 
  fprintf(outfile,"---- Module description: Top-level file for the hw_looping unit.  ----\n");
109 
  fprintf(outfile,"----                     Also implements input and output         ----\n");
110 
  fprintf(outfile,"----                     wrapping operations.                     ----\n");
111 
  fprintf(outfile,"----                                                              ----\n");
112 
  fprintf(outfile,"---- Author: Nikolaos Kavvadias                                   ----\n");
113 
  fprintf(outfile,"----         nkavv@physics.auth.gr                                ----\n");
114 
  fprintf(outfile,"----                                                              ----\n");
115 
  fprintf(outfile,"----                                                              ----\n");
116 
  fprintf(outfile,"---- Part of the hwlu OPENCORES project generated automatically   ----\n");
117 
  fprintf(outfile,"---- with the use of the \"gen_hw_looping\" tool                    ----\n");
118 
  fprintf(outfile,"----                                                              ----\n");
119 
  fprintf(outfile,"---- To Do:                                                       ----\n");
120 
  fprintf(outfile,"----         Considered stable for the time being                 ----\n");
121 
  print_vhdl_header_common(outfile);
122 
 
123 
  /* Code generation for library inclusions */
124 
  fprintf(outfile,"library IEEE;\n");
125 
  fprintf(outfile,"use IEEE.std_logic_1164.all;\n");
126 
  fprintf(outfile,"\n");
127 
 
128 
  /* Generate entity declaration */
129 
  fprintf(outfile,"entity hw_looping is\n");
130 
  fprintf(outfile,"\tgeneric (\n");
131 
  fprintf(outfile,"\t\tNLP : integer := %d;\n", nlp);
132 
  fprintf(outfile,"\t\tDW  : integer := 8\n");
133 
  fprintf(outfile,"\t);\n");
134 
  fprintf(outfile,"\tport (\n");
135 
  fprintf(outfile,  "\t\tclk            : in std_logic;\n");
136 
  fprintf(outfile,  "\t\treset          : in std_logic;\n");
137 
  fprintf(outfile,  "\t\ttask_loop%d_end : in std_logic;\n", nlp);
138 
  //
139 
  if (enable_nodistrib == 1)
140 
  {
141 
    fprintf(outfile,"\t\tloop_count    : in std_logic_vector(NLP*DW-1 downto 0);\n");
142 
    fprintf(outfile,"\t\tindex         : out std_logic_vector(NLP*DW-1 downto 0);\n");
143 
  }
144 
  else
145 
  {
146 
    for (i=1; i<=nlp; i++)
147 
    {
148 
      fprintf(outfile,"\t\tloop%d_count    : in std_logic_vector(DW-1 downto 0);\n", i);
149 
    }
150 
    for (i=1; i<=nlp; i++)
151 
    {
152 
      fprintf(outfile,"\t\tindex%d         : out std_logic_vector(DW-1 downto 0);\n", i);
153 
    }
154 
  }
155 
  //
156 
  fprintf(outfile,  "\t\tloops_end      : out std_logic\n");
157 
  //
158 
  fprintf(outfile,"\t);\n");
159 
  fprintf(outfile,"end hw_looping;\n");
160 
  fprintf(outfile,"\n");
161 
 
162 
  /* Generate architecture declaration */
163 
  fprintf(outfile,"architecture structural of hw_looping is\n");
164 
 
165 
  /* Add component declarations here if needed */
166 
  fprintf(outfile,"--\n");
167 
  fprintf(outfile,"-- Component declarations\n");
168 
  fprintf(outfile,"component cmpeq\n");
169 
  fprintf(outfile,"\tgeneric (\n");
170 
  fprintf(outfile,"\t\tDW : integer := 8\n");
171 
  fprintf(outfile,"\t);\n");
172 
  fprintf(outfile,"\tport (\n");
173 
  fprintf(outfile,"\t\ta      : in std_logic_vector(DW-1 downto 0);\n");
174 
  fprintf(outfile,"\t\tb      : in std_logic_vector(DW-1 downto 0);\n");
175 
  fprintf(outfile,"\t\treset  : in std_logic;\n");
176 
  fprintf(outfile,"\t\ta_eq_b : out std_logic\n");
177 
  fprintf(outfile,"\t);\n");
178 
  fprintf(outfile,"end component;\n");
179 
  //
180 
  fprintf(outfile,"--\n");
181 
  fprintf(outfile,"component index_inc\n");
182 
  fprintf(outfile,"\tgeneric (\n");
183 
  fprintf(outfile,"\t\tDW : integer := 8\n");
184 
  fprintf(outfile,"\t);\n");
185 
  fprintf(outfile,"\tport (\n");
186 
  fprintf(outfile,"\t\tclk            : in std_logic;\n");
187 
  fprintf(outfile,"\t\treset          : in std_logic;\n");
188 
  fprintf(outfile,"\t\tinc_en         : in std_logic;\n");
189 
  fprintf(outfile,"\t\tindex_plus_one : out std_logic_vector(DW-1 downto 0);\n");
190 
  fprintf(outfile,"\t\tindex_out      : out std_logic_vector(DW-1 downto 0)\n");
191 
  fprintf(outfile,"\t);\n");
192 
  fprintf(outfile,"end component;\n");
193 
  //
194 
  fprintf(outfile,"--\n");
195 
  fprintf(outfile,"component priority_encoder\n");
196 
  fprintf(outfile,"\tgeneric (\n");
197 
  fprintf(outfile,"\t\tNLP : integer := 5\n");
198 
  fprintf(outfile,"\t);\n");
199 
  fprintf(outfile,"\tport (\n");
200 
  fprintf(outfile,"\t\tflag           : in std_logic_vector(NLP-1 downto 0);\n");
201 
  fprintf(outfile,"\t\ttask_loop%d_end : in std_logic;\n", nlp);
202 
  fprintf(outfile,"\t\tincl           : out std_logic_vector(NLP-1 downto 0);\n");
203 
  fprintf(outfile,"\t\treset_vct      : out std_logic_vector(NLP-1 downto 0);\n");
204 
  fprintf(outfile,"\t\tloops_end      : out std_logic\n");
205 
  fprintf(outfile,"\t);\n");
206 
  fprintf(outfile,"end component;\n");
207 
 
208 
  /* Add signal declarations here if needed */
209 
  fprintf(outfile,"--\n");
210 
  fprintf(outfile,"-- Signal declarations\n");
211 
  // flag
212 
  fprintf(outfile,"signal flag                : std_logic_vector(NLP-1 downto 0);\n");
213 
  // incl
214 
  fprintf(outfile,"signal incl                : std_logic_vector(NLP-1 downto 0);\n");
215 
  // temp_loop_count
216 
  fprintf(outfile,"signal temp_loop_count     : std_logic_vector(NLP*DW-1 downto 0);\n");
217 
  // temp_index
218 
  fprintf(outfile,"signal temp_index          : std_logic_vector(NLP*DW-1 downto 0);\n");
219 
  // temp_index_plus_one
220 
  fprintf(outfile,"signal temp_index_plus_one : std_logic_vector(NLP*DW-1 downto 0);\n");
221 
  // temp_vct_penc
222 
  fprintf(outfile,"signal reset_vct_penc      : std_logic_vector(NLP-1 downto 0);\n");
223 
  // temp_index
224 
  fprintf(outfile,"signal reset_vct_ix        : std_logic_vector(NLP-1 downto 0);\n");
225 
  fprintf(outfile,"--\n");
226 
 
227 
  /* Continue with the rest of the architecture declaration */
228 
  fprintf(outfile,"begin\n");
229 
  fprintf(outfile,"\n");
230 
 
231 
  /***************************************/
232 
  /* GENERATE INPUT WRAPPING ASSIGNMENTS */
233 
  /***************************************/
234 
 
235 
  if (enable_nodistrib == 1)
236 
  {
237 
    fprintf(outfile,"\ttemp_loop_count <= loop_count;\n");
238 
  }
239 
  else
240 
  {
241 
    /* Iterate through all loops */
242 
    for (i=1; i<=nlp; i++)
243 
    {
244 
      /* Generate assignment code */
245 
      fprintf(outfile,"\ttemp_loop_count( ((NLP-%d)*DW-1) downto ((NLP-%d)*DW) ) <= loop%d_count;\n",
246 
            i-1, i, i);
247 
    }
248 
  }
249 
  fprintf(outfile,"\n");
250 
 
251 
  /***************************************/
252 
  /* GENERATE INTERNAL HW_LOOPING MODULE */
253 
  /***************************************/
254 
 
255 
  // Generate cmpeq modules
256 
  fprintf(outfile,"\tGEN_COMPARATORS: for i in 0 to NLP-1 generate\n");
257 
  fprintf(outfile,"\t\tU_cmp : cmpeq\n");
258 
  fprintf(outfile,"\t\t\tgeneric map (\n");
259 
  fprintf(outfile,"\t\t\t\tDW => DW\n");
260 
  fprintf(outfile,"\t\t\t)\n");
261 
  fprintf(outfile,"\t\t\tport map (\n");
262 
  fprintf(outfile,"\t\t\t\ta => temp_index_plus_one( ((i+1)*DW-1) downto (i*DW) ),\n");
263 
  fprintf(outfile,"\t\t\t\tb => temp_loop_count( ((i+1)*DW-1) downto (i*DW) ),\n");
264 
  fprintf(outfile,"\t\t\t\treset => reset,\n");
265 
  fprintf(outfile,"\t\t\t\ta_eq_b => flag(i)\n");
266 
  fprintf(outfile,"\t\t\t);\n");
267 
  fprintf(outfile,"\tend generate GEN_COMPARATORS;\n");
268 
  fprintf(outfile,"\n");
269 
 
270 
  // Generate priority encoder
271 
  fprintf(outfile,"\tU_priority_enc : priority_encoder\n");
272 
  fprintf(outfile,"\t\tgeneric map (\n");
273 
  fprintf(outfile,"\t\t\tNLP => NLP\n");
274 
  fprintf(outfile,"\t\t)\n");
275 
  fprintf(outfile,"\t\tport map (\n");
276 
  fprintf(outfile,"\t\t\tflag => flag,\n");
277 
  fprintf(outfile,"\t\t\ttask_loop%d_end => task_loop%d_end,\n", nlp, nlp);
278 
  fprintf(outfile,"\t\t\tincl => incl,\n");
279 
  fprintf(outfile,"\t\t\treset_vct => reset_vct_penc,\n");
280 
  fprintf(outfile,"\t\t\tloops_end => loops_end\n");
281 
  fprintf(outfile,"\t\t);\n");
282 
  fprintf(outfile,"\n");
283 
 
284 
  // Generate reset_vct_ix
285 
  fprintf(outfile,"\tGEN_RESET_SEL: for i in 0 to NLP-1 generate\n");
286 
  fprintf(outfile,"\t\treset_vct_ix(i) <= reset_vct_penc(i) or reset;\n");
287 
  fprintf(outfile,"\tend generate GEN_RESET_SEL;\n");
288 
  fprintf(outfile,"\n");
289 
 
290 
  // Generate index_inc modules
291 
  fprintf(outfile,"\tGEN_INC_IX: for i in 0 to NLP-1 generate\n");
292 
  fprintf(outfile,"\t\tU_inc_ix1 : index_inc\n");
293 
  fprintf(outfile,"\t\t\tgeneric map (\n");
294 
  fprintf(outfile,"\t\t\t\tDW => DW\n");
295 
  fprintf(outfile,"\t\t\t)\n");
296 
  fprintf(outfile,"\t\t\tport map (\n");
297 
  fprintf(outfile,"\t\t\t\tclk => clk,\n");
298 
  fprintf(outfile,"\t\t\t\treset => reset_vct_ix(i),\n");
299 
  fprintf(outfile,"\t\t\t\tinc_en => incl(i),\n");
300 
  fprintf(outfile,"\t\t\t\tindex_plus_one => temp_index_plus_one( ((i+1)*DW-1) downto (i*DW) ),\n");
301 
  fprintf(outfile,"\t\t\t\tindex_out => temp_index( ((i+1)*DW-1) downto (i*DW) )\n");
302 
  fprintf(outfile,"\t\t\t);\n");
303 
  fprintf(outfile,"\tend generate GEN_INC_IX;\n");
304 
  fprintf(outfile,"\n");
305 
 
306 
  /****************************************/
307 
  /* GENERATE OUTPUT WRAPPING ASSIGNMENTS */
308 
  /****************************************/
309 
 
310 
  if (enable_nodistrib == 1)
311 
  {
312 
    fprintf(outfile,"\ttemp_loop_count <= loop_count;\n");
313 
  }
314 
  else
315 
  {
316 
    /* Iterate through all loops */
317 
    for (i=1; i<=nlp; i++)
318 
    {
319 
      /* Generate assignment code */
320 
      fprintf(outfile,"\tindex%d <= temp_index( ((NLP-%d)*DW-1) downto ((NLP-%d)*DW) );\n", i, i-1, i);
321 
    }
322 
  }
323 
  fprintf(outfile,"\n");
324 
  fprintf(outfile,"end structural;\n");
325 
}

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