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/********************************************************************/
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/* Filename : gen_hw_looping.c */
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/* Description: Generates top-level module for the hw_looping unit. */
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/* Author : Nikolaos Kavvadias, <nkavv@physics.auth.gr> */
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/* Date : Friday, 09/04/2004 */
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/* Revision : 09/02/2010: Created common.[c|h]. */
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/********************************************************************/
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#include <stdio.h>
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#include <stdlib.h>
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#include <time.h>
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#include "common.h"
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#define PRINT_DEBUG
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// FUNCTION PROTOTYPES
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void write_file_hw_looping(FILE *outfile);
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FILE *file_hw_looping; /* VHDL source for the top-level module of the
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* hw_looping unit (hw_looping.vhd) */
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char hw_looping_file_name[32];
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int enable_nlp=0, enable_nodistrib=0;
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int nlp=1;
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time_t t;
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int main(int argc, char **argv)
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{
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int i;
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int gen_hw_looping_file;
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char nlp_s[3];
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gen_hw_looping_file = 0;
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// Read input arguments
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if (argc < 3)
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{
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printf("Usage: gen_hw_looping -nlp <num loops> [-nodistrib] <output base>\n");
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printf("where:\n");
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printf("-nlp <num> = give number of supported loops (default = 1).\n");
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printf("-nodistrib = use vectors for data input ports.\n");
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printf("<output base> = output file base name. The generated files will be named:\n");
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printf(" \"<output base>_top.vhd\" for the top-level module.\n");
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printf("\n");
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exit(1);
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}
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for (i = 1; i < argc; i++)
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{
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if (strcmp("-nodistrib",argv[i]) == 0)
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{
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enable_nodistrib = 1;
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}
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else if (strcmp("-nlp",argv[i]) == 0)
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{
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enable_nlp = 1;
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if ((i+1) < argc)
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{
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i++;
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nlp = atoi(argv[i]);
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}
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}
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else //if (strcmp("-o",argv[i]) == 0)
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{
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if (i < argc)
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{
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sprintf(hw_looping_file_name,"%s_loops%d%s", argv[i], nlp, "_top.vhd");
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gen_hw_looping_file = 1;
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}
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}
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}
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// DEBUG OUTPUT
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#ifdef PRINT_DEBUG
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printf("\n");
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//
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printf("nlp = %d\n",nlp);
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printf("hw_looping_file_name = %s\n", hw_looping_file_name);
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//
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#endif
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/*************************************************************/
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/* Generate VHDL source for the top-level unit of hw_looping */
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/*************************************************************/
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if (gen_hw_looping_file == 1)
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{
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file_hw_looping = fopen(hw_looping_file_name,"w");
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write_file_hw_looping(file_hw_looping);
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fclose(file_hw_looping);
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}
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return 0;
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}
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void write_file_hw_looping(FILE *outfile)
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{
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unsigned int i;
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// Get current time
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time(&t);
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/* Generate interface for the VHDL file */
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fprintf(outfile,"----==============================================================----\n");
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fprintf(outfile,"---- ----\n");
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fprintf(outfile,"---- Filename: %s ----\n", hw_looping_file_name);
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fprintf(outfile,"---- Module description: Top-level file for the hw_looping unit. ----\n");
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fprintf(outfile,"---- Also implements input and output ----\n");
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fprintf(outfile,"---- wrapping operations. ----\n");
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fprintf(outfile,"---- ----\n");
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fprintf(outfile,"---- Author: Nikolaos Kavvadias ----\n");
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fprintf(outfile,"---- nkavv@physics.auth.gr ----\n");
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fprintf(outfile,"---- ----\n");
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fprintf(outfile,"---- ----\n");
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fprintf(outfile,"---- Part of the hwlu OPENCORES project generated automatically ----\n");
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fprintf(outfile,"---- with the use of the \"gen_hw_looping\" tool ----\n");
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fprintf(outfile,"---- ----\n");
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fprintf(outfile,"---- To Do: ----\n");
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fprintf(outfile,"---- Considered stable for the time being ----\n");
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print_vhdl_header_common(outfile);
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/* Code generation for library inclusions */
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fprintf(outfile,"library IEEE;\n");
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fprintf(outfile,"use IEEE.std_logic_1164.all;\n");
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fprintf(outfile,"\n");
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/* Generate entity declaration */
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fprintf(outfile,"entity hw_looping is\n");
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fprintf(outfile,"\tgeneric (\n");
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fprintf(outfile,"\t\tNLP : integer := %d;\n", nlp);
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fprintf(outfile,"\t\tDW : integer := 8\n");
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fprintf(outfile,"\t);\n");
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fprintf(outfile,"\tport (\n");
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fprintf(outfile, "\t\tclk : in std_logic;\n");
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fprintf(outfile, "\t\treset : in std_logic;\n");
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fprintf(outfile, "\t\ttask_loop%d_end : in std_logic;\n", nlp);
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//
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if (enable_nodistrib == 1)
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{
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fprintf(outfile,"\t\tloop_count : in std_logic_vector(NLP*DW-1 downto 0);\n");
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fprintf(outfile,"\t\tindex : out std_logic_vector(NLP*DW-1 downto 0);\n");
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}
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else
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{
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for (i=1; i<=nlp; i++)
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{
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fprintf(outfile,"\t\tloop%d_count : in std_logic_vector(DW-1 downto 0);\n", i);
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}
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for (i=1; i<=nlp; i++)
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{
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fprintf(outfile,"\t\tindex%d : out std_logic_vector(DW-1 downto 0);\n", i);
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}
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}
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//
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fprintf(outfile, "\t\tloops_end : out std_logic\n");
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//
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fprintf(outfile,"\t);\n");
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fprintf(outfile,"end hw_looping;\n");
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fprintf(outfile,"\n");
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/* Generate architecture declaration */
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fprintf(outfile,"architecture structural of hw_looping is\n");
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/* Add component declarations here if needed */
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fprintf(outfile,"--\n");
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fprintf(outfile,"-- Component declarations\n");
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fprintf(outfile,"component cmpeq\n");
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fprintf(outfile,"\tgeneric (\n");
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fprintf(outfile,"\t\tDW : integer := 8\n");
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fprintf(outfile,"\t);\n");
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fprintf(outfile,"\tport (\n");
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fprintf(outfile,"\t\ta : in std_logic_vector(DW-1 downto 0);\n");
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fprintf(outfile,"\t\tb : in std_logic_vector(DW-1 downto 0);\n");
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fprintf(outfile,"\t\treset : in std_logic;\n");
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fprintf(outfile,"\t\ta_eq_b : out std_logic\n");
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fprintf(outfile,"\t);\n");
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fprintf(outfile,"end component;\n");
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//
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fprintf(outfile,"--\n");
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fprintf(outfile,"component index_inc\n");
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fprintf(outfile,"\tgeneric (\n");
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fprintf(outfile,"\t\tDW : integer := 8\n");
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fprintf(outfile,"\t);\n");
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fprintf(outfile,"\tport (\n");
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fprintf(outfile,"\t\tclk : in std_logic;\n");
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fprintf(outfile,"\t\treset : in std_logic;\n");
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fprintf(outfile,"\t\tinc_en : in std_logic;\n");
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fprintf(outfile,"\t\tindex_plus_one : out std_logic_vector(DW-1 downto 0);\n");
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fprintf(outfile,"\t\tindex_out : out std_logic_vector(DW-1 downto 0)\n");
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fprintf(outfile,"\t);\n");
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fprintf(outfile,"end component;\n");
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//
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fprintf(outfile,"--\n");
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fprintf(outfile,"component priority_encoder\n");
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fprintf(outfile,"\tgeneric (\n");
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fprintf(outfile,"\t\tNLP : integer := 5\n");
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fprintf(outfile,"\t);\n");
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fprintf(outfile,"\tport (\n");
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fprintf(outfile,"\t\tflag : in std_logic_vector(NLP-1 downto 0);\n");
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fprintf(outfile,"\t\ttask_loop%d_end : in std_logic;\n", nlp);
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fprintf(outfile,"\t\tincl : out std_logic_vector(NLP-1 downto 0);\n");
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fprintf(outfile,"\t\treset_vct : out std_logic_vector(NLP-1 downto 0);\n");
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fprintf(outfile,"\t\tloops_end : out std_logic\n");
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fprintf(outfile,"\t);\n");
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fprintf(outfile,"end component;\n");
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/* Add signal declarations here if needed */
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fprintf(outfile,"--\n");
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fprintf(outfile,"-- Signal declarations\n");
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// flag
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fprintf(outfile,"signal flag : std_logic_vector(NLP-1 downto 0);\n");
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// incl
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fprintf(outfile,"signal incl : std_logic_vector(NLP-1 downto 0);\n");
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// temp_loop_count
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fprintf(outfile,"signal temp_loop_count : std_logic_vector(NLP*DW-1 downto 0);\n");
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// temp_index
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fprintf(outfile,"signal temp_index : std_logic_vector(NLP*DW-1 downto 0);\n");
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// temp_index_plus_one
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fprintf(outfile,"signal temp_index_plus_one : std_logic_vector(NLP*DW-1 downto 0);\n");
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// temp_vct_penc
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fprintf(outfile,"signal reset_vct_penc : std_logic_vector(NLP-1 downto 0);\n");
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// temp_index
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fprintf(outfile,"signal reset_vct_ix : std_logic_vector(NLP-1 downto 0);\n");
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fprintf(outfile,"--\n");
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/* Continue with the rest of the architecture declaration */
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fprintf(outfile,"begin\n");
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fprintf(outfile,"\n");
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/***************************************/
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/* GENERATE INPUT WRAPPING ASSIGNMENTS */
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/***************************************/
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if (enable_nodistrib == 1)
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{
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fprintf(outfile,"\ttemp_loop_count <= loop_count;\n");
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}
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else
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{
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/* Iterate through all loops */
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for (i=1; i<=nlp; i++)
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{
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/* Generate assignment code */
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fprintf(outfile,"\ttemp_loop_count( ((NLP-%d)*DW-1) downto ((NLP-%d)*DW) ) <= loop%d_count;\n",
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i-1, i, i);
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}
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}
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fprintf(outfile,"\n");
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/***************************************/
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/* GENERATE INTERNAL HW_LOOPING MODULE */
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/***************************************/
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// Generate cmpeq modules
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fprintf(outfile,"\tGEN_COMPARATORS: for i in 0 to NLP-1 generate\n");
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fprintf(outfile,"\t\tU_cmp : cmpeq\n");
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fprintf(outfile,"\t\t\tgeneric map (\n");
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fprintf(outfile,"\t\t\t\tDW => DW\n");
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fprintf(outfile,"\t\t\t)\n");
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fprintf(outfile,"\t\t\tport map (\n");
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fprintf(outfile,"\t\t\t\ta => temp_index_plus_one( ((i+1)*DW-1) downto (i*DW) ),\n");
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fprintf(outfile,"\t\t\t\tb => temp_loop_count( ((i+1)*DW-1) downto (i*DW) ),\n");
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fprintf(outfile,"\t\t\t\treset => reset,\n");
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fprintf(outfile,"\t\t\t\ta_eq_b => flag(i)\n");
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fprintf(outfile,"\t\t\t);\n");
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fprintf(outfile,"\tend generate GEN_COMPARATORS;\n");
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fprintf(outfile,"\n");
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// Generate priority encoder
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fprintf(outfile,"\tU_priority_enc : priority_encoder\n");
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fprintf(outfile,"\t\tgeneric map (\n");
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fprintf(outfile,"\t\t\tNLP => NLP\n");
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fprintf(outfile,"\t\t)\n");
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fprintf(outfile,"\t\tport map (\n");
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fprintf(outfile,"\t\t\tflag => flag,\n");
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fprintf(outfile,"\t\t\ttask_loop%d_end => task_loop%d_end,\n", nlp, nlp);
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fprintf(outfile,"\t\t\tincl => incl,\n");
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fprintf(outfile,"\t\t\treset_vct => reset_vct_penc,\n");
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fprintf(outfile,"\t\t\tloops_end => loops_end\n");
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fprintf(outfile,"\t\t);\n");
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fprintf(outfile,"\n");
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// Generate reset_vct_ix
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fprintf(outfile,"\tGEN_RESET_SEL: for i in 0 to NLP-1 generate\n");
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fprintf(outfile,"\t\treset_vct_ix(i) <= reset_vct_penc(i) or reset;\n");
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fprintf(outfile,"\tend generate GEN_RESET_SEL;\n");
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fprintf(outfile,"\n");
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// Generate index_inc modules
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fprintf(outfile,"\tGEN_INC_IX: for i in 0 to NLP-1 generate\n");
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fprintf(outfile,"\t\tU_inc_ix1 : index_inc\n");
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fprintf(outfile,"\t\t\tgeneric map (\n");
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fprintf(outfile,"\t\t\t\tDW => DW\n");
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fprintf(outfile,"\t\t\t)\n");
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fprintf(outfile,"\t\t\tport map (\n");
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fprintf(outfile,"\t\t\t\tclk => clk,\n");
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fprintf(outfile,"\t\t\t\treset => reset_vct_ix(i),\n");
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fprintf(outfile,"\t\t\t\tinc_en => incl(i),\n");
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fprintf(outfile,"\t\t\t\tindex_plus_one => temp_index_plus_one( ((i+1)*DW-1) downto (i*DW) ),\n");
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fprintf(outfile,"\t\t\t\tindex_out => temp_index( ((i+1)*DW-1) downto (i*DW) )\n");
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fprintf(outfile,"\t\t\t);\n");
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fprintf(outfile,"\tend generate GEN_INC_IX;\n");
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fprintf(outfile,"\n");
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/****************************************/
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/* GENERATE OUTPUT WRAPPING ASSIGNMENTS */
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/****************************************/
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|
310 |
|
|
if (enable_nodistrib == 1)
|
311 |
|
|
{
|
312 |
|
|
fprintf(outfile,"\ttemp_loop_count <= loop_count;\n");
|
313 |
|
|
}
|
314 |
|
|
else
|
315 |
|
|
{
|
316 |
|
|
/* Iterate through all loops */
|
317 |
|
|
for (i=1; i<=nlp; i++)
|
318 |
|
|
{
|
319 |
|
|
/* Generate assignment code */
|
320 |
|
|
fprintf(outfile,"\tindex%d <= temp_index( ((NLP-%d)*DW-1) downto ((NLP-%d)*DW) );\n", i, i-1, i);
|
321 |
|
|
}
|
322 |
|
|
}
|
323 |
|
|
fprintf(outfile,"\n");
|
324 |
|
|
fprintf(outfile,"end structural;\n");
|
325 |
|
|
}
|