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[/] [i2c/] [trunk/] [bench/] [verilog/] [spi_slave_model.v] - Blame information for rev 72

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/////////////////////////////////////////////////////////////////////
////                                                             ////
////  SPI Slave Model                                            ////
////                                                             ////
////                                                             ////
////  Authors: Richard Herveille (richard@asics.ws) www.asics.ws ////
////                                                             ////
////  http://www.opencores.org/projects/simple_spi/              ////
////                                                             ////
/////////////////////////////////////////////////////////////////////
////                                                             ////
//// Copyright (C) 2004 Richard Herveille                        ////
////                         richard@asics.ws                    ////
////                                                             ////
//// This source file may be used and distributed without        ////
//// restriction provided that this copyright statement is not   ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer.////
////                                                             ////
////     THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY     ////
//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED   ////
//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS   ////
//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR      ////
//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,         ////
//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES    ////
//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE   ////
//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR        ////
//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF  ////
//// LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT  ////
//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT  ////
//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE         ////
//// POSSIBILITY OF SUCH DAMAGE.                                 ////
////                                                             ////
/////////////////////////////////////////////////////////////////////
 
//  CVS Log
//
//  $Id: spi_slave_model.v,v 1.1 2004-02-28 15:32:54 rherveille Exp $
//
//  $Date: 2004-02-28 15:32:54 $
//  $Revision: 1.1 $
//  $Author: rherveille $
//  $Locker:  $
//  $State: Exp $
//
// Change History:
//               $Log: not supported by cvs2svn $
//
//
 
 
// Requires: Verilog2001
 
`include "timescale.v"
 
module spi_slave_model (
        input  wire csn;
        input  wire sck
        input  wire di;
        output wire do
);
 
        //
        // Variable declaration
        //
        wire debug = 1'b1;
 
        wire cpol = 1'b0;
        wire cpha  = 1'b0;
 
        reg [7:0] mem [7:0]; // initiate memory
        reg [2:0] mem_adr;   // memory address
        reg [7:0] mem_do;    // memory data output
 
        reg [7:0] sri, sro;  // 8bit shift register
 
        reg [2:0] bit_cnt;
        reg       ld;
 
        wire clk;
 
        //
        // module body
        //
 
        assign clk = cpol ^ cpha ^ sck;
 
        // generate shift registers
        always @(posedge clk)
          sri <= #1 {sri[6:0],di};
 
        always @(posedge clk)
          if (&bit_cnt)
            sro <= #1 mem[mem_adr];
          else
            sro <= #1 {sro[6:0],1'bx};
 
        assign do = sro[7];
 
        //generate bit-counter
        always @(posedge clk, posedge csn)
          if(csn)
            bit_cnt <= #1 3'b111;
          else
            bit_cnt <= #1 bit_cnt - 3'h1;
 
        //generate access done signal
        always @(posedge clk)
          ld <= #1 ~(|bit_cnt);
 
        always @(negedge clk)
          if (ld) begin
            mem[mem_adr] <= #1 sri;
            mem_adr      <= #1 mem_adr + 1'b1;
          end
 
        initial
        begin
          bit_cnt=3'b111;
          mem_adr = 0;
          sro = mem[mem_adr];
        end
endmodule
 
 

Line No.	Rev	Author	Line
1	49	rherveille	`/////////////////////////////////////////////////////////////////////`
2			`//// ////`
3			`//// SPI Slave Model ////`
4			`//// ////`
5			`//// ////`
6			`//// Authors: Richard Herveille (richard@asics.ws) www.asics.ws ////`
7			`//// ////`
8			`//// http://www.opencores.org/projects/simple_spi/ ////`
9			`//// ////`
10			`/////////////////////////////////////////////////////////////////////`
11			`//// ////`
12			`//// Copyright (C) 2004 Richard Herveille ////`
13			`//// richard@asics.ws ////`
14			`//// ////`
15			`//// This source file may be used and distributed without ////`
16			`//// restriction provided that this copyright statement is not ////`
17			`//// removed from the file and that any derivative work contains ////`
18			`//// the original copyright notice and the associated disclaimer.////`
19			`//// ////`
20			//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY ////
21			`//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED ////`
22			`//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ////`
23			`//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR ////`
24			`//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ////`
25			`//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ////`
26			`//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE ////`
27			`//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR ////`
28			`//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ////`
29			`//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ////`
30			`//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT ////`
31			`//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ////`
32			`//// POSSIBILITY OF SUCH DAMAGE. ////`
33			`//// ////`
34			`/////////////////////////////////////////////////////////////////////`
35
36			`// CVS Log`
37			`//`
38			`// $Id: spi_slave_model.v,v 1.1 2004-02-28 15:32:54 rherveille Exp $`
39			`//`
40			`// $Date: 2004-02-28 15:32:54 $`
41			`// $Revision: 1.1 $`
42			`// $Author: rherveille $`
43			`// $Locker: $`
44			`// $State: Exp $`
45			`//`
46			`// Change History:`
47			`// $Log: not supported by cvs2svn $`
48			`//`
49			`//`
50
51
52			`// Requires: Verilog2001`
53
54			`include "timescale.v"
55
56			`module spi_slave_model (`
57			`input wire csn;`
58			`input wire sck`
59			`input wire di;`
60			`output wire do`
61			`);`
62
63			`//`
64			`// Variable declaration`
65			`//`
66			`wire debug = 1'b1;`
67
68			`wire cpol = 1'b0;`
69			`wire cpha = 1'b0;`
70
71			`reg [7:0] mem [7:0]; // initiate memory`
72			`reg [2:0] mem_adr; // memory address`
73			`reg [7:0] mem_do; // memory data output`
74
75			`reg [7:0] sri, sro; // 8bit shift register`
76
77			`reg [2:0] bit_cnt;`
78			`reg ld;`
79
80			`wire clk;`
81
82			`//`
83			`// module body`
84			`//`
85
86			`assign clk = cpol ^ cpha ^ sck;`
87
88			`// generate shift registers`
89			`always @(posedge clk)`
90			`sri <= #1 {sri[6:0],di};`
91
92			`always @(posedge clk)`
93			`if (&bit_cnt)`
94			`sro <= #1 mem[mem_adr];`
95			`else`
96			`sro <= #1 {sro[6:0],1'bx};`
97
98			`assign do = sro[7];`
99
100			`//generate bit-counter`
101			`always @(posedge clk, posedge csn)`
102			`if(csn)`
103			`bit_cnt <= #1 3'b111;`
104			`else`
105			`bit_cnt <= #1 bit_cnt - 3'h1;`
106
107			`//generate access done signal`
108			`always @(posedge clk)`
109			`ld <= #1 ~(\|bit_cnt);`
110
111			`always @(negedge clk)`
112			`if (ld) begin`
113			`mem[mem_adr] <= #1 sri;`
114			`mem_adr <= #1 mem_adr + 1'b1;`
115			`end`
116
117			`initial`
118			`begin`
119			`bit_cnt=3'b111;`
120			`mem_adr = 0;`
121			`sro = mem[mem_adr];`
122			`end`
123			`endmodule`
124
125

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[/] [i2c/] [trunk/] [bench/] [verilog/] [spi_slave_model.v] - Blame information for rev 72