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/////////////////////////////////////////////////////////////////////
////                                                             ////
////  WISHBONE rev.B2 compliant I2C Master controller Testbench  ////
////                                                             ////
////                                                             ////
////  Author: Richard Herveille                                  ////
////          richard@asics.ws                                   ////
////          www.asics.ws                                       ////
////                                                             ////
////  Downloaded from: http://www.opencores.org/projects/i2c/    ////
////                                                             ////
/////////////////////////////////////////////////////////////////////
////                                                             ////
//// Copyright (C) 2001 Richard Herveille                        ////
////                    richard@asics.ws                         ////
////                                                             ////
//// This source file may be used and distributed without        ////
//// restriction provided that this copyright statement is not   ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer.////
////                                                             ////
////     THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY     ////
//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED   ////
//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS   ////
//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR      ////
//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,         ////
//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES    ////
//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE   ////
//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR        ////
//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF  ////
//// LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT  ////
//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT  ////
//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE         ////
//// POSSIBILITY OF SUCH DAMAGE.                                 ////
////                                                             ////
/////////////////////////////////////////////////////////////////////
 
//  CVS Log
//
//  $Id: tst_bench_top.v,v 1.3 2002-10-30 18:11:06 rherveille Exp $
//
//  $Date: 2002-10-30 18:11:06 $
//  $Revision: 1.3 $
//  $Author: rherveille $
//  $Locker:  $
//  $State: Exp $
//
// Change History:
//               $Log: not supported by cvs2svn $
//               Revision 1.2  2002/03/17 10:26:38  rherveille
//               Fixed some race conditions in the i2c-slave model.
//               Added debug information.
//               Added headers.
//
 
`include "timescale.v"
 
module tst_bench_top();
 
        //
        // wires && regs
        //
        reg  clk;
        reg  rstn;
 
        wire [31:0] adr;
        wire [ 7:0] dat_i, dat_o;
        wire we;
        wire stb;
        wire cyc;
        wire ack;
        wire inta;
 
        reg [7:0] q, qq;
 
        wire scl, scl_o, scl_oen;
        wire sda, sda_o, sda_oen;
 
        parameter PRER_LO = 3'b000;
        parameter PRER_HI = 3'b001;
        parameter CTR     = 3'b010;
        parameter RXR     = 3'b011;
        parameter TXR     = 3'b011;
        parameter CR      = 3'b100;
        parameter SR      = 3'b100;
 
        parameter TXR_R   = 3'b101; // undocumented / reserved output
        parameter CR_R    = 3'b110; // undocumented / reserved output
 
        //
        // Module body
        //
 
        // generate clock
        always #5 clk = ~clk;
 
        // hookup wishbone master model
        wb_master_model #(8, 32) u0 (
                .clk(clk),
                .rst(rstn),
                .adr(adr),
                .din(dat_i),
                .dout(dat_o),
                .cyc(cyc),
                .stb(stb),
                .we(we),
                .sel(),
                .ack(ack),
                .err(1'b0),
                .rty(1'b0)
        );
 
        // hookup wishbone_i2c_master core
        i2c_master_top i2c_top (
 
                // wishbone interface
                .wb_clk_i(clk),
                .wb_rst_i(1'b0),
                .arst_i(rstn),
                .wb_adr_i(adr[2:0]),
                .wb_dat_i(dat_o),
                .wb_dat_o(dat_i),
                .wb_we_i(we),
                .wb_stb_i(stb),
                .wb_cyc_i(cyc),
                .wb_ack_o(ack),
                .wb_inta_o(inta),
 
                // i2c signals
                .scl_pad_i(scl),
                .scl_pad_o(scl_o),
                .scl_padoen_o(scl_oen),
                .sda_pad_i(sda),
                .sda_pad_o(sda_o),
                .sda_padoen_o(sda_oen)
        );
 
        // hookup i2c slave model
        i2c_slave_model #(7'b1010_000) i2c_slave (
                .scl(scl),
                .sda(sda)
        );
 
        // create i2c lines
        assign scl = scl_oen ? 1'bz : scl_o; // create tri-state buffer for i2c_master scl line
        assign sda = sda_oen ? 1'bz : sda_o; // create tri-state buffer for i2c_master sda line
 
        pullup p1(scl); // pullup scl line
        pullup p2(sda); // pullup sda line
 
        initial
          begin
              `ifdef WAVES
                 $shm_open("waves");
                 $shm_probe("AS",tst_bench_top,"AS");
                 $display("INFO: Signal dump enabled ...\n\n");
              `endif
 
//            force i2c_slave.debug = 1'b1; // enable i2c_slave debug information
              force i2c_slave.debug = 1'b0; // disable i2c_slave debug information
 
              $display("\nstatus: %t Testbench started\n\n", $time);
 
//            $dumpfile("bench.vcd");
//            $dumpvars(1, tst_bench_top);
//            $dumpvars(1, tst_bench_top.i2c_slave);
 
              // initially values
              clk = 0;
 
              // reset system
              rstn = 1'b1; // negate reset
              #2;
              rstn = 1'b0; // assert reset
              repeat(20) @(posedge clk);
              rstn = 1'b1; // negate reset
 
              $display("status: %t done reset", $time);
 
              @(posedge clk);
 
              //
              // program core
              //
 
              // program internal registers
//            u0.wb_write(1, PRER_LO, 8'hfa); // load prescaler lo-byte
              u0.wb_write(1, PRER_LO, 8'hc8); // load prescaler lo-byte
              u0.wb_write(1, PRER_HI, 8'h00); // load prescaler hi-byte
              $display("status: %t programmed registers", $time);
 
              u0.wb_cmp(0, PRER_LO, 8'hc8); // verify prescaler lo-byte
              u0.wb_cmp(0, PRER_HI, 8'h00); // verify prescaler hi-byte
              $display("status: %t verified registers", $time);
 
              u0.wb_write(1, CTR,     8'h80); // enable core
              $display("status: %t core enabled", $time);
 
              //
              // access slave (write)
              //
 
              // drive slave address
              u0.wb_write(1, TXR,     8'ha0); // present slave address, set write-bit (== !read)
              u0.wb_write(0, CR,      8'h90); // set command (start, write)
              $display("status: %t generate 'start', write cmd a0 (slave address+write)", $time);
 
              // check tip bit
              u0.wb_read(1, SR, q);
              while(q[1])
                   u0.wb_read(0, SR, q); // poll it until it is zero
              $display("status: %t tip==0", $time);
 
              // send memory address
              u0.wb_write(1, TXR,     8'h01); // present slave's memory address
              u0.wb_write(0, CR,      8'h10); // set command (write)
              $display("status: %t write slave memory address 01", $time);
 
              // check tip bit
              u0.wb_read(1, SR, q);
              while(q[1])
                   u0.wb_read(0, SR, q); // poll it until it is zero
              $display("status: %t tip==0", $time);
 
              // send memory contents
              u0.wb_write(1, TXR,     8'ha5); // present data
              u0.wb_write(0, CR,      8'h10); // set command (write)
              $display("status: %t write data a5", $time);
 
              // check tip bit
              u0.wb_read(1, SR, q);
              while(q[1])
                   u0.wb_read(1, SR, q); // poll it until it is zero
              $display("status: %t tip==0", $time);
 
              // send memory contents for next memory address (auto_inc)
              u0.wb_write(1, TXR,     8'h5a); // present data
              u0.wb_write(0, CR,      8'h50); // set command (stop, write)
              $display("status: %t write next data 5a, generate 'stop'", $time);
 
              // check tip bit
              u0.wb_read(1, SR, q);
              while(q[1])
                   u0.wb_read(1, SR, q); // poll it until it is zero
              $display("status: %t tip==0", $time);
 
              //
              // delay
              //
//            #100000; // wait for 100us.
//            $display("status: %t wait 100us", $time);
 
              //
              // access slave (read)
              //
 
              // drive slave address
              u0.wb_write(1, TXR,     8'ha0); // present slave address, set write-bit (== !read)
              u0.wb_write(0, CR,      8'h90); // set command (start, write)
              $display("status: %t generate 'start', write cmd a0 (slave address+write)", $time);
 
              // check tip bit
              u0.wb_read(1, SR, q);
              while(q[1])
                   u0.wb_read(1, SR, q); // poll it until it is zero
              $display("status: %t tip==0", $time);
 
              // send memory address
              u0.wb_write(1, TXR,     8'h01); // present slave's memory address
              u0.wb_write(0, CR,      8'h10); // set command (write)
              $display("status: %t write slave address 01", $time);
 
              // check tip bit
              u0.wb_read(1, SR, q);
              while(q[1])
                   u0.wb_read(1, SR, q); // poll it until it is zero
              $display("status: %t tip==0", $time);
 
              // drive slave address
              u0.wb_write(1, TXR,     8'ha1); // present slave's address, set read-bit
              u0.wb_write(0, CR,      8'h90); // set command (start, write)
              $display("status: %t generate 'repeated start', write cmd a1 (slave address+read)", $time);
 
              // check tip bit
              u0.wb_read(1, SR, q);
              while(q[1])
                   u0.wb_read(1, SR, q); // poll it until it is zero
              $display("status: %t tip==0", $time);
 
              // read data from slave
              u0.wb_write(1, CR,      8'h20); // set command (read, ack_read)
              $display("status: %t read + ack", $time);
 
              // check tip bit
              u0.wb_read(1, SR, q);
              while(q[1])
                   u0.wb_read(1, SR, q); // poll it until it is zero
              $display("status: %t tip==0", $time);
 
              // check data just received
              u0.wb_read(1, RXR, qq);
              if(qq !== 8'ha5)
                $display("\nERROR: Expected a5, received %x at time %t", qq, $time);
 
              // read data from slave
              u0.wb_write(1, CR,      8'h20); // set command (read, ack_read)
              $display("status: %t read + ack", $time);
 
              // check tip bit
              u0.wb_read(1, SR, q);
              while(q[1])
                   u0.wb_read(1, SR, q); // poll it until it is zero
              $display("status: %t tip==0", $time);
 
              // check data just received
              u0.wb_read(1, RXR, qq);
              if(qq !== 8'h5a)
                $display("\nERROR: Expected 5a, received %x at time %t", qq, $time);
 
              // read data from slave
              u0.wb_write(1, CR,      8'h20); // set command (read, ack_read)
              $display("status: %t read + ack", $time);
 
              // check tip bit
              u0.wb_read(1, SR, q);
              while(q[1])
                   u0.wb_read(1, SR, q); // poll it until it is zero
              $display("status: %t tip==0", $time);
 
              // check data just received
              u0.wb_read(1, RXR, qq);
              $display("status: %t received %x from 3rd read address", $time, qq);
 
              // read data from slave
              u0.wb_write(1, CR,      8'h28); // set command (read, nack_read)
              $display("status: %t read + nack", $time);
 
              // check tip bit
              u0.wb_read(1, SR, q);
              while(q[1])
                   u0.wb_read(1, SR, q); // poll it until it is zero
              $display("status: %t tip==0", $time);
 
              // check data just received
              u0.wb_read(1, RXR, qq);
              $display("status: %t received %x from 4th read address", $time, qq);
 
              //
              // check invalid slave memory address
              //
 
              // drive slave address
              u0.wb_write(1, TXR,     8'ha0); // present slave address, set write-bit (== !read)
              u0.wb_write(0, CR,      8'h90); // set command (start, write)
              $display("status: %t generate 'start', write cmd a0 (slave address+write). Check invalid address", $time);
 
              // check tip bit
              u0.wb_read(1, SR, q);
              while(q[1])
                   u0.wb_read(1, SR, q); // poll it until it is zero
              $display("status: %t tip==0", $time);
 
              // send memory address
              u0.wb_write(1, TXR,     8'h10); // present slave's memory address
              u0.wb_write(0, CR,      8'h10); // set command (write)
              $display("status: %t write slave memory address 10", $time);
 
              // check tip bit
              u0.wb_read(1, SR, q);
              while(q[1])
                   u0.wb_read(1, SR, q); // poll it until it is zero
              $display("status: %t tip==0", $time);
 
              // slave should have send NACK
              $display("status: %t Check for nack", $time);
              if(!q[7])
                $display("\nERROR: Expected NACK, received ACK\n");
 
              // read data from slave
              u0.wb_write(1, CR,      8'h40); // set command (stop)
              $display("status: %t generate 'stop'", $time);
 
              // check tip bit
              u0.wb_read(1, SR, q);
              while(q[1])
              u0.wb_read(1, SR, q); // poll it until it is zero
              $display("status: %t tip==0", $time);
 
              #25000; // wait 25us
              $display("\n\nstatus: %t Testbench done", $time);
              $finish;
          end
 
endmodule
 
 

Line No.	Rev	Author	Line
1	19	rherveille	`/////////////////////////////////////////////////////////////////////`
2			`//// ////`
3			`//// WISHBONE rev.B2 compliant I2C Master controller Testbench ////`
4			`//// ////`
5			`//// ////`
6			`//// Author: Richard Herveille ////`
7			`//// richard@asics.ws ////`
8			`//// www.asics.ws ////`
9			`//// ////`
10			`//// Downloaded from: http://www.opencores.org/projects/i2c/ ////`
11			`//// ////`
12			`/////////////////////////////////////////////////////////////////////`
13			`//// ////`
14			`//// Copyright (C) 2001 Richard Herveille ////`
15			`//// richard@asics.ws ////`
16			`//// ////`
17			`//// This source file may be used and distributed without ////`
18			`//// restriction provided that this copyright statement is not ////`
19			`//// removed from the file and that any derivative work contains ////`
20			`//// the original copyright notice and the associated disclaimer.////`
21			`//// ////`
22			//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY ////
23			`//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED ////`
24			`//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ////`
25			`//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR ////`
26			`//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ////`
27			`//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ////`
28			`//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE ////`
29			`//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR ////`
30			`//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ////`
31			`//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ////`
32			`//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT ////`
33			`//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ////`
34			`//// POSSIBILITY OF SUCH DAMAGE. ////`
35			`//// ////`
36			`/////////////////////////////////////////////////////////////////////`
37
38			`// CVS Log`
39	10	rherveille	`//`
40	25	rherveille	`// $Id: tst_bench_top.v,v 1.3 2002-10-30 18:11:06 rherveille Exp $`
41	10	rherveille	`//`
42	25	rherveille	`// $Date: 2002-10-30 18:11:06 $`
43			`// $Revision: 1.3 $`
44	19	rherveille	`// $Author: rherveille $`
45			`// $Locker: $`
46			`// $State: Exp $`
47			`//`
48			`// Change History:`
49			`// $Log: not supported by cvs2svn $`
50	25	rherveille	`// Revision 1.2 2002/03/17 10:26:38 rherveille`
51			`// Fixed some race conditions in the i2c-slave model.`
52			`// Added debug information.`
53			`// Added headers.`
54			`//`
55	10	rherveille
56			`include "timescale.v"
57
58			`module tst_bench_top();`
59
60			`//`
61			`// wires && regs`
62			`//`
63			`reg clk;`
64			`reg rstn;`
65
66			`wire [31:0] adr;`
67			`wire [ 7:0] dat_i, dat_o;`
68			`wire we;`
69			`wire stb;`
70			`wire cyc;`
71			`wire ack;`
72			`wire inta;`
73
74	19	rherveille	`reg [7:0] q, qq;`
75	10	rherveille
76			`wire scl, scl_o, scl_oen;`
77			`wire sda, sda_o, sda_oen;`
78
79			`parameter PRER_LO = 3'b000;`
80			`parameter PRER_HI = 3'b001;`
81			`parameter CTR = 3'b010;`
82			`parameter RXR = 3'b011;`
83			`parameter TXR = 3'b011;`
84			`parameter CR = 3'b100;`
85			`parameter SR = 3'b100;`
86
87			`parameter TXR_R = 3'b101; // undocumented / reserved output`
88			`parameter CR_R = 3'b110; // undocumented / reserved output`
89
90			`//`
91			`// Module body`
92			`//`
93
94			`// generate clock`
95			`always #5 clk = ~clk;`
96
97			`// hookup wishbone master model`
98	19	rherveille	`wb_master_model #(8, 32) u0 (`
99	10	rherveille	`.clk(clk),`
100			`.rst(rstn),`
101			`.adr(adr),`
102			`.din(dat_i),`
103			`.dout(dat_o),`
104			`.cyc(cyc),`
105			`.stb(stb),`
106			`.we(we),`
107	19	rherveille	`.sel(),`
108	10	rherveille	`.ack(ack),`
109			`.err(1'b0),`
110			`.rty(1'b0)`
111			`);`
112
113			`// hookup wishbone_i2c_master core`
114			`i2c_master_top i2c_top (`
115
116			`// wishbone interface`
117			`.wb_clk_i(clk),`
118			`.wb_rst_i(1'b0),`
119			`.arst_i(rstn),`
120			`.wb_adr_i(adr[2:0]),`
121			`.wb_dat_i(dat_o),`
122			`.wb_dat_o(dat_i),`
123			`.wb_we_i(we),`
124			`.wb_stb_i(stb),`
125			`.wb_cyc_i(cyc),`
126			`.wb_ack_o(ack),`
127			`.wb_inta_o(inta),`
128
129			`// i2c signals`
130			`.scl_pad_i(scl),`
131			`.scl_pad_o(scl_o),`
132			`.scl_padoen_o(scl_oen),`
133			`.sda_pad_i(sda),`
134			`.sda_pad_o(sda_o),`
135			`.sda_padoen_o(sda_oen)`
136			`);`
137
138			`// hookup i2c slave model`
139			`i2c_slave_model #(7'b1010_000) i2c_slave (`
140			`.scl(scl),`
141			`.sda(sda)`
142			`);`
143
144			`// create i2c lines`
145			`assign scl = scl_oen ? 1'bz : scl_o; // create tri-state buffer for i2c_master scl line`
146			`assign sda = sda_oen ? 1'bz : sda_o; // create tri-state buffer for i2c_master sda line`
147
148			`pullup p1(scl); // pullup scl line`
149			`pullup p2(sda); // pullup sda line`
150
151			`initial`
152	25	rherveille	`begin`
153			`ifdef WAVES
154			`$shm_open("waves");`
155			`$shm_probe("AS",tst_bench_top,"AS");`
156			`$display("INFO: Signal dump enabled ...\n\n");`
157			`endif
158	19	rherveille
159	25	rherveille	`// force i2c_slave.debug = 1'b1; // enable i2c_slave debug information`
160			`force i2c_slave.debug = 1'b0; // disable i2c_slave debug information`
161	19	rherveille
162	25	rherveille	`$display("\nstatus: %t Testbench started\n\n", $time);`
163	19	rherveille
164	25	rherveille	`// $dumpfile("bench.vcd");`
165			`// $dumpvars(1, tst_bench_top);`
166			`// $dumpvars(1, tst_bench_top.i2c_slave);`
167	10	rherveille
168	25	rherveille	`// initially values`
169			`clk = 0;`
170	19	rherveille
171	25	rherveille	`// reset system`
172			`rstn = 1'b1; // negate reset`
173			`#2;`
174			`rstn = 1'b0; // assert reset`
175			`repeat(20) @(posedge clk);`
176			`rstn = 1'b1; // negate reset`
177	10	rherveille
178	25	rherveille	`$display("status: %t done reset", $time);`
179	10	rherveille
180	25	rherveille	`@(posedge clk);`
181	10	rherveille
182	25	rherveille	`//`
183			`// program core`
184			`//`
185	19	rherveille
186	25	rherveille	`// program internal registers`
187			`// u0.wb_write(1, PRER_LO, 8'hfa); // load prescaler lo-byte`
188			`u0.wb_write(1, PRER_LO, 8'hc8); // load prescaler lo-byte`
189			`u0.wb_write(1, PRER_HI, 8'h00); // load prescaler hi-byte`
190			`$display("status: %t programmed registers", $time);`
191	19	rherveille
192	25	rherveille	`u0.wb_cmp(0, PRER_LO, 8'hc8); // verify prescaler lo-byte`
193			`u0.wb_cmp(0, PRER_HI, 8'h00); // verify prescaler hi-byte`
194			`$display("status: %t verified registers", $time);`
195	19	rherveille
196	25	rherveille	`u0.wb_write(1, CTR, 8'h80); // enable core`
197			`$display("status: %t core enabled", $time);`
198	10	rherveille
199	25	rherveille	`//`
200			`// access slave (write)`
201			`//`
202	19	rherveille
203	25	rherveille	`// drive slave address`
204			`u0.wb_write(1, TXR, 8'ha0); // present slave address, set write-bit (== !read)`
205			`u0.wb_write(0, CR, 8'h90); // set command (start, write)`
206			`$display("status: %t generate 'start', write cmd a0 (slave address+write)", $time);`
207	10	rherveille
208	25	rherveille	`// check tip bit`
209			`u0.wb_read(1, SR, q);`
210			`while(q[1])`
211			`u0.wb_read(0, SR, q); // poll it until it is zero`
212			`$display("status: %t tip==0", $time);`
213	10	rherveille
214	25	rherveille	`// send memory address`
215			`u0.wb_write(1, TXR, 8'h01); // present slave's memory address`
216			`u0.wb_write(0, CR, 8'h10); // set command (write)`
217			`$display("status: %t write slave memory address 01", $time);`
218	19	rherveille
219	25	rherveille	`// check tip bit`
220			`u0.wb_read(1, SR, q);`
221			`while(q[1])`
222			`u0.wb_read(0, SR, q); // poll it until it is zero`
223			`$display("status: %t tip==0", $time);`
224	10	rherveille
225	25	rherveille	`// send memory contents`
226			`u0.wb_write(1, TXR, 8'ha5); // present data`
227			`u0.wb_write(0, CR, 8'h10); // set command (write)`
228			`$display("status: %t write data a5", $time);`
229	19	rherveille
230	25	rherveille	`// check tip bit`
231			`u0.wb_read(1, SR, q);`
232			`while(q[1])`
233			`u0.wb_read(1, SR, q); // poll it until it is zero`
234			`$display("status: %t tip==0", $time);`
235	10	rherveille
236	25	rherveille	`// send memory contents for next memory address (auto_inc)`
237			`u0.wb_write(1, TXR, 8'h5a); // present data`
238			`u0.wb_write(0, CR, 8'h50); // set command (stop, write)`
239			`$display("status: %t write next data 5a, generate 'stop'", $time);`
240	19	rherveille
241	25	rherveille	`// check tip bit`
242			`u0.wb_read(1, SR, q);`
243			`while(q[1])`
244			`u0.wb_read(1, SR, q); // poll it until it is zero`
245			`$display("status: %t tip==0", $time);`
246	10	rherveille
247	25	rherveille	`//`
248			`// delay`
249			`//`
250			`// #100000; // wait for 100us.`
251			`// $display("status: %t wait 100us", $time);`
252	19	rherveille
253	25	rherveille	`//`
254			`// access slave (read)`
255			`//`
256	10	rherveille
257	25	rherveille	`// drive slave address`
258			`u0.wb_write(1, TXR, 8'ha0); // present slave address, set write-bit (== !read)`
259			`u0.wb_write(0, CR, 8'h90); // set command (start, write)`
260			`$display("status: %t generate 'start', write cmd a0 (slave address+write)", $time);`
261	19	rherveille
262	25	rherveille	`// check tip bit`
263			`u0.wb_read(1, SR, q);`
264			`while(q[1])`
265			`u0.wb_read(1, SR, q); // poll it until it is zero`
266			`$display("status: %t tip==0", $time);`
267	10	rherveille
268	25	rherveille	`// send memory address`
269			`u0.wb_write(1, TXR, 8'h01); // present slave's memory address`
270			`u0.wb_write(0, CR, 8'h10); // set command (write)`
271			`$display("status: %t write slave address 01", $time);`
272	19	rherveille
273	25	rherveille	`// check tip bit`
274			`u0.wb_read(1, SR, q);`
275			`while(q[1])`
276			`u0.wb_read(1, SR, q); // poll it until it is zero`
277			`$display("status: %t tip==0", $time);`
278	10	rherveille
279	25	rherveille	`// drive slave address`
280			`u0.wb_write(1, TXR, 8'ha1); // present slave's address, set read-bit`
281			`u0.wb_write(0, CR, 8'h90); // set command (start, write)`
282			`$display("status: %t generate 'repeated start', write cmd a1 (slave address+read)", $time);`
283	19	rherveille
284	25	rherveille	`// check tip bit`
285			`u0.wb_read(1, SR, q);`
286			`while(q[1])`
287			`u0.wb_read(1, SR, q); // poll it until it is zero`
288			`$display("status: %t tip==0", $time);`
289	10	rherveille
290	25	rherveille	`// read data from slave`
291			`u0.wb_write(1, CR, 8'h20); // set command (read, ack_read)`
292			`$display("status: %t read + ack", $time);`
293	10	rherveille
294	25	rherveille	`// check tip bit`
295			`u0.wb_read(1, SR, q);`
296			`while(q[1])`
297			`u0.wb_read(1, SR, q); // poll it until it is zero`
298			`$display("status: %t tip==0", $time);`
299	19	rherveille
300	25	rherveille	`// check data just received`
301			`u0.wb_read(1, RXR, qq);`
302			`if(qq !== 8'ha5)`
303			`$display("\nERROR: Expected a5, received %x at time %t", qq, $time);`
304	10	rherveille
305	25	rherveille	`// read data from slave`
306			`u0.wb_write(1, CR, 8'h20); // set command (read, ack_read)`
307			`$display("status: %t read + ack", $time);`
308	19	rherveille
309	25	rherveille	`// check tip bit`
310			`u0.wb_read(1, SR, q);`
311			`while(q[1])`
312			`u0.wb_read(1, SR, q); // poll it until it is zero`
313			`$display("status: %t tip==0", $time);`
314	10	rherveille
315	25	rherveille	`// check data just received`
316			`u0.wb_read(1, RXR, qq);`
317			`if(qq !== 8'h5a)`
318			`$display("\nERROR: Expected 5a, received %x at time %t", qq, $time);`
319	10	rherveille
320	25	rherveille	`// read data from slave`
321			`u0.wb_write(1, CR, 8'h20); // set command (read, ack_read)`
322			`$display("status: %t read + ack", $time);`
323	19	rherveille
324	25	rherveille	`// check tip bit`
325			`u0.wb_read(1, SR, q);`
326			`while(q[1])`
327			`u0.wb_read(1, SR, q); // poll it until it is zero`
328			`$display("status: %t tip==0", $time);`
329	10	rherveille
330	25	rherveille	`// check data just received`
331			`u0.wb_read(1, RXR, qq);`
332			`$display("status: %t received %x from 3rd read address", $time, qq);`
333	19	rherveille
334	25	rherveille	`// read data from slave`
335			`u0.wb_write(1, CR, 8'h28); // set command (read, nack_read)`
336			`$display("status: %t read + nack", $time);`
337	10	rherveille
338	25	rherveille	`// check tip bit`
339			`u0.wb_read(1, SR, q);`
340			`while(q[1])`
341			`u0.wb_read(1, SR, q); // poll it until it is zero`
342			`$display("status: %t tip==0", $time);`
343	19	rherveille
344	25	rherveille	`// check data just received`
345			`u0.wb_read(1, RXR, qq);`
346			`$display("status: %t received %x from 4th read address", $time, qq);`
347	10	rherveille
348	25	rherveille	`//`
349			`// check invalid slave memory address`
350			`//`
351	19	rherveille
352	25	rherveille	`// drive slave address`
353			`u0.wb_write(1, TXR, 8'ha0); // present slave address, set write-bit (== !read)`
354			`u0.wb_write(0, CR, 8'h90); // set command (start, write)`
355			`$display("status: %t generate 'start', write cmd a0 (slave address+write). Check invalid address", $time);`
356	10	rherveille
357	25	rherveille	`// check tip bit`
358			`u0.wb_read(1, SR, q);`
359			`while(q[1])`
360			`u0.wb_read(1, SR, q); // poll it until it is zero`
361			`$display("status: %t tip==0", $time);`
362	19	rherveille
363	25	rherveille	`// send memory address`
364			`u0.wb_write(1, TXR, 8'h10); // present slave's memory address`
365			`u0.wb_write(0, CR, 8'h10); // set command (write)`
366			`$display("status: %t write slave memory address 10", $time);`
367	10	rherveille
368	25	rherveille	`// check tip bit`
369			`u0.wb_read(1, SR, q);`
370			`while(q[1])`
371			`u0.wb_read(1, SR, q); // poll it until it is zero`
372			`$display("status: %t tip==0", $time);`
373	19	rherveille
374	25	rherveille	`// slave should have send NACK`
375			`$display("status: %t Check for nack", $time);`
376			`if(!q[7])`
377			`$display("\nERROR: Expected NACK, received ACK\n");`
378	10	rherveille
379	25	rherveille	`// read data from slave`
380			`u0.wb_write(1, CR, 8'h40); // set command (stop)`
381			`$display("status: %t generate 'stop'", $time);`
382	19	rherveille
383	25	rherveille	`// check tip bit`
384			`u0.wb_read(1, SR, q);`
385			`while(q[1])`
386			`u0.wb_read(1, SR, q); // poll it until it is zero`
387			`$display("status: %t tip==0", $time);`
388	10	rherveille
389	25	rherveille	`#25000; // wait 25us`
390			`$display("\n\nstatus: %t Testbench done", $time);`
391			`$finish;`
392			`end`
393	19	rherveille
394	10	rherveille	`endmodule`
395
396

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