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/////////////////////////////////////////////////////////////////////
////                                                             ////
////  WISHBONE rev.B2 compliant I2C Master controller Testbench  ////
////                                                             ////
////                                                             ////
////  Author: Richard Herveille                                  ////
////          richard@asics.ws                                   ////
////          www.asics.ws                                       ////
////                                                             ////
////  Downloaded from: http://www.opencores.org/projects/i2c/    ////
////                                                             ////
/////////////////////////////////////////////////////////////////////
////                                                             ////
//// Copyright (C) 2001 Richard Herveille                        ////
////                    richard@asics.ws                         ////
////                                                             ////
//// This source file may be used and distributed without        ////
//// restriction provided that this copyright statement is not   ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer.////
////                                                             ////
////     THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY     ////
//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED   ////
//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS   ////
//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR      ////
//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,         ////
//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES    ////
//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE   ////
//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR        ////
//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF  ////
//// LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT  ////
//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT  ////
//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE         ////
//// POSSIBILITY OF SUCH DAMAGE.                                 ////
////                                                             ////
/////////////////////////////////////////////////////////////////////
 
//  CVS Log
//
//  $Id: tst_bench_top.v,v 1.4 2003-12-05 11:04:38 rherveille Exp $
//
//  $Date: 2003-12-05 11:04:38 $
//  $Revision: 1.4 $
//  $Author: rherveille $
//  $Locker:  $
//  $State: Exp $
//
// Change History:
//               $Log: not supported by cvs2svn $
//               Revision 1.3  2002/10/30 18:11:06  rherveille
//               Added timing tests to i2c_model.
//               Updated testbench.
//
//               Revision 1.2  2002/03/17 10:26:38  rherveille
//               Fixed some race conditions in the i2c-slave model.
//               Added debug information.
//               Added headers.
//
 
`include "timescale.v"
 
module tst_bench_top();
 
        //
        // wires && regs
        //
        reg  clk;
        reg  rstn;
 
        wire [31:0] adr;
        wire [ 7:0] dat_i, dat_o;
        wire we;
        wire stb;
        wire cyc;
        wire ack;
        wire inta;
 
        reg [7:0] q, qq;
 
        wire scl, scl_o, scl_oen;
        wire sda, sda_o, sda_oen;
        reg rscl, rsda;
 
        parameter PRER_LO = 3'b000;
        parameter PRER_HI = 3'b001;
        parameter CTR     = 3'b010;
        parameter RXR     = 3'b011;
        parameter TXR     = 3'b011;
        parameter CR      = 3'b100;
        parameter SR      = 3'b100;
 
        parameter TXR_R   = 3'b101; // undocumented / reserved output
        parameter CR_R    = 3'b110; // undocumented / reserved output
 
        parameter RD      = 1'b1;
        parameter WR      = 1'b0;
        parameter SADR    = 7'b0010_000;
 
        //
        // Module body
        //
 
        // generate clock
        always #5 clk = ~clk;
 
        // hookup wishbone master model
        wb_master_model #(8, 32) u0 (
                .clk(clk),
                .rst(rstn),
                .adr(adr),
                .din(dat_i),
                .dout(dat_o),
                .cyc(cyc),
                .stb(stb),
                .we(we),
                .sel(),
                .ack(ack),
                .err(1'b0),
                .rty(1'b0)
        );
 
        // hookup wishbone_i2c_master core
        i2c_master_top i2c_top (
 
                // wishbone interface
                .wb_clk_i(clk),
                .wb_rst_i(1'b0),
                .arst_i(rstn),
                .wb_adr_i(adr[2:0]),
                .wb_dat_i(dat_o),
                .wb_dat_o(dat_i),
                .wb_we_i(we),
                .wb_stb_i(stb),
                .wb_cyc_i(cyc),
                .wb_ack_o(ack),
                .wb_inta_o(inta),
 
                // i2c signals
                .scl_pad_i(scl),
                .scl_pad_o(scl_o),
                .scl_padoen_o(scl_oen),
                .sda_pad_i(sda),
                .sda_pad_o(sda_o),
                .sda_padoen_o(sda_oen)
        );
 
        // hookup i2c slave model
        i2c_slave_model #(SADR) i2c_slave (
                .scl(scl),
                .sda(sda)
        );
 
        // create i2c lines
        always rscl = #600 scl_oen ? 1'bz : scl_o; // create tri-state buffer for i2c_master scl line
        always rsda = #600 sda_oen ? 1'bz : sda_o; // create tri-state buffer for i2c_master sda line
 
        assign scl = rscl;
        assign sda = rsda;
 
        pullup p1(scl); // pullup scl line
        pullup p2(sda); // pullup sda line
 
        initial
          begin
              `ifdef WAVES
                 $shm_open("waves");
                 $shm_probe("AS",tst_bench_top,"AS");
                 $display("INFO: Signal dump enabled ...\n\n");
              `endif
 
//            force i2c_slave.debug = 1'b1; // enable i2c_slave debug information
              force i2c_slave.debug = 1'b0; // disable i2c_slave debug information
 
              $display("\nstatus: %t Testbench started\n\n", $time);
 
//            $dumpfile("bench.vcd");
//            $dumpvars(1, tst_bench_top);
//            $dumpvars(1, tst_bench_top.i2c_slave);
 
              // initially values
              clk = 0;
 
              // reset system
              rstn = 1'b1; // negate reset
              #2;
              rstn = 1'b0; // assert reset
              repeat(1) @(posedge clk);
              rstn = 1'b1; // negate reset
 
              $display("status: %t done reset", $time);
 
              @(posedge clk);
 
              //
              // program core
              //
 
              // program internal registers
              u0.wb_write(1, PRER_LO, 8'hfa); // load prescaler lo-byte
              u0.wb_write(1, PRER_LO, 8'hc8); // load prescaler lo-byte
              u0.wb_write(1, PRER_HI, 8'h00); // load prescaler hi-byte
              $display("status: %t programmed registers", $time);
 
              u0.wb_cmp(0, PRER_LO, 8'hc8); // verify prescaler lo-byte
              u0.wb_cmp(0, PRER_HI, 8'h00); // verify prescaler hi-byte
              $display("status: %t verified registers", $time);
 
              u0.wb_write(1, CTR,     8'h80); // enable core
              $display("status: %t core enabled", $time);
 
              //
              // access slave (write)
              //
 
              // drive slave address
              u0.wb_write(1, TXR, {SADR,WR} ); // present slave address, set write-bit
              u0.wb_write(0, CR,      8'h90 ); // set command (start, write)
              $display("status: %t generate 'start', write cmd %0h (slave address+write)", $time, {SADR,WR} );
 
              // check tip bit
              u0.wb_read(1, SR, q);
              while(q[1])
                   u0.wb_read(0, SR, q); // poll it until it is zero
              $display("status: %t tip==0", $time);
 
              // send memory address
              u0.wb_write(1, TXR,     8'h01); // present slave's memory address
              u0.wb_write(0, CR,      8'h10); // set command (write)
              $display("status: %t write slave memory address 01", $time);
 
              // check tip bit
              u0.wb_read(1, SR, q);
              while(q[1])
                   u0.wb_read(0, SR, q); // poll it until it is zero
              $display("status: %t tip==0", $time);
 
              // send memory contents
              u0.wb_write(1, TXR,     8'ha5); // present data
              u0.wb_write(0, CR,      8'h10); // set command (write)
              $display("status: %t write data a5", $time);
 
              // check tip bit
              u0.wb_read(1, SR, q);
              while(q[1])
                   u0.wb_read(1, SR, q); // poll it until it is zero
              $display("status: %t tip==0", $time);
 
              // send memory contents for next memory address (auto_inc)
              u0.wb_write(1, TXR,     8'h5a); // present data
              u0.wb_write(0, CR,      8'h50); // set command (stop, write)
              $display("status: %t write next data 5a, generate 'stop'", $time);
 
              // check tip bit
              u0.wb_read(1, SR, q);
              while(q[1])
                   u0.wb_read(1, SR, q); // poll it until it is zero
              $display("status: %t tip==0", $time);
 
              //
              // delay
              //
//            #100000; // wait for 100us.
//            $display("status: %t wait 100us", $time);
 
              //
              // access slave (read)
              //
 
              // drive slave address
              u0.wb_write(1, TXR,{SADR,WR} ); // present slave address, set write-bit
              u0.wb_write(0, CR,     8'h90 ); // set command (start, write)
              $display("status: %t generate 'start', write cmd %0h (slave address+write)", $time, {SADR,WR} );
 
              // check tip bit
              u0.wb_read(1, SR, q);
              while(q[1])
                   u0.wb_read(1, SR, q); // poll it until it is zero
              $display("status: %t tip==0", $time);
 
              // send memory address
              u0.wb_write(1, TXR,     8'h01); // present slave's memory address
              u0.wb_write(0, CR,      8'h10); // set command (write)
              $display("status: %t write slave address 01", $time);
 
              // check tip bit
              u0.wb_read(1, SR, q);
              while(q[1])
                   u0.wb_read(1, SR, q); // poll it until it is zero
              $display("status: %t tip==0", $time);
 
              // drive slave address
              u0.wb_write(1, TXR, {SADR,RD} ); // present slave's address, set read-bit
              u0.wb_write(0, CR,      8'h90 ); // set command (start, write)
              $display("status: %t generate 'repeated start', write cmd %0h (slave address+read)", $time, {SADR,RD} );
 
              // check tip bit
              u0.wb_read(1, SR, q);
              while(q[1])
                   u0.wb_read(1, SR, q); // poll it until it is zero
              $display("status: %t tip==0", $time);
 
              // read data from slave
              u0.wb_write(1, CR,      8'h20); // set command (read, ack_read)
              $display("status: %t read + ack", $time);
 
              // check tip bit
              u0.wb_read(1, SR, q);
              while(q[1])
                   u0.wb_read(1, SR, q); // poll it until it is zero
              $display("status: %t tip==0", $time);
 
              // check data just received
              u0.wb_read(1, RXR, qq);
              if(qq !== 8'ha5)
                $display("\nERROR: Expected a5, received %x at time %t", qq, $time);
              else
                $display("status: %t received %x", $time, qq);
 
              // read data from slave
              u0.wb_write(1, CR,      8'h20); // set command (read, ack_read)
              $display("status: %t read + ack", $time);
 
              // check tip bit
              u0.wb_read(1, SR, q);
              while(q[1])
                   u0.wb_read(1, SR, q); // poll it until it is zero
              $display("status: %t tip==0", $time);
 
              // check data just received
              u0.wb_read(1, RXR, qq);
              if(qq !== 8'h5a)
                $display("\nERROR: Expected 5a, received %x at time %t", qq, $time);
              else
                $display("status: %t received %x", $time, qq);
 
              // read data from slave
              u0.wb_write(1, CR,      8'h20); // set command (read, ack_read)
              $display("status: %t read + ack", $time);
 
              // check tip bit
              u0.wb_read(1, SR, q);
              while(q[1])
                   u0.wb_read(1, SR, q); // poll it until it is zero
              $display("status: %t tip==0", $time);
 
              // check data just received
              u0.wb_read(1, RXR, qq);
              $display("status: %t received %x from 3rd read address", $time, qq);
 
              // read data from slave
              u0.wb_write(1, CR,      8'h28); // set command (read, nack_read)
              $display("status: %t read + nack", $time);
 
              // check tip bit
              u0.wb_read(1, SR, q);
              while(q[1])
                   u0.wb_read(1, SR, q); // poll it until it is zero
              $display("status: %t tip==0", $time);
 
              // check data just received
              u0.wb_read(1, RXR, qq);
              $display("status: %t received %x from 4th read address", $time, qq);
 
              //
              // check invalid slave memory address
              //
 
              // drive slave address
              u0.wb_write(1, TXR, {SADR,WR} ); // present slave address, set write-bit
              u0.wb_write(0, CR,      8'h90 ); // set command (start, write)
              $display("status: %t generate 'start', write cmd %0h (slave address+write). Check invalid address", $time, {SADR,WR} );
 
              // check tip bit
              u0.wb_read(1, SR, q);
              while(q[1])
                   u0.wb_read(1, SR, q); // poll it until it is zero
              $display("status: %t tip==0", $time);
 
              // send memory address
              u0.wb_write(1, TXR,     8'h10); // present slave's memory address
              u0.wb_write(0, CR,      8'h10); // set command (write)
              $display("status: %t write slave memory address 10", $time);
 
              // check tip bit
              u0.wb_read(1, SR, q);
              while(q[1])
                   u0.wb_read(1, SR, q); // poll it until it is zero
              $display("status: %t tip==0", $time);
 
              // slave should have send NACK
              $display("status: %t Check for nack", $time);
              if(!q[7])
                $display("\nERROR: Expected NACK, received ACK\n");
 
              // read data from slave
              u0.wb_write(1, CR,      8'h40); // set command (stop)
              $display("status: %t generate 'stop'", $time);
 
              // check tip bit
              u0.wb_read(1, SR, q);
              while(q[1])
              u0.wb_read(1, SR, q); // poll it until it is zero
              $display("status: %t tip==0", $time);
 
              #250000; // wait 250us
              $display("\n\nstatus: %t Testbench done", $time);
              $finish;
          end
 
endmodule
 
 
 

Line No.	Rev	Author	Line
1	19	rherveille	`/////////////////////////////////////////////////////////////////////`
2			`//// ////`
3			`//// WISHBONE rev.B2 compliant I2C Master controller Testbench ////`
4			`//// ////`
5			`//// ////`
6			`//// Author: Richard Herveille ////`
7			`//// richard@asics.ws ////`
8			`//// www.asics.ws ////`
9			`//// ////`
10			`//// Downloaded from: http://www.opencores.org/projects/i2c/ ////`
11			`//// ////`
12			`/////////////////////////////////////////////////////////////////////`
13			`//// ////`
14			`//// Copyright (C) 2001 Richard Herveille ////`
15			`//// richard@asics.ws ////`
16			`//// ////`
17			`//// This source file may be used and distributed without ////`
18			`//// restriction provided that this copyright statement is not ////`
19			`//// removed from the file and that any derivative work contains ////`
20			`//// the original copyright notice and the associated disclaimer.////`
21			`//// ////`
22			//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY ////
23			`//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED ////`
24			`//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ////`
25			`//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR ////`
26			`//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ////`
27			`//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ////`
28			`//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE ////`
29			`//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR ////`
30			`//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ////`
31			`//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ////`
32			`//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT ////`
33			`//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ////`
34			`//// POSSIBILITY OF SUCH DAMAGE. ////`
35			`//// ////`
36			`/////////////////////////////////////////////////////////////////////`
37
38			`// CVS Log`
39	10	rherveille	`//`
40	45	rherveille	`// $Id: tst_bench_top.v,v 1.4 2003-12-05 11:04:38 rherveille Exp $`
41	10	rherveille	`//`
42	45	rherveille	`// $Date: 2003-12-05 11:04:38 $`
43			`// $Revision: 1.4 $`
44	19	rherveille	`// $Author: rherveille $`
45			`// $Locker: $`
46			`// $State: Exp $`
47			`//`
48			`// Change History:`
49			`// $Log: not supported by cvs2svn $`
50	45	rherveille	`// Revision 1.3 2002/10/30 18:11:06 rherveille`
51			`// Added timing tests to i2c_model.`
52			`// Updated testbench.`
53			`//`
54	25	rherveille	`// Revision 1.2 2002/03/17 10:26:38 rherveille`
55			`// Fixed some race conditions in the i2c-slave model.`
56			`// Added debug information.`
57			`// Added headers.`
58			`//`
59	10	rherveille
60			`include "timescale.v"
61
62			`module tst_bench_top();`
63
64			`//`
65			`// wires && regs`
66			`//`
67			`reg clk;`
68			`reg rstn;`
69
70			`wire [31:0] adr;`
71			`wire [ 7:0] dat_i, dat_o;`
72			`wire we;`
73			`wire stb;`
74			`wire cyc;`
75			`wire ack;`
76			`wire inta;`
77
78	19	rherveille	`reg [7:0] q, qq;`
79	10	rherveille
80			`wire scl, scl_o, scl_oen;`
81			`wire sda, sda_o, sda_oen;`
82	45	rherveille	`reg rscl, rsda;`
83	10	rherveille
84			`parameter PRER_LO = 3'b000;`
85			`parameter PRER_HI = 3'b001;`
86			`parameter CTR = 3'b010;`
87			`parameter RXR = 3'b011;`
88			`parameter TXR = 3'b011;`
89			`parameter CR = 3'b100;`
90			`parameter SR = 3'b100;`
91
92			`parameter TXR_R = 3'b101; // undocumented / reserved output`
93			`parameter CR_R = 3'b110; // undocumented / reserved output`
94
95	45	rherveille	`parameter RD = 1'b1;`
96			`parameter WR = 1'b0;`
97			`parameter SADR = 7'b0010_000;`
98
99	10	rherveille	`//`
100			`// Module body`
101			`//`
102
103			`// generate clock`
104			`always #5 clk = ~clk;`
105
106			`// hookup wishbone master model`
107	19	rherveille	`wb_master_model #(8, 32) u0 (`
108	10	rherveille	`.clk(clk),`
109			`.rst(rstn),`
110			`.adr(adr),`
111			`.din(dat_i),`
112			`.dout(dat_o),`
113			`.cyc(cyc),`
114			`.stb(stb),`
115			`.we(we),`
116	19	rherveille	`.sel(),`
117	10	rherveille	`.ack(ack),`
118			`.err(1'b0),`
119			`.rty(1'b0)`
120			`);`
121
122			`// hookup wishbone_i2c_master core`
123			`i2c_master_top i2c_top (`
124
125			`// wishbone interface`
126	45	rherveille	`.wb_clk_i(clk),`
127			`.wb_rst_i(1'b0),`
128			`.arst_i(rstn),`
129			`.wb_adr_i(adr[2:0]),`
130			`.wb_dat_i(dat_o),`
131			`.wb_dat_o(dat_i),`
132			`.wb_we_i(we),`
133			`.wb_stb_i(stb),`
134			`.wb_cyc_i(cyc),`
135			`.wb_ack_o(ack),`
136	10	rherveille	`.wb_inta_o(inta),`
137
138			`// i2c signals`
139	45	rherveille	`.scl_pad_i(scl),`
140			`.scl_pad_o(scl_o),`
141			`.scl_padoen_o(scl_oen),`
142			`.sda_pad_i(sda),`
143			`.sda_pad_o(sda_o),`
144	10	rherveille	`.sda_padoen_o(sda_oen)`
145			`);`
146
147			`// hookup i2c slave model`
148	45	rherveille	`i2c_slave_model #(SADR) i2c_slave (`
149	10	rherveille	`.scl(scl),`
150			`.sda(sda)`
151			`);`
152
153			`// create i2c lines`
154	45	rherveille	`always rscl = #600 scl_oen ? 1'bz : scl_o; // create tri-state buffer for i2c_master scl line`
155			`always rsda = #600 sda_oen ? 1'bz : sda_o; // create tri-state buffer for i2c_master sda line`
156	10	rherveille
157	45	rherveille	`assign scl = rscl;`
158			`assign sda = rsda;`
159
160	10	rherveille	`pullup p1(scl); // pullup scl line`
161			`pullup p2(sda); // pullup sda line`
162
163			`initial`
164	25	rherveille	`begin`
165			`ifdef WAVES
166			`$shm_open("waves");`
167			`$shm_probe("AS",tst_bench_top,"AS");`
168			`$display("INFO: Signal dump enabled ...\n\n");`
169			`endif
170	19	rherveille
171	25	rherveille	`// force i2c_slave.debug = 1'b1; // enable i2c_slave debug information`
172			`force i2c_slave.debug = 1'b0; // disable i2c_slave debug information`
173	19	rherveille
174	25	rherveille	`$display("\nstatus: %t Testbench started\n\n", $time);`
175	19	rherveille
176	25	rherveille	`// $dumpfile("bench.vcd");`
177			`// $dumpvars(1, tst_bench_top);`
178			`// $dumpvars(1, tst_bench_top.i2c_slave);`
179	10	rherveille
180	25	rherveille	`// initially values`
181			`clk = 0;`
182	19	rherveille
183	25	rherveille	`// reset system`
184			`rstn = 1'b1; // negate reset`
185			`#2;`
186			`rstn = 1'b0; // assert reset`
187	45	rherveille	`repeat(1) @(posedge clk);`
188	25	rherveille	`rstn = 1'b1; // negate reset`
189	10	rherveille
190	25	rherveille	`$display("status: %t done reset", $time);`
191	10	rherveille
192	25	rherveille	`@(posedge clk);`
193	10	rherveille
194	25	rherveille	`//`
195			`// program core`
196			`//`
197	19	rherveille
198	25	rherveille	`// program internal registers`
199	45	rherveille	`u0.wb_write(1, PRER_LO, 8'hfa); // load prescaler lo-byte`
200	25	rherveille	`u0.wb_write(1, PRER_LO, 8'hc8); // load prescaler lo-byte`
201			`u0.wb_write(1, PRER_HI, 8'h00); // load prescaler hi-byte`
202			`$display("status: %t programmed registers", $time);`
203	19	rherveille
204	25	rherveille	`u0.wb_cmp(0, PRER_LO, 8'hc8); // verify prescaler lo-byte`
205			`u0.wb_cmp(0, PRER_HI, 8'h00); // verify prescaler hi-byte`
206			`$display("status: %t verified registers", $time);`
207	19	rherveille
208	25	rherveille	`u0.wb_write(1, CTR, 8'h80); // enable core`
209			`$display("status: %t core enabled", $time);`
210	10	rherveille
211	25	rherveille	`//`
212			`// access slave (write)`
213			`//`
214	19	rherveille
215	25	rherveille	`// drive slave address`
216	45	rherveille	`u0.wb_write(1, TXR, {SADR,WR} ); // present slave address, set write-bit`
217			`u0.wb_write(0, CR, 8'h90 ); // set command (start, write)`
218			`$display("status: %t generate 'start', write cmd %0h (slave address+write)", $time, {SADR,WR} );`
219	10	rherveille
220	25	rherveille	`// check tip bit`
221			`u0.wb_read(1, SR, q);`
222			`while(q[1])`
223			`u0.wb_read(0, SR, q); // poll it until it is zero`
224			`$display("status: %t tip==0", $time);`
225	10	rherveille
226	25	rherveille	`// send memory address`
227			`u0.wb_write(1, TXR, 8'h01); // present slave's memory address`
228			`u0.wb_write(0, CR, 8'h10); // set command (write)`
229			`$display("status: %t write slave memory address 01", $time);`
230	19	rherveille
231	25	rherveille	`// check tip bit`
232			`u0.wb_read(1, SR, q);`
233			`while(q[1])`
234			`u0.wb_read(0, SR, q); // poll it until it is zero`
235			`$display("status: %t tip==0", $time);`
236	10	rherveille
237	25	rherveille	`// send memory contents`
238			`u0.wb_write(1, TXR, 8'ha5); // present data`
239			`u0.wb_write(0, CR, 8'h10); // set command (write)`
240			`$display("status: %t write data a5", $time);`
241	19	rherveille
242	25	rherveille	`// check tip bit`
243			`u0.wb_read(1, SR, q);`
244			`while(q[1])`
245			`u0.wb_read(1, SR, q); // poll it until it is zero`
246			`$display("status: %t tip==0", $time);`
247	10	rherveille
248	25	rherveille	`// send memory contents for next memory address (auto_inc)`
249			`u0.wb_write(1, TXR, 8'h5a); // present data`
250			`u0.wb_write(0, CR, 8'h50); // set command (stop, write)`
251			`$display("status: %t write next data 5a, generate 'stop'", $time);`
252	19	rherveille
253	25	rherveille	`// check tip bit`
254			`u0.wb_read(1, SR, q);`
255			`while(q[1])`
256			`u0.wb_read(1, SR, q); // poll it until it is zero`
257			`$display("status: %t tip==0", $time);`
258	10	rherveille
259	25	rherveille	`//`
260			`// delay`
261			`//`
262			`// #100000; // wait for 100us.`
263			`// $display("status: %t wait 100us", $time);`
264	19	rherveille
265	25	rherveille	`//`
266			`// access slave (read)`
267			`//`
268	10	rherveille
269	25	rherveille	`// drive slave address`
270	45	rherveille	`u0.wb_write(1, TXR,{SADR,WR} ); // present slave address, set write-bit`
271			`u0.wb_write(0, CR, 8'h90 ); // set command (start, write)`
272			`$display("status: %t generate 'start', write cmd %0h (slave address+write)", $time, {SADR,WR} );`
273	19	rherveille
274	25	rherveille	`// check tip bit`
275			`u0.wb_read(1, SR, q);`
276			`while(q[1])`
277			`u0.wb_read(1, SR, q); // poll it until it is zero`
278			`$display("status: %t tip==0", $time);`
279	10	rherveille
280	25	rherveille	`// send memory address`
281			`u0.wb_write(1, TXR, 8'h01); // present slave's memory address`
282			`u0.wb_write(0, CR, 8'h10); // set command (write)`
283			`$display("status: %t write slave address 01", $time);`
284	19	rherveille
285	25	rherveille	`// check tip bit`
286			`u0.wb_read(1, SR, q);`
287			`while(q[1])`
288			`u0.wb_read(1, SR, q); // poll it until it is zero`
289			`$display("status: %t tip==0", $time);`
290	10	rherveille
291	25	rherveille	`// drive slave address`
292	45	rherveille	`u0.wb_write(1, TXR, {SADR,RD} ); // present slave's address, set read-bit`
293			`u0.wb_write(0, CR, 8'h90 ); // set command (start, write)`
294			`$display("status: %t generate 'repeated start', write cmd %0h (slave address+read)", $time, {SADR,RD} );`
295	19	rherveille
296	25	rherveille	`// check tip bit`
297			`u0.wb_read(1, SR, q);`
298			`while(q[1])`
299			`u0.wb_read(1, SR, q); // poll it until it is zero`
300			`$display("status: %t tip==0", $time);`
301	10	rherveille
302	25	rherveille	`// read data from slave`
303			`u0.wb_write(1, CR, 8'h20); // set command (read, ack_read)`
304			`$display("status: %t read + ack", $time);`
305	10	rherveille
306	25	rherveille	`// check tip bit`
307			`u0.wb_read(1, SR, q);`
308			`while(q[1])`
309			`u0.wb_read(1, SR, q); // poll it until it is zero`
310			`$display("status: %t tip==0", $time);`
311	19	rherveille
312	25	rherveille	`// check data just received`
313			`u0.wb_read(1, RXR, qq);`
314			`if(qq !== 8'ha5)`
315			`$display("\nERROR: Expected a5, received %x at time %t", qq, $time);`
316	45	rherveille	`else`
317			`$display("status: %t received %x", $time, qq);`
318	10	rherveille
319	25	rherveille	`// read data from slave`
320			`u0.wb_write(1, CR, 8'h20); // set command (read, ack_read)`
321			`$display("status: %t read + ack", $time);`
322	19	rherveille
323	25	rherveille	`// check tip bit`
324			`u0.wb_read(1, SR, q);`
325			`while(q[1])`
326			`u0.wb_read(1, SR, q); // poll it until it is zero`
327			`$display("status: %t tip==0", $time);`
328	10	rherveille
329	25	rherveille	`// check data just received`
330			`u0.wb_read(1, RXR, qq);`
331			`if(qq !== 8'h5a)`
332			`$display("\nERROR: Expected 5a, received %x at time %t", qq, $time);`
333	45	rherveille	`else`
334			`$display("status: %t received %x", $time, qq);`
335	10	rherveille
336	25	rherveille	`// read data from slave`
337			`u0.wb_write(1, CR, 8'h20); // set command (read, ack_read)`
338			`$display("status: %t read + ack", $time);`
339	19	rherveille
340	25	rherveille	`// check tip bit`
341			`u0.wb_read(1, SR, q);`
342			`while(q[1])`
343			`u0.wb_read(1, SR, q); // poll it until it is zero`
344			`$display("status: %t tip==0", $time);`
345	10	rherveille
346	25	rherveille	`// check data just received`
347			`u0.wb_read(1, RXR, qq);`
348			`$display("status: %t received %x from 3rd read address", $time, qq);`
349	19	rherveille
350	25	rherveille	`// read data from slave`
351			`u0.wb_write(1, CR, 8'h28); // set command (read, nack_read)`
352			`$display("status: %t read + nack", $time);`
353	10	rherveille
354	25	rherveille	`// check tip bit`
355			`u0.wb_read(1, SR, q);`
356			`while(q[1])`
357			`u0.wb_read(1, SR, q); // poll it until it is zero`
358			`$display("status: %t tip==0", $time);`
359	19	rherveille
360	25	rherveille	`// check data just received`
361			`u0.wb_read(1, RXR, qq);`
362			`$display("status: %t received %x from 4th read address", $time, qq);`
363	10	rherveille
364	25	rherveille	`//`
365			`// check invalid slave memory address`
366			`//`
367	19	rherveille
368	25	rherveille	`// drive slave address`
369	45	rherveille	`u0.wb_write(1, TXR, {SADR,WR} ); // present slave address, set write-bit`
370			`u0.wb_write(0, CR, 8'h90 ); // set command (start, write)`
371			`$display("status: %t generate 'start', write cmd %0h (slave address+write). Check invalid address", $time, {SADR,WR} );`
372	10	rherveille
373	25	rherveille	`// check tip bit`
374			`u0.wb_read(1, SR, q);`
375			`while(q[1])`
376			`u0.wb_read(1, SR, q); // poll it until it is zero`
377			`$display("status: %t tip==0", $time);`
378	19	rherveille
379	25	rherveille	`// send memory address`
380			`u0.wb_write(1, TXR, 8'h10); // present slave's memory address`
381			`u0.wb_write(0, CR, 8'h10); // set command (write)`
382			`$display("status: %t write slave memory address 10", $time);`
383	10	rherveille
384	25	rherveille	`// check tip bit`
385			`u0.wb_read(1, SR, q);`
386			`while(q[1])`
387			`u0.wb_read(1, SR, q); // poll it until it is zero`
388			`$display("status: %t tip==0", $time);`
389	19	rherveille
390	25	rherveille	`// slave should have send NACK`
391			`$display("status: %t Check for nack", $time);`
392			`if(!q[7])`
393			`$display("\nERROR: Expected NACK, received ACK\n");`
394	10	rherveille
395	25	rherveille	`// read data from slave`
396			`u0.wb_write(1, CR, 8'h40); // set command (stop)`
397			`$display("status: %t generate 'stop'", $time);`
398	19	rherveille
399	25	rherveille	`// check tip bit`
400			`u0.wb_read(1, SR, q);`
401			`while(q[1])`
402			`u0.wb_read(1, SR, q); // poll it until it is zero`
403			`$display("status: %t tip==0", $time);`
404	10	rherveille
405	45	rherveille	`#250000; // wait 250us`
406	25	rherveille	`$display("\n\nstatus: %t Testbench done", $time);`
407			`$finish;`
408			`end`
409	19	rherveille
410	10	rherveille	`endmodule`
411
412
413	45	rherveille

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