URL https://opencores.org/ocsvn/i2c/i2c/trunk

Subversion Repositories i2c

[/] [i2c/] [trunk/] [bench/] [verilog/] [tst_bench_top.v] - Blame information for rev 50

Go to most recent revision | Details | Compare with Previous | View Log


/////////////////////////////////////////////////////////////////////
////                                                             ////
////  WISHBONE rev.B2 compliant I2C Master controller Testbench  ////
////                                                             ////
////                                                             ////
////  Author: Richard Herveille                                  ////
////          richard@asics.ws                                   ////
////          www.asics.ws                                       ////
////                                                             ////
////  Downloaded from: http://www.opencores.org/projects/i2c/    ////
////                                                             ////
/////////////////////////////////////////////////////////////////////
////                                                             ////
//// Copyright (C) 2001 Richard Herveille                        ////
////                    richard@asics.ws                         ////
////                                                             ////
//// This source file may be used and distributed without        ////
//// restriction provided that this copyright statement is not   ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer.////
////                                                             ////
////     THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY     ////
//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED   ////
//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS   ////
//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR      ////
//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,         ////
//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES    ////
//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE   ////
//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR        ////
//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF  ////
//// LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT  ////
//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT  ////
//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE         ////
//// POSSIBILITY OF SUCH DAMAGE.                                 ////
////                                                             ////
/////////////////////////////////////////////////////////////////////
 
//  CVS Log
//
//  $Id: tst_bench_top.v,v 1.6 2004-02-28 15:40:42 rherveille Exp $
//
//  $Date: 2004-02-28 15:40:42 $
//  $Revision: 1.6 $
//  $Author: rherveille $
//  $Locker:  $
//  $State: Exp $
//
// Change History:
//               $Log: not supported by cvs2svn $
//               Revision 1.4  2003/12/05 11:04:38  rherveille
//               Added slave address configurability
//
//               Revision 1.3  2002/10/30 18:11:06  rherveille
//               Added timing tests to i2c_model.
//               Updated testbench.
//
//               Revision 1.2  2002/03/17 10:26:38  rherveille
//               Fixed some race conditions in the i2c-slave model.
//               Added debug information.
//               Added headers.
//
 
`include "timescale.v"
 
module tst_bench_top();
 
        //
        // wires && regs
        //
        reg  clk;
        reg  rstn;
 
        wire [31:0] adr;
        wire [ 7:0] dat_i, dat_o;
        wire we;
        wire stb;
        wire cyc;
        wire ack;
        wire inta;
 
        reg [7:0] q, qq;
 
        wire scl, scl_o, scl_oen;
        wire sda, sda_o, sda_oen;
        reg rscl, rsda;
 
        parameter PRER_LO = 3'b000;
        parameter PRER_HI = 3'b001;
        parameter CTR     = 3'b010;
        parameter RXR     = 3'b011;
        parameter TXR     = 3'b011;
        parameter CR      = 3'b100;
        parameter SR      = 3'b100;
 
        parameter TXR_R   = 3'b101; // undocumented / reserved output
        parameter CR_R    = 3'b110; // undocumented / reserved output
 
        parameter RD      = 1'b1;
        parameter WR      = 1'b0;
        parameter SADR    = 7'b0010_000;
 
        //
        // Module body
        //
 
        // generate clock
        always #5 clk = ~clk;
 
        // hookup wishbone master model
        wb_master_model #(8, 32) u0 (
                .clk(clk),
                .rst(rstn),
                .adr(adr),
                .din(dat_i),
                .dout(dat_o),
                .cyc(cyc),
                .stb(stb),
                .we(we),
                .sel(),
                .ack(ack),
                .err(1'b0),
                .rty(1'b0)
        );
 
        // hookup wishbone_i2c_master core
        i2c_master_top i2c_top (
 
                // wishbone interface
                .wb_clk_i(clk),
                .wb_rst_i(1'b0),
                .arst_i(rstn),
                .wb_adr_i(adr[2:0]),
                .wb_dat_i(dat_o),
                .wb_dat_o(dat_i),
                .wb_we_i(we),
                .wb_stb_i(stb),
                .wb_cyc_i(cyc),
                .wb_ack_o(ack),
                .wb_inta_o(inta),
 
                // i2c signals
                .scl_pad_i(scl),
                .scl_pad_o(scl_o),
                .scl_padoen_o(scl_oen),
                .sda_pad_i(sda),
                .sda_pad_o(sda_o),
                .sda_padoen_o(sda_oen)
        );
 
        // hookup i2c slave model
        i2c_slave_model #(SADR) i2c_slave (
                .scl(scl),
                .sda(sda)
        );
 
        // create i2c lines
        always rscl = #600 scl_oen ? 1'bz : scl_o; // create tri-state buffer for i2c_master scl line
        always rsda = #600 sda_oen ? 1'bz : sda_o; // create tri-state buffer for i2c_master sda line
 
        assign scl = rscl;
        assign sda = rsda;
 
        pullup p1(scl); // pullup scl line
        pullup p2(sda); // pullup sda line
 
        initial
          begin
              `ifdef WAVES
                 $shm_open("waves");
                 $shm_probe("AS",tst_bench_top,"AS");
                 $display("INFO: Signal dump enabled ...\n\n");
              `endif
 
//            force i2c_slave.debug = 1'b1; // enable i2c_slave debug information
              force i2c_slave.debug = 1'b0; // disable i2c_slave debug information
 
              $display("\nstatus: %t Testbench started\n\n", $time);
 
//            $dumpfile("bench.vcd");
//            $dumpvars(1, tst_bench_top);
//            $dumpvars(1, tst_bench_top.i2c_slave);
 
              // initially values
              clk = 0;
 
              // reset system
              rstn = 1'b1; // negate reset
              #2;
              rstn = 1'b0; // assert reset
              repeat(1) @(posedge clk);
              rstn = 1'b1; // negate reset
 
              $display("status: %t done reset", $time);
 
              @(posedge clk);
 
              //
              // program core
              //
 
              // program internal registers
              u0.wb_write(1, PRER_LO, 8'hfa); // load prescaler lo-byte
              u0.wb_write(1, PRER_LO, 8'hc8); // load prescaler lo-byte
              u0.wb_write(1, PRER_HI, 8'h00); // load prescaler hi-byte
              $display("status: %t programmed registers", $time);
 
              u0.wb_cmp(0, PRER_LO, 8'hc8); // verify prescaler lo-byte
              u0.wb_cmp(0, PRER_HI, 8'h00); // verify prescaler hi-byte
              $display("status: %t verified registers", $time);
 
              u0.wb_write(1, CTR,     8'h80); // enable core
              $display("status: %t core enabled", $time);
 
              //
              // access slave (write)
              //
 
              // drive slave address
              u0.wb_write(1, TXR, {SADR,WR} ); // present slave address, set write-bit
              u0.wb_write(0, CR,      8'h90 ); // set command (start, write)
              $display("status: %t generate 'start', write cmd %0h (slave address+write)", $time, {SADR,WR} );
 
              // check tip bit
              u0.wb_read(1, SR, q);
              while(q[1])
                   u0.wb_read(0, SR, q); // poll it until it is zero
              $display("status: %t tip==0", $time);
 
              // send memory address
              u0.wb_write(1, TXR,     8'h01); // present slave's memory address
              u0.wb_write(0, CR,      8'h10); // set command (write)
              $display("status: %t write slave memory address 01", $time);
 
              // check tip bit
              u0.wb_read(1, SR, q);
              while(q[1])
                   u0.wb_read(0, SR, q); // poll it until it is zero
              $display("status: %t tip==0", $time);
 
              // send memory contents
              u0.wb_write(1, TXR,     8'ha5); // present data
              u0.wb_write(0, CR,      8'h10); // set command (write)
              $display("status: %t write data a5", $time);
 
              // check tip bit
              u0.wb_read(1, SR, q);
              while(q[1])
                   u0.wb_read(1, SR, q); // poll it until it is zero
              $display("status: %t tip==0", $time);
 
              // send memory contents for next memory address (auto_inc)
              u0.wb_write(1, TXR,     8'h5a); // present data
              u0.wb_write(0, CR,      8'h50); // set command (stop, write)
              $display("status: %t write next data 5a, generate 'stop'", $time);
 
              // check tip bit
              u0.wb_read(1, SR, q);
              while(q[1])
                   u0.wb_read(1, SR, q); // poll it until it is zero
              $display("status: %t tip==0", $time);
 
              //
              // delay
              //
//            #100000; // wait for 100us.
//            $display("status: %t wait 100us", $time);
 
              //
              // access slave (read)
              //
 
              // drive slave address
              u0.wb_write(1, TXR,{SADR,WR} ); // present slave address, set write-bit
              u0.wb_write(0, CR,     8'h90 ); // set command (start, write)
              $display("status: %t generate 'start', write cmd %0h (slave address+write)", $time, {SADR,WR} );
 
              // check tip bit
              u0.wb_read(1, SR, q);
              while(q[1])
                   u0.wb_read(1, SR, q); // poll it until it is zero
              $display("status: %t tip==0", $time);
 
              // send memory address
              u0.wb_write(1, TXR,     8'h01); // present slave's memory address
              u0.wb_write(0, CR,      8'h10); // set command (write)
              $display("status: %t write slave address 01", $time);
 
              // check tip bit
              u0.wb_read(1, SR, q);
              while(q[1])
                   u0.wb_read(1, SR, q); // poll it until it is zero
              $display("status: %t tip==0", $time);
 
              // drive slave address
              u0.wb_write(1, TXR, {SADR,RD} ); // present slave's address, set read-bit
              u0.wb_write(0, CR,      8'h90 ); // set command (start, write)
              $display("status: %t generate 'repeated start', write cmd %0h (slave address+read)", $time, {SADR,RD} );
 
              // check tip bit
              u0.wb_read(1, SR, q);
              while(q[1])
                   u0.wb_read(1, SR, q); // poll it until it is zero
              $display("status: %t tip==0", $time);
 
              // read data from slave
              u0.wb_write(1, CR,      8'h20); // set command (read, ack_read)
              $display("status: %t read + ack", $time);
 
              // check tip bit
              u0.wb_read(1, SR, q);
              while(q[1])
                   u0.wb_read(1, SR, q); // poll it until it is zero
              $display("status: %t tip==0", $time);
 
              // check data just received
              u0.wb_read(1, RXR, qq);
              if(qq !== 8'ha5)
                $display("\nERROR: Expected a5, received %x at time %t", qq, $time);
              else
                $display("status: %t received %x", $time, qq);
 
              // read data from slave
              u0.wb_write(1, CR,      8'h20); // set command (read, ack_read)
              $display("status: %t read + ack", $time);
 
              // check tip bit
              u0.wb_read(1, SR, q);
              while(q[1])
                   u0.wb_read(1, SR, q); // poll it until it is zero
              $display("status: %t tip==0", $time);
 
              // check data just received
              u0.wb_read(1, RXR, qq);
              if(qq !== 8'h5a)
                $display("\nERROR: Expected 5a, received %x at time %t", qq, $time);
              else
                $display("status: %t received %x", $time, qq);
 
              // read data from slave
              u0.wb_write(1, CR,      8'h20); // set command (read, ack_read)
              $display("status: %t read + ack", $time);
 
              // check tip bit
              u0.wb_read(1, SR, q);
              while(q[1])
                   u0.wb_read(1, SR, q); // poll it until it is zero
              $display("status: %t tip==0", $time);
 
              // check data just received
              u0.wb_read(1, RXR, qq);
              $display("status: %t received %x from 3rd read address", $time, qq);
 
              // read data from slave
              u0.wb_write(1, CR,      8'h28); // set command (read, nack_read)
              $display("status: %t read + nack", $time);
 
              // check tip bit
              u0.wb_read(1, SR, q);
              while(q[1])
                   u0.wb_read(1, SR, q); // poll it until it is zero
              $display("status: %t tip==0", $time);
 
              // check data just received
              u0.wb_read(1, RXR, qq);
              $display("status: %t received %x from 4th read address", $time, qq);
 
              //
              // check invalid slave memory address
              //
 
              // drive slave address
              u0.wb_write(1, TXR, {SADR,WR} ); // present slave address, set write-bit
              u0.wb_write(0, CR,      8'h90 ); // set command (start, write)
              $display("status: %t generate 'start', write cmd %0h (slave address+write). Check invalid address", $time, {SADR,WR} );
 
              // check tip bit
              u0.wb_read(1, SR, q);
              while(q[1])
                   u0.wb_read(1, SR, q); // poll it until it is zero
              $display("status: %t tip==0", $time);
 
              // send memory address
              u0.wb_write(1, TXR,     8'h10); // present slave's memory address
              u0.wb_write(0, CR,      8'h10); // set command (write)
              $display("status: %t write slave memory address 10", $time);
 
              // check tip bit
              u0.wb_read(1, SR, q);
              while(q[1])
                   u0.wb_read(1, SR, q); // poll it until it is zero
              $display("status: %t tip==0", $time);
 
              // slave should have send NACK
              $display("status: %t Check for nack", $time);
              if(!q[7])
                $display("\nERROR: Expected NACK, received ACK\n");
 
              // read data from slave
              u0.wb_write(1, CR,      8'h40); // set command (stop)
              $display("status: %t generate 'stop'", $time);
 
              // check tip bit
              u0.wb_read(1, SR, q);
              while(q[1])
              u0.wb_read(1, SR, q); // poll it until it is zero
              $display("status: %t tip==0", $time);
 
              #250000; // wait 250us
              $display("\n\nstatus: %t Testbench done", $time);
              $finish;
          end
 
endmodule
 
 
 

Line No.	Rev	Author	Line
1	19	rherveille	`/////////////////////////////////////////////////////////////////////`
2			`//// ////`
3			`//// WISHBONE rev.B2 compliant I2C Master controller Testbench ////`
4			`//// ////`
5			`//// ////`
6			`//// Author: Richard Herveille ////`
7			`//// richard@asics.ws ////`
8			`//// www.asics.ws ////`
9			`//// ////`
10			`//// Downloaded from: http://www.opencores.org/projects/i2c/ ////`
11			`//// ////`
12			`/////////////////////////////////////////////////////////////////////`
13			`//// ////`
14			`//// Copyright (C) 2001 Richard Herveille ////`
15			`//// richard@asics.ws ////`
16			`//// ////`
17			`//// This source file may be used and distributed without ////`
18			`//// restriction provided that this copyright statement is not ////`
19			`//// removed from the file and that any derivative work contains ////`
20			`//// the original copyright notice and the associated disclaimer.////`
21			`//// ////`
22			//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY ////
23			`//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED ////`
24			`//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ////`
25			`//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR ////`
26			`//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ////`
27			`//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ////`
28			`//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE ////`
29			`//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR ////`
30			`//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ////`
31			`//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ////`
32			`//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT ////`
33			`//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ////`
34			`//// POSSIBILITY OF SUCH DAMAGE. ////`
35			`//// ////`
36			`/////////////////////////////////////////////////////////////////////`
37
38			`// CVS Log`
39	10	rherveille	`//`
40	50	rherveille	`// $Id: tst_bench_top.v,v 1.6 2004-02-28 15:40:42 rherveille Exp $`
41	10	rherveille	`//`
42	50	rherveille	`// $Date: 2004-02-28 15:40:42 $`
43			`// $Revision: 1.6 $`
44	19	rherveille	`// $Author: rherveille $`
45			`// $Locker: $`
46			`// $State: Exp $`
47			`//`
48			`// Change History:`
49			`// $Log: not supported by cvs2svn $`
50	50	rherveille	`// Revision 1.4 2003/12/05 11:04:38 rherveille`
51			`// Added slave address configurability`
52	45	rherveille	`//`
53	50	rherveille	`// Revision 1.3 2002/10/30 18:11:06 rherveille`
54			`// Added timing tests to i2c_model.`
55			`// Updated testbench.`
56			`//`
57			`// Revision 1.2 2002/03/17 10:26:38 rherveille`
58			`// Fixed some race conditions in the i2c-slave model.`
59			`// Added debug information.`
60			`// Added headers.`
61			`//`
62	10	rherveille
63			`include "timescale.v"
64
65			`module tst_bench_top();`
66
67			`//`
68			`// wires && regs`
69			`//`
70			`reg clk;`
71			`reg rstn;`
72
73			`wire [31:0] adr;`
74			`wire [ 7:0] dat_i, dat_o;`
75			`wire we;`
76			`wire stb;`
77			`wire cyc;`
78			`wire ack;`
79			`wire inta;`
80
81	50	rherveille	`reg [7:0] q, qq;`
82	10	rherveille
83	50	rherveille	`wire scl, scl_o, scl_oen;`
84			`wire sda, sda_o, sda_oen;`
85			`reg rscl, rsda;`
86	10	rherveille
87	50	rherveille	`parameter PRER_LO = 3'b000;`
88			`parameter PRER_HI = 3'b001;`
89			`parameter CTR = 3'b010;`
90			`parameter RXR = 3'b011;`
91			`parameter TXR = 3'b011;`
92			`parameter CR = 3'b100;`
93			`parameter SR = 3'b100;`
94	10	rherveille
95	50	rherveille	`parameter TXR_R = 3'b101; // undocumented / reserved output`
96			`parameter CR_R = 3'b110; // undocumented / reserved output`
97
98			`parameter RD = 1'b1;`
99			`parameter WR = 1'b0;`
100			`parameter SADR = 7'b0010_000;`
101
102	10	rherveille	`//`
103			`// Module body`
104			`//`
105
106			`// generate clock`
107			`always #5 clk = ~clk;`
108
109			`// hookup wishbone master model`
110	19	rherveille	`wb_master_model #(8, 32) u0 (`
111	50	rherveille	`.clk(clk),`
112			`.rst(rstn),`
113			`.adr(adr),`
114			`.din(dat_i),`
115	10	rherveille	`.dout(dat_o),`
116	50	rherveille	`.cyc(cyc),`
117			`.stb(stb),`
118			`.we(we),`
119			`.sel(),`
120			`.ack(ack),`
121			`.err(1'b0),`
122			`.rty(1'b0)`
123	10	rherveille	`);`
124
125	50	rherveille	`// hookup wishbone_i2c_master core`
126			`i2c_master_top i2c_top (`
127
128	10	rherveille	`// wishbone interface`
129	50	rherveille	`.wb_clk_i(clk),`
130			`.wb_rst_i(1'b0),`
131			`.arst_i(rstn),`
132			`.wb_adr_i(adr[2:0]),`
133			`.wb_dat_i(dat_o),`
134			`.wb_dat_o(dat_i),`
135			`.wb_we_i(we),`
136			`.wb_stb_i(stb),`
137			`.wb_cyc_i(cyc),`
138			`.wb_ack_o(ack),`
139			`.wb_inta_o(inta),`
140	10	rherveille
141	50	rherveille	`// i2c signals`
142			`.scl_pad_i(scl),`
143			`.scl_pad_o(scl_o),`
144			`.scl_padoen_o(scl_oen),`
145			`.sda_pad_i(sda),`
146			`.sda_pad_o(sda_o),`
147			`.sda_padoen_o(sda_oen)`
148	10	rherveille	`);`
149
150	50	rherveille	`// hookup i2c slave model`
151			`i2c_slave_model #(SADR) i2c_slave (`
152			`.scl(scl),`
153			`.sda(sda)`
154	10	rherveille	`);`
155
156	50	rherveille	`// create i2c lines`
157			`always rscl = #600 scl_oen ? 1'bz : scl_o; // create tri-state buffer for i2c_master scl line`
158			`always rsda = #600 sda_oen ? 1'bz : sda_o; // create tri-state buffer for i2c_master sda line`
159
160			`assign scl = rscl;`
161			`assign sda = rsda;`
162
163			`pullup p1(scl); // pullup scl line`
164			`pullup p2(sda); // pullup sda line`
165
166	10	rherveille	`initial`
167	25	rherveille	`begin`
168			`ifdef WAVES
169			`$shm_open("waves");`
170			`$shm_probe("AS",tst_bench_top,"AS");`
171			`$display("INFO: Signal dump enabled ...\n\n");`
172			`endif
173	19	rherveille
174	50	rherveille	`// force i2c_slave.debug = 1'b1; // enable i2c_slave debug information`
175			`force i2c_slave.debug = 1'b0; // disable i2c_slave debug information`
176	19	rherveille
177	25	rherveille	`$display("\nstatus: %t Testbench started\n\n", $time);`
178	19	rherveille
179	50	rherveille	`// $dumpfile("bench.vcd");`
180			`// $dumpvars(1, tst_bench_top);`
181			`// $dumpvars(1, tst_bench_top.i2c_slave);`
182	10	rherveille
183	25	rherveille	`// initially values`
184			`clk = 0;`
185	19	rherveille
186	25	rherveille	`// reset system`
187			`rstn = 1'b1; // negate reset`
188			`#2;`
189			`rstn = 1'b0; // assert reset`
190	45	rherveille	`repeat(1) @(posedge clk);`
191	25	rherveille	`rstn = 1'b1; // negate reset`
192	10	rherveille
193	25	rherveille	`$display("status: %t done reset", $time);`
194	10	rherveille
195	25	rherveille	`@(posedge clk);`
196	10	rherveille
197	25	rherveille	`//`
198			`// program core`
199			`//`
200	19	rherveille
201	50	rherveille	`// program internal registers`
202			`u0.wb_write(1, PRER_LO, 8'hfa); // load prescaler lo-byte`
203			`u0.wb_write(1, PRER_LO, 8'hc8); // load prescaler lo-byte`
204			`u0.wb_write(1, PRER_HI, 8'h00); // load prescaler hi-byte`
205			`$display("status: %t programmed registers", $time);`
206	19	rherveille
207	50	rherveille	`u0.wb_cmp(0, PRER_LO, 8'hc8); // verify prescaler lo-byte`
208			`u0.wb_cmp(0, PRER_HI, 8'h00); // verify prescaler hi-byte`
209			`$display("status: %t verified registers", $time);`
210	19	rherveille
211	50	rherveille	`u0.wb_write(1, CTR, 8'h80); // enable core`
212			`$display("status: %t core enabled", $time);`
213	10	rherveille
214	50	rherveille	`//`
215			`// access slave (write)`
216			`//`
217	19	rherveille
218	50	rherveille	`// drive slave address`
219			`u0.wb_write(1, TXR, {SADR,WR} ); // present slave address, set write-bit`
220			`u0.wb_write(0, CR, 8'h90 ); // set command (start, write)`
221			`$display("status: %t generate 'start', write cmd %0h (slave address+write)", $time, {SADR,WR} );`
222	10	rherveille
223	25	rherveille	`// check tip bit`
224	50	rherveille	`u0.wb_read(1, SR, q);`
225			`while(q[1])`
226			`u0.wb_read(0, SR, q); // poll it until it is zero`
227			`$display("status: %t tip==0", $time);`
228	10	rherveille
229	50	rherveille	`// send memory address`
230			`u0.wb_write(1, TXR, 8'h01); // present slave's memory address`
231			`u0.wb_write(0, CR, 8'h10); // set command (write)`
232			`$display("status: %t write slave memory address 01", $time);`
233
234			`// check tip bit`
235			`u0.wb_read(1, SR, q);`
236			`while(q[1])`
237			`u0.wb_read(0, SR, q); // poll it until it is zero`
238			`$display("status: %t tip==0", $time);`
239
240			`// send memory contents`
241			`u0.wb_write(1, TXR, 8'ha5); // present data`
242			`u0.wb_write(0, CR, 8'h10); // set command (write)`
243			`$display("status: %t write data a5", $time);`
244
245			`// check tip bit`
246			`u0.wb_read(1, SR, q);`
247			`while(q[1])`
248			`u0.wb_read(1, SR, q); // poll it until it is zero`
249			`$display("status: %t tip==0", $time);`
250
251			`// send memory contents for next memory address (auto_inc)`
252			`u0.wb_write(1, TXR, 8'h5a); // present data`
253			`u0.wb_write(0, CR, 8'h50); // set command (stop, write)`
254			`$display("status: %t write next data 5a, generate 'stop'", $time);`
255
256			`// check tip bit`
257			`u0.wb_read(1, SR, q);`
258			`while(q[1])`
259			`u0.wb_read(1, SR, q); // poll it until it is zero`
260			`$display("status: %t tip==0", $time);`
261
262			`//`
263			`// delay`
264			`//`
265			`// #100000; // wait for 100us.`
266			`// $display("status: %t wait 100us", $time);`
267
268			`//`
269			`// access slave (read)`
270			`//`
271
272			`// drive slave address`
273			`u0.wb_write(1, TXR,{SADR,WR} ); // present slave address, set write-bit`
274			`u0.wb_write(0, CR, 8'h90 ); // set command (start, write)`
275			`$display("status: %t generate 'start', write cmd %0h (slave address+write)", $time, {SADR,WR} );`
276
277			`// check tip bit`
278			`u0.wb_read(1, SR, q);`
279			`while(q[1])`
280			`u0.wb_read(1, SR, q); // poll it until it is zero`
281			`$display("status: %t tip==0", $time);`
282
283			`// send memory address`
284			`u0.wb_write(1, TXR, 8'h01); // present slave's memory address`
285			`u0.wb_write(0, CR, 8'h10); // set command (write)`
286			`$display("status: %t write slave address 01", $time);`
287
288			`// check tip bit`
289			`u0.wb_read(1, SR, q);`
290			`while(q[1])`
291			`u0.wb_read(1, SR, q); // poll it until it is zero`
292			`$display("status: %t tip==0", $time);`
293
294			`// drive slave address`
295			`u0.wb_write(1, TXR, {SADR,RD} ); // present slave's address, set read-bit`
296			`u0.wb_write(0, CR, 8'h90 ); // set command (start, write)`
297			`$display("status: %t generate 'repeated start', write cmd %0h (slave address+read)", $time, {SADR,RD} );`
298
299			`// check tip bit`
300			`u0.wb_read(1, SR, q);`
301			`while(q[1])`
302			`u0.wb_read(1, SR, q); // poll it until it is zero`
303			`$display("status: %t tip==0", $time);`
304
305			`// read data from slave`
306			`u0.wb_write(1, CR, 8'h20); // set command (read, ack_read)`
307			`$display("status: %t read + ack", $time);`
308
309			`// check tip bit`
310			`u0.wb_read(1, SR, q);`
311			`while(q[1])`
312			`u0.wb_read(1, SR, q); // poll it until it is zero`
313			`$display("status: %t tip==0", $time);`
314
315			`// check data just received`
316			`u0.wb_read(1, RXR, qq);`
317			`if(qq !== 8'ha5)`
318			`$display("\nERROR: Expected a5, received %x at time %t", qq, $time);`
319			`else`
320			`$display("status: %t received %x", $time, qq);`
321
322			`// read data from slave`
323			`u0.wb_write(1, CR, 8'h20); // set command (read, ack_read)`
324			`$display("status: %t read + ack", $time);`
325
326			`// check tip bit`
327			`u0.wb_read(1, SR, q);`
328			`while(q[1])`
329			`u0.wb_read(1, SR, q); // poll it until it is zero`
330			`$display("status: %t tip==0", $time);`
331
332			`// check data just received`
333			`u0.wb_read(1, RXR, qq);`
334			`if(qq !== 8'h5a)`
335			`$display("\nERROR: Expected 5a, received %x at time %t", qq, $time);`
336			`else`
337			`$display("status: %t received %x", $time, qq);`
338
339			`// read data from slave`
340			`u0.wb_write(1, CR, 8'h20); // set command (read, ack_read)`
341			`$display("status: %t read + ack", $time);`
342
343			`// check tip bit`
344			`u0.wb_read(1, SR, q);`
345			`while(q[1])`
346			`u0.wb_read(1, SR, q); // poll it until it is zero`
347			`$display("status: %t tip==0", $time);`
348
349			`// check data just received`
350			`u0.wb_read(1, RXR, qq);`
351			`$display("status: %t received %x from 3rd read address", $time, qq);`
352
353			`// read data from slave`
354			`u0.wb_write(1, CR, 8'h28); // set command (read, nack_read)`
355			`$display("status: %t read + nack", $time);`
356
357			`// check tip bit`
358			`u0.wb_read(1, SR, q);`
359			`while(q[1])`
360			`u0.wb_read(1, SR, q); // poll it until it is zero`
361			`$display("status: %t tip==0", $time);`
362
363			`// check data just received`
364			`u0.wb_read(1, RXR, qq);`
365			`$display("status: %t received %x from 4th read address", $time, qq);`
366
367			`//`
368			`// check invalid slave memory address`
369			`//`
370
371			`// drive slave address`
372			`u0.wb_write(1, TXR, {SADR,WR} ); // present slave address, set write-bit`
373			`u0.wb_write(0, CR, 8'h90 ); // set command (start, write)`
374			`$display("status: %t generate 'start', write cmd %0h (slave address+write). Check invalid address", $time, {SADR,WR} );`
375
376			`// check tip bit`
377			`u0.wb_read(1, SR, q);`
378			`while(q[1])`
379			`u0.wb_read(1, SR, q); // poll it until it is zero`
380			`$display("status: %t tip==0", $time);`
381
382			`// send memory address`
383			`u0.wb_write(1, TXR, 8'h10); // present slave's memory address`
384			`u0.wb_write(0, CR, 8'h10); // set command (write)`
385			`$display("status: %t write slave memory address 10", $time);`
386
387			`// check tip bit`
388			`u0.wb_read(1, SR, q);`
389			`while(q[1])`
390			`u0.wb_read(1, SR, q); // poll it until it is zero`
391			`$display("status: %t tip==0", $time);`
392
393			`// slave should have send NACK`
394			`$display("status: %t Check for nack", $time);`
395			`if(!q[7])`
396			`$display("\nERROR: Expected NACK, received ACK\n");`
397
398			`// read data from slave`
399			`u0.wb_write(1, CR, 8'h40); // set command (stop)`
400			`$display("status: %t generate 'stop'", $time);`
401
402			`// check tip bit`
403			`u0.wb_read(1, SR, q);`
404			`while(q[1])`
405			`u0.wb_read(1, SR, q); // poll it until it is zero`
406			`$display("status: %t tip==0", $time);`
407
408	45	rherveille	`#250000; // wait 250us`
409	25	rherveille	`$display("\n\nstatus: %t Testbench done", $time);`
410			`$finish;`
411			`end`
412	19	rherveille
413	10	rherveille	`endmodule`
414
415	50	rherveille
416

Browse

Tools

Subversion Repositories i2c

[/] [i2c/] [trunk/] [bench/] [verilog/] [tst_bench_top.v] - Blame information for rev 50