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/////////////////////////////////////////////////////////////////////
////                                                             ////
////  WISHBONE rev.B2 compliant I2C Master controller Testbench  ////
////                                                             ////
////                                                             ////
////  Author: Richard Herveille                                  ////
////          richard@asics.ws                                   ////
////          www.asics.ws                                       ////
////                                                             ////
////  Downloaded from: http://www.opencores.org/projects/i2c/    ////
////                                                             ////
/////////////////////////////////////////////////////////////////////
////                                                             ////
//// Copyright (C) 2001 Richard Herveille                        ////
////                    richard@asics.ws                         ////
////                                                             ////
//// This source file may be used and distributed without        ////
//// restriction provided that this copyright statement is not   ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer.////
////                                                             ////
////     THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY     ////
//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED   ////
//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS   ////
//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR      ////
//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,         ////
//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES    ////
//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE   ////
//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR        ////
//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF  ////
//// LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT  ////
//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT  ////
//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE         ////
//// POSSIBILITY OF SUCH DAMAGE.                                 ////
////                                                             ////
/////////////////////////////////////////////////////////////////////
 
//  CVS Log
//
//  $Id: tst_bench_top.v,v 1.7 2005-02-27 09:24:18 rherveille Exp $
//
//  $Date: 2005-02-27 09:24:18 $
//  $Revision: 1.7 $
//  $Author: rherveille $
//  $Locker:  $
//  $State: Exp $
//
// Change History:
//               $Log: not supported by cvs2svn $
//               Revision 1.6  2004/02/28 15:40:42  rherveille
//               *** empty log message ***
//
//               Revision 1.4  2003/12/05 11:04:38  rherveille
//               Added slave address configurability
//
//               Revision 1.3  2002/10/30 18:11:06  rherveille
//               Added timing tests to i2c_model.
//               Updated testbench.
//
//               Revision 1.2  2002/03/17 10:26:38  rherveille
//               Fixed some race conditions in the i2c-slave model.
//               Added debug information.
//               Added headers.
//
 
`include "timescale.v"
 
module tst_bench_top();
 
        //
        // wires && regs
        //
        reg  clk;
        reg  rstn;
 
        wire [31:0] adr;
        wire [ 7:0] dat_i, dat_o, dat0_i, dat1_i;
        wire we;
        wire stb;
        wire cyc;
        wire ack;
        wire inta;
 
        reg [7:0] q, qq;
 
        wire scl, scl0_o, scl0_oen, scl1_o, scl1_oen;
        wire sda, sda0_o, sda0_oen, sda1_o, sda1_oen;
 
        parameter PRER_LO = 3'b000;
        parameter PRER_HI = 3'b001;
        parameter CTR     = 3'b010;
        parameter RXR     = 3'b011;
        parameter TXR     = 3'b011;
        parameter CR      = 3'b100;
        parameter SR      = 3'b100;
 
        parameter TXR_R   = 3'b101; // undocumented / reserved output
        parameter CR_R    = 3'b110; // undocumented / reserved output
 
        parameter RD      = 1'b1;
        parameter WR      = 1'b0;
        parameter SADR    = 7'b0010_000;
 
        //
        // Module body
        //
 
        // generate clock
        always #5 clk = ~clk;
 
        // hookup wishbone master model
        wb_master_model #(8, 32) u0 (
                .clk(clk),
                .rst(rstn),
                .adr(adr),
                .din(dat_i),
                .dout(dat_o),
                .cyc(cyc),
                .stb(stb),
                .we(we),
                .sel(),
                .ack(ack),
                .err(1'b0),
                .rty(1'b0)
        );
 
        wire stb0 = stb & ~adr[3];
        wire stb1 = stb &  adr[3];
 
        assign dat_i = ({{8'd8}{stb0}} & dat0_i) | ({{8'd8}{stb1}} & dat1_i);
 
        // hookup wishbone_i2c_master core
        i2c_master_top i2c_top (
 
                // wishbone interface
                .wb_clk_i(clk),
                .wb_rst_i(1'b0),
                .arst_i(rstn),
                .wb_adr_i(adr[2:0]),
                .wb_dat_i(dat_o),
                .wb_dat_o(dat0_i),
                .wb_we_i(we),
                .wb_stb_i(stb0),
                .wb_cyc_i(cyc),
                .wb_ack_o(ack),
                .wb_inta_o(inta),
 
                // i2c signals
                .scl_pad_i(scl),
                .scl_pad_o(scl0_o),
                .scl_padoen_o(scl0_oen),
                .sda_pad_i(sda),
                .sda_pad_o(sda0_o),
                .sda_padoen_o(sda0_oen)
        ),
        i2c_top2 (
 
                // wishbone interface
                .wb_clk_i(clk),
                .wb_rst_i(1'b0),
                .arst_i(rstn),
                .wb_adr_i(adr[2:0]),
                .wb_dat_i(dat_o),
                .wb_dat_o(dat1_i),
                .wb_we_i(we),
                .wb_stb_i(stb1),
                .wb_cyc_i(cyc),
                .wb_ack_o(ack),
                .wb_inta_o(inta),
 
                // i2c signals
                .scl_pad_i(scl),
                .scl_pad_o(scl1_o),
                .scl_padoen_o(scl1_oen),
                .sda_pad_i(sda),
                .sda_pad_o(sda1_o),
                .sda_padoen_o(sda1_oen)
        );
 
 
        // hookup i2c slave model
        i2c_slave_model #(SADR) i2c_slave (
                .scl(scl),
                .sda(sda)
        );
 
        // create i2c lines
        delay m0_scl (scl0_oen ? 1'bz : scl0_o, scl),
              m1_scl (scl1_oen ? 1'bz : scl1_o, scl),
              m0_sda (sda0_oen ? 1'bz : sda0_o, sda),
              m1_sda (sda1_oen ? 1'bz : sda1_o, sda);
 
        pullup p1(scl); // pullup scl line
        pullup p2(sda); // pullup sda line
 
        initial
          begin
              `ifdef WAVES
                 $shm_open("waves");
                 $shm_probe("AS",tst_bench_top,"AS");
                 $display("INFO: Signal dump enabled ...\n\n");
              `endif
 
//            force i2c_slave.debug = 1'b1; // enable i2c_slave debug information
              force i2c_slave.debug = 1'b0; // disable i2c_slave debug information
 
              $display("\nstatus: %t Testbench started\n\n", $time);
 
//            $dumpfile("bench.vcd");
//            $dumpvars(1, tst_bench_top);
//            $dumpvars(1, tst_bench_top.i2c_slave);
 
              // initially values
              clk = 0;
 
              // reset system
              rstn = 1'b1; // negate reset
              #2;
              rstn = 1'b0; // assert reset
              repeat(1) @(posedge clk);
              rstn = 1'b1; // negate reset
 
              $display("status: %t done reset", $time);
 
              @(posedge clk);
 
              //
              // program core
              //
 
              // program internal registers
              u0.wb_write(1, PRER_LO, 8'hfa); // load prescaler lo-byte
              u0.wb_write(1, PRER_LO, 8'hc8); // load prescaler lo-byte
              u0.wb_write(1, PRER_HI, 8'h00); // load prescaler hi-byte
              $display("status: %t programmed registers", $time);
 
              u0.wb_cmp(0, PRER_LO, 8'hc8); // verify prescaler lo-byte
              u0.wb_cmp(0, PRER_HI, 8'h00); // verify prescaler hi-byte
              $display("status: %t verified registers", $time);
 
              u0.wb_write(1, CTR,     8'h80); // enable core
              $display("status: %t core enabled", $time);
 
              //
              // access slave (write)
              //
 
              // drive slave address
              u0.wb_write(1, TXR, {SADR,WR} ); // present slave address, set write-bit
              u0.wb_write(0, CR,      8'h90 ); // set command (start, write)
              $display("status: %t generate 'start', write cmd %0h (slave address+write)", $time, {SADR,WR} );
 
              // check tip bit
              u0.wb_read(1, SR, q);
              while(q[1])
                   u0.wb_read(0, SR, q); // poll it until it is zero
              $display("status: %t tip==0", $time);
 
              // send memory address
              u0.wb_write(1, TXR,     8'h01); // present slave's memory address
              u0.wb_write(0, CR,      8'h10); // set command (write)
              $display("status: %t write slave memory address 01", $time);
 
              // check tip bit
              u0.wb_read(1, SR, q);
              while(q[1])
                   u0.wb_read(0, SR, q); // poll it until it is zero
              $display("status: %t tip==0", $time);
 
              // send memory contents
              u0.wb_write(1, TXR,     8'ha5); // present data
              u0.wb_write(0, CR,      8'h10); // set command (write)
              $display("status: %t write data a5", $time);
 
              // check tip bit
              u0.wb_read(1, SR, q);
              while(q[1])
                   u0.wb_read(1, SR, q); // poll it until it is zero
              $display("status: %t tip==0", $time);
 
              // send memory contents for next memory address (auto_inc)
              u0.wb_write(1, TXR,     8'h5a); // present data
              u0.wb_write(0, CR,      8'h50); // set command (stop, write)
              $display("status: %t write next data 5a, generate 'stop'", $time);
 
              // check tip bit
              u0.wb_read(1, SR, q);
              while(q[1])
                   u0.wb_read(1, SR, q); // poll it until it is zero
              $display("status: %t tip==0", $time);
 
              //
              // delay
              //
//            #100000; // wait for 100us.
//            $display("status: %t wait 100us", $time);
 
              //
              // access slave (read)
              //
 
              // drive slave address
              u0.wb_write(1, TXR,{SADR,WR} ); // present slave address, set write-bit
              u0.wb_write(0, CR,     8'h90 ); // set command (start, write)
              $display("status: %t generate 'start', write cmd %0h (slave address+write)", $time, {SADR,WR} );
 
              // check tip bit
              u0.wb_read(1, SR, q);
              while(q[1])
                   u0.wb_read(1, SR, q); // poll it until it is zero
              $display("status: %t tip==0", $time);
 
              // send memory address
              u0.wb_write(1, TXR,     8'h01); // present slave's memory address
              u0.wb_write(0, CR,      8'h10); // set command (write)
              $display("status: %t write slave address 01", $time);
 
              // check tip bit
              u0.wb_read(1, SR, q);
              while(q[1])
                   u0.wb_read(1, SR, q); // poll it until it is zero
              $display("status: %t tip==0", $time);
 
              // drive slave address
              u0.wb_write(1, TXR, {SADR,RD} ); // present slave's address, set read-bit
              u0.wb_write(0, CR,      8'h90 ); // set command (start, write)
              $display("status: %t generate 'repeated start', write cmd %0h (slave address+read)", $time, {SADR,RD} );
 
              // check tip bit
              u0.wb_read(1, SR, q);
              while(q[1])
                   u0.wb_read(1, SR, q); // poll it until it is zero
              $display("status: %t tip==0", $time);
 
              // read data from slave
              u0.wb_write(1, CR,      8'h20); // set command (read, ack_read)
              $display("status: %t read + ack", $time);
 
              // check tip bit
              u0.wb_read(1, SR, q);
              while(q[1])
                   u0.wb_read(1, SR, q); // poll it until it is zero
              $display("status: %t tip==0", $time);
 
              // check data just received
              u0.wb_read(1, RXR, qq);
              if(qq !== 8'ha5)
                $display("\nERROR: Expected a5, received %x at time %t", qq, $time);
              else
                $display("status: %t received %x", $time, qq);
 
              // read data from slave
              u0.wb_write(1, CR,      8'h20); // set command (read, ack_read)
              $display("status: %t read + ack", $time);
 
              // check tip bit
              u0.wb_read(1, SR, q);
              while(q[1])
                   u0.wb_read(1, SR, q); // poll it until it is zero
              $display("status: %t tip==0", $time);
 
              // check data just received
              u0.wb_read(1, RXR, qq);
              if(qq !== 8'h5a)
                $display("\nERROR: Expected 5a, received %x at time %t", qq, $time);
              else
                $display("status: %t received %x", $time, qq);
 
              // read data from slave
              u0.wb_write(1, CR,      8'h20); // set command (read, ack_read)
              $display("status: %t read + ack", $time);
 
              // check tip bit
              u0.wb_read(1, SR, q);
              while(q[1])
                   u0.wb_read(1, SR, q); // poll it until it is zero
              $display("status: %t tip==0", $time);
 
              // check data just received
              u0.wb_read(1, RXR, qq);
              $display("status: %t received %x from 3rd read address", $time, qq);
 
              // read data from slave
              u0.wb_write(1, CR,      8'h28); // set command (read, nack_read)
              $display("status: %t read + nack", $time);
 
              // check tip bit
              u0.wb_read(1, SR, q);
              while(q[1])
                   u0.wb_read(1, SR, q); // poll it until it is zero
              $display("status: %t tip==0", $time);
 
              // check data just received
              u0.wb_read(1, RXR, qq);
              $display("status: %t received %x from 4th read address", $time, qq);
 
              //
              // check invalid slave memory address
              //
 
              // drive slave address
              u0.wb_write(1, TXR, {SADR,WR} ); // present slave address, set write-bit
              u0.wb_write(0, CR,      8'h90 ); // set command (start, write)
              $display("status: %t generate 'start', write cmd %0h (slave address+write). Check invalid address", $time, {SADR,WR} );
 
              // check tip bit
              u0.wb_read(1, SR, q);
              while(q[1])
                   u0.wb_read(1, SR, q); // poll it until it is zero
              $display("status: %t tip==0", $time);
 
              // send memory address
              u0.wb_write(1, TXR,     8'h10); // present slave's memory address
              u0.wb_write(0, CR,      8'h10); // set command (write)
              $display("status: %t write slave memory address 10", $time);
 
              // check tip bit
              u0.wb_read(1, SR, q);
              while(q[1])
                   u0.wb_read(1, SR, q); // poll it until it is zero
              $display("status: %t tip==0", $time);
 
              // slave should have send NACK
              $display("status: %t Check for nack", $time);
              if(!q[7])
                $display("\nERROR: Expected NACK, received ACK\n");
 
              // read data from slave
              u0.wb_write(1, CR,      8'h40); // set command (stop)
              $display("status: %t generate 'stop'", $time);
 
              // check tip bit
              u0.wb_read(1, SR, q);
              while(q[1])
              u0.wb_read(1, SR, q); // poll it until it is zero
              $display("status: %t tip==0", $time);
 
              #250000; // wait 250us
              $display("\n\nstatus: %t Testbench done", $time);
              $finish;
          end
 
endmodule
 
module delay (in, out);
  input  in;
  output out;
 
  assign out = in;
 
  specify
    (in => out) = (600,600);
  endspecify
endmodule
 
 

Line No.	Rev	Author	Line
1	19	rherveille	`/////////////////////////////////////////////////////////////////////`
2			`//// ////`
3			`//// WISHBONE rev.B2 compliant I2C Master controller Testbench ////`
4			`//// ////`
5			`//// ////`
6			`//// Author: Richard Herveille ////`
7			`//// richard@asics.ws ////`
8			`//// www.asics.ws ////`
9			`//// ////`
10			`//// Downloaded from: http://www.opencores.org/projects/i2c/ ////`
11			`//// ////`
12			`/////////////////////////////////////////////////////////////////////`
13			`//// ////`
14			`//// Copyright (C) 2001 Richard Herveille ////`
15			`//// richard@asics.ws ////`
16			`//// ////`
17			`//// This source file may be used and distributed without ////`
18			`//// restriction provided that this copyright statement is not ////`
19			`//// removed from the file and that any derivative work contains ////`
20			`//// the original copyright notice and the associated disclaimer.////`
21			`//// ////`
22			//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY ////
23			`//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED ////`
24			`//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ////`
25			`//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR ////`
26			`//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ////`
27			`//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ////`
28			`//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE ////`
29			`//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR ////`
30			`//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ////`
31			`//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ////`
32			`//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT ////`
33			`//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ////`
34			`//// POSSIBILITY OF SUCH DAMAGE. ////`
35			`//// ////`
36			`/////////////////////////////////////////////////////////////////////`
37
38			`// CVS Log`
39	10	rherveille	`//`
40	54	rherveille	`// $Id: tst_bench_top.v,v 1.7 2005-02-27 09:24:18 rherveille Exp $`
41	10	rherveille	`//`
42	54	rherveille	`// $Date: 2005-02-27 09:24:18 $`
43			`// $Revision: 1.7 $`
44	19	rherveille	`// $Author: rherveille $`
45			`// $Locker: $`
46			`// $State: Exp $`
47			`//`
48			`// Change History:`
49			`// $Log: not supported by cvs2svn $`
50	54	rherveille	`// Revision 1.6 2004/02/28 15:40:42 rherveille`
51			`// * empty log message *`
52			`//`
53	50	rherveille	`// Revision 1.4 2003/12/05 11:04:38 rherveille`
54			`// Added slave address configurability`
55	45	rherveille	`//`
56	50	rherveille	`// Revision 1.3 2002/10/30 18:11:06 rherveille`
57			`// Added timing tests to i2c_model.`
58			`// Updated testbench.`
59			`//`
60			`// Revision 1.2 2002/03/17 10:26:38 rherveille`
61			`// Fixed some race conditions in the i2c-slave model.`
62			`// Added debug information.`
63			`// Added headers.`
64			`//`
65	10	rherveille
66			`include "timescale.v"
67
68			`module tst_bench_top();`
69
70			`//`
71			`// wires && regs`
72			`//`
73			`reg clk;`
74			`reg rstn;`
75
76			`wire [31:0] adr;`
77	54	rherveille	`wire [ 7:0] dat_i, dat_o, dat0_i, dat1_i;`
78	10	rherveille	`wire we;`
79			`wire stb;`
80			`wire cyc;`
81			`wire ack;`
82			`wire inta;`
83
84	50	rherveille	`reg [7:0] q, qq;`
85	10	rherveille
86	54	rherveille	`wire scl, scl0_o, scl0_oen, scl1_o, scl1_oen;`
87			`wire sda, sda0_o, sda0_oen, sda1_o, sda1_oen;`
88	10	rherveille
89	50	rherveille	`parameter PRER_LO = 3'b000;`
90			`parameter PRER_HI = 3'b001;`
91			`parameter CTR = 3'b010;`
92			`parameter RXR = 3'b011;`
93			`parameter TXR = 3'b011;`
94			`parameter CR = 3'b100;`
95			`parameter SR = 3'b100;`
96	10	rherveille
97	50	rherveille	`parameter TXR_R = 3'b101; // undocumented / reserved output`
98			`parameter CR_R = 3'b110; // undocumented / reserved output`
99
100			`parameter RD = 1'b1;`
101			`parameter WR = 1'b0;`
102			`parameter SADR = 7'b0010_000;`
103
104	10	rherveille	`//`
105			`// Module body`
106			`//`
107
108			`// generate clock`
109			`always #5 clk = ~clk;`
110
111			`// hookup wishbone master model`
112	19	rherveille	`wb_master_model #(8, 32) u0 (`
113	50	rherveille	`.clk(clk),`
114			`.rst(rstn),`
115			`.adr(adr),`
116			`.din(dat_i),`
117	10	rherveille	`.dout(dat_o),`
118	50	rherveille	`.cyc(cyc),`
119			`.stb(stb),`
120			`.we(we),`
121			`.sel(),`
122			`.ack(ack),`
123			`.err(1'b0),`
124			`.rty(1'b0)`
125	10	rherveille	`);`
126
127	54	rherveille	`wire stb0 = stb & ~adr[3];`
128			`wire stb1 = stb & adr[3];`
129
130			`assign dat_i = ({{8'd8}{stb0}} & dat0_i) \| ({{8'd8}{stb1}} & dat1_i);`
131
132	50	rherveille	`// hookup wishbone_i2c_master core`
133			`i2c_master_top i2c_top (`
134
135	10	rherveille	`// wishbone interface`
136	50	rherveille	`.wb_clk_i(clk),`
137			`.wb_rst_i(1'b0),`
138			`.arst_i(rstn),`
139			`.wb_adr_i(adr[2:0]),`
140			`.wb_dat_i(dat_o),`
141	54	rherveille	`.wb_dat_o(dat0_i),`
142	50	rherveille	`.wb_we_i(we),`
143	54	rherveille	`.wb_stb_i(stb0),`
144	50	rherveille	`.wb_cyc_i(cyc),`
145			`.wb_ack_o(ack),`
146			`.wb_inta_o(inta),`
147	10	rherveille
148	50	rherveille	`// i2c signals`
149			`.scl_pad_i(scl),`
150	54	rherveille	`.scl_pad_o(scl0_o),`
151			`.scl_padoen_o(scl0_oen),`
152	50	rherveille	`.sda_pad_i(sda),`
153	54	rherveille	`.sda_pad_o(sda0_o),`
154			`.sda_padoen_o(sda0_oen)`
155			`),`
156			`i2c_top2 (`
157
158			`// wishbone interface`
159			`.wb_clk_i(clk),`
160			`.wb_rst_i(1'b0),`
161			`.arst_i(rstn),`
162			`.wb_adr_i(adr[2:0]),`
163			`.wb_dat_i(dat_o),`
164			`.wb_dat_o(dat1_i),`
165			`.wb_we_i(we),`
166			`.wb_stb_i(stb1),`
167			`.wb_cyc_i(cyc),`
168			`.wb_ack_o(ack),`
169			`.wb_inta_o(inta),`
170
171			`// i2c signals`
172			`.scl_pad_i(scl),`
173			`.scl_pad_o(scl1_o),`
174			`.scl_padoen_o(scl1_oen),`
175			`.sda_pad_i(sda),`
176			`.sda_pad_o(sda1_o),`
177			`.sda_padoen_o(sda1_oen)`
178	10	rherveille	`);`
179
180	54	rherveille
181	50	rherveille	`// hookup i2c slave model`
182			`i2c_slave_model #(SADR) i2c_slave (`
183			`.scl(scl),`
184			`.sda(sda)`
185	10	rherveille	`);`
186
187	54	rherveille	`// create i2c lines`
188			`delay m0_scl (scl0_oen ? 1'bz : scl0_o, scl),`
189			`m1_scl (scl1_oen ? 1'bz : scl1_o, scl),`
190			`m0_sda (sda0_oen ? 1'bz : sda0_o, sda),`
191			`m1_sda (sda1_oen ? 1'bz : sda1_o, sda);`
192	50	rherveille
193			`pullup p1(scl); // pullup scl line`
194			`pullup p2(sda); // pullup sda line`
195
196	10	rherveille	`initial`
197	25	rherveille	`begin`
198			`ifdef WAVES
199			`$shm_open("waves");`
200			`$shm_probe("AS",tst_bench_top,"AS");`
201			`$display("INFO: Signal dump enabled ...\n\n");`
202			`endif
203	19	rherveille
204	50	rherveille	`// force i2c_slave.debug = 1'b1; // enable i2c_slave debug information`
205			`force i2c_slave.debug = 1'b0; // disable i2c_slave debug information`
206	19	rherveille
207	25	rherveille	`$display("\nstatus: %t Testbench started\n\n", $time);`
208	19	rherveille
209	50	rherveille	`// $dumpfile("bench.vcd");`
210			`// $dumpvars(1, tst_bench_top);`
211			`// $dumpvars(1, tst_bench_top.i2c_slave);`
212	10	rherveille
213	25	rherveille	`// initially values`
214			`clk = 0;`
215	19	rherveille
216	25	rherveille	`// reset system`
217			`rstn = 1'b1; // negate reset`
218			`#2;`
219			`rstn = 1'b0; // assert reset`
220	45	rherveille	`repeat(1) @(posedge clk);`
221	25	rherveille	`rstn = 1'b1; // negate reset`
222	10	rherveille
223	25	rherveille	`$display("status: %t done reset", $time);`
224	10	rherveille
225	25	rherveille	`@(posedge clk);`
226	10	rherveille
227	25	rherveille	`//`
228			`// program core`
229			`//`
230	19	rherveille
231	50	rherveille	`// program internal registers`
232			`u0.wb_write(1, PRER_LO, 8'hfa); // load prescaler lo-byte`
233			`u0.wb_write(1, PRER_LO, 8'hc8); // load prescaler lo-byte`
234			`u0.wb_write(1, PRER_HI, 8'h00); // load prescaler hi-byte`
235			`$display("status: %t programmed registers", $time);`
236	19	rherveille
237	50	rherveille	`u0.wb_cmp(0, PRER_LO, 8'hc8); // verify prescaler lo-byte`
238			`u0.wb_cmp(0, PRER_HI, 8'h00); // verify prescaler hi-byte`
239			`$display("status: %t verified registers", $time);`
240	19	rherveille
241	50	rherveille	`u0.wb_write(1, CTR, 8'h80); // enable core`
242			`$display("status: %t core enabled", $time);`
243	10	rherveille
244	50	rherveille	`//`
245			`// access slave (write)`
246			`//`
247	19	rherveille
248	50	rherveille	`// drive slave address`
249			`u0.wb_write(1, TXR, {SADR,WR} ); // present slave address, set write-bit`
250			`u0.wb_write(0, CR, 8'h90 ); // set command (start, write)`
251			`$display("status: %t generate 'start', write cmd %0h (slave address+write)", $time, {SADR,WR} );`
252	10	rherveille
253	25	rherveille	`// check tip bit`
254	50	rherveille	`u0.wb_read(1, SR, q);`
255			`while(q[1])`
256			`u0.wb_read(0, SR, q); // poll it until it is zero`
257			`$display("status: %t tip==0", $time);`
258	10	rherveille
259	50	rherveille	`// send memory address`
260			`u0.wb_write(1, TXR, 8'h01); // present slave's memory address`
261			`u0.wb_write(0, CR, 8'h10); // set command (write)`
262			`$display("status: %t write slave memory address 01", $time);`
263
264			`// check tip bit`
265			`u0.wb_read(1, SR, q);`
266			`while(q[1])`
267			`u0.wb_read(0, SR, q); // poll it until it is zero`
268			`$display("status: %t tip==0", $time);`
269
270			`// send memory contents`
271			`u0.wb_write(1, TXR, 8'ha5); // present data`
272			`u0.wb_write(0, CR, 8'h10); // set command (write)`
273			`$display("status: %t write data a5", $time);`
274
275			`// check tip bit`
276			`u0.wb_read(1, SR, q);`
277			`while(q[1])`
278			`u0.wb_read(1, SR, q); // poll it until it is zero`
279			`$display("status: %t tip==0", $time);`
280
281			`// send memory contents for next memory address (auto_inc)`
282			`u0.wb_write(1, TXR, 8'h5a); // present data`
283			`u0.wb_write(0, CR, 8'h50); // set command (stop, write)`
284			`$display("status: %t write next data 5a, generate 'stop'", $time);`
285
286			`// check tip bit`
287			`u0.wb_read(1, SR, q);`
288			`while(q[1])`
289			`u0.wb_read(1, SR, q); // poll it until it is zero`
290			`$display("status: %t tip==0", $time);`
291
292			`//`
293			`// delay`
294			`//`
295			`// #100000; // wait for 100us.`
296			`// $display("status: %t wait 100us", $time);`
297
298			`//`
299			`// access slave (read)`
300			`//`
301
302			`// drive slave address`
303			`u0.wb_write(1, TXR,{SADR,WR} ); // present slave address, set write-bit`
304			`u0.wb_write(0, CR, 8'h90 ); // set command (start, write)`
305			`$display("status: %t generate 'start', write cmd %0h (slave address+write)", $time, {SADR,WR} );`
306
307			`// check tip bit`
308			`u0.wb_read(1, SR, q);`
309			`while(q[1])`
310			`u0.wb_read(1, SR, q); // poll it until it is zero`
311			`$display("status: %t tip==0", $time);`
312
313			`// send memory address`
314			`u0.wb_write(1, TXR, 8'h01); // present slave's memory address`
315			`u0.wb_write(0, CR, 8'h10); // set command (write)`
316			`$display("status: %t write slave address 01", $time);`
317
318			`// check tip bit`
319			`u0.wb_read(1, SR, q);`
320			`while(q[1])`
321			`u0.wb_read(1, SR, q); // poll it until it is zero`
322			`$display("status: %t tip==0", $time);`
323
324			`// drive slave address`
325			`u0.wb_write(1, TXR, {SADR,RD} ); // present slave's address, set read-bit`
326			`u0.wb_write(0, CR, 8'h90 ); // set command (start, write)`
327			`$display("status: %t generate 'repeated start', write cmd %0h (slave address+read)", $time, {SADR,RD} );`
328
329			`// check tip bit`
330			`u0.wb_read(1, SR, q);`
331			`while(q[1])`
332			`u0.wb_read(1, SR, q); // poll it until it is zero`
333			`$display("status: %t tip==0", $time);`
334
335			`// read data from slave`
336			`u0.wb_write(1, CR, 8'h20); // set command (read, ack_read)`
337			`$display("status: %t read + ack", $time);`
338
339			`// check tip bit`
340			`u0.wb_read(1, SR, q);`
341			`while(q[1])`
342			`u0.wb_read(1, SR, q); // poll it until it is zero`
343			`$display("status: %t tip==0", $time);`
344
345			`// check data just received`
346			`u0.wb_read(1, RXR, qq);`
347			`if(qq !== 8'ha5)`
348			`$display("\nERROR: Expected a5, received %x at time %t", qq, $time);`
349			`else`
350			`$display("status: %t received %x", $time, qq);`
351
352			`// read data from slave`
353			`u0.wb_write(1, CR, 8'h20); // set command (read, ack_read)`
354			`$display("status: %t read + ack", $time);`
355
356			`// check tip bit`
357			`u0.wb_read(1, SR, q);`
358			`while(q[1])`
359			`u0.wb_read(1, SR, q); // poll it until it is zero`
360			`$display("status: %t tip==0", $time);`
361
362			`// check data just received`
363			`u0.wb_read(1, RXR, qq);`
364			`if(qq !== 8'h5a)`
365			`$display("\nERROR: Expected 5a, received %x at time %t", qq, $time);`
366			`else`
367			`$display("status: %t received %x", $time, qq);`
368
369			`// read data from slave`
370			`u0.wb_write(1, CR, 8'h20); // set command (read, ack_read)`
371			`$display("status: %t read + ack", $time);`
372
373			`// check tip bit`
374			`u0.wb_read(1, SR, q);`
375			`while(q[1])`
376			`u0.wb_read(1, SR, q); // poll it until it is zero`
377			`$display("status: %t tip==0", $time);`
378
379			`// check data just received`
380			`u0.wb_read(1, RXR, qq);`
381			`$display("status: %t received %x from 3rd read address", $time, qq);`
382
383			`// read data from slave`
384			`u0.wb_write(1, CR, 8'h28); // set command (read, nack_read)`
385			`$display("status: %t read + nack", $time);`
386
387			`// check tip bit`
388			`u0.wb_read(1, SR, q);`
389			`while(q[1])`
390			`u0.wb_read(1, SR, q); // poll it until it is zero`
391			`$display("status: %t tip==0", $time);`
392
393			`// check data just received`
394			`u0.wb_read(1, RXR, qq);`
395			`$display("status: %t received %x from 4th read address", $time, qq);`
396
397			`//`
398			`// check invalid slave memory address`
399			`//`
400
401			`// drive slave address`
402			`u0.wb_write(1, TXR, {SADR,WR} ); // present slave address, set write-bit`
403			`u0.wb_write(0, CR, 8'h90 ); // set command (start, write)`
404			`$display("status: %t generate 'start', write cmd %0h (slave address+write). Check invalid address", $time, {SADR,WR} );`
405
406			`// check tip bit`
407			`u0.wb_read(1, SR, q);`
408			`while(q[1])`
409			`u0.wb_read(1, SR, q); // poll it until it is zero`
410			`$display("status: %t tip==0", $time);`
411
412			`// send memory address`
413			`u0.wb_write(1, TXR, 8'h10); // present slave's memory address`
414			`u0.wb_write(0, CR, 8'h10); // set command (write)`
415			`$display("status: %t write slave memory address 10", $time);`
416
417			`// check tip bit`
418			`u0.wb_read(1, SR, q);`
419			`while(q[1])`
420			`u0.wb_read(1, SR, q); // poll it until it is zero`
421			`$display("status: %t tip==0", $time);`
422
423			`// slave should have send NACK`
424			`$display("status: %t Check for nack", $time);`
425			`if(!q[7])`
426			`$display("\nERROR: Expected NACK, received ACK\n");`
427
428			`// read data from slave`
429			`u0.wb_write(1, CR, 8'h40); // set command (stop)`
430			`$display("status: %t generate 'stop'", $time);`
431
432			`// check tip bit`
433			`u0.wb_read(1, SR, q);`
434			`while(q[1])`
435			`u0.wb_read(1, SR, q); // poll it until it is zero`
436			`$display("status: %t tip==0", $time);`
437
438	45	rherveille	`#250000; // wait 250us`
439	25	rherveille	`$display("\n\nstatus: %t Testbench done", $time);`
440			`$finish;`
441			`end`
442	19	rherveille
443	10	rherveille	`endmodule`
444
445	54	rherveille	`module delay (in, out);`
446			`input in;`
447			`output out;`
448	50	rherveille
449	54	rherveille	`assign out = in;`
450	50	rherveille
451	54	rherveille	`specify`
452			`(in => out) = (600,600);`
453			`endspecify`
454			`endmodule`
455
456

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