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[/] [i2c/] [trunk/] [bench/] [verilog/] [wb_master_model.v] - Blame information for rev 10

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//
// Wishbone master model
//
 
`include "timescale.v"
 
module wb_master_model(clk, rst, adr, din, dout, cyc, stb, we, ack, err, rty);
 
input         clk, rst;
output [31:0]    adr;
input  [ 7:0]    din;
output [ 7:0]    dout;
output        cyc, stb;
output          we;
input                  ack, err, rty;
 
////////////////////////////////////////////////////////////////////
//
// Local Wires
//
 
reg     [31:0]   adr;
reg     [ 7:0]   dout;
reg                   cyc, stb;
reg                   we;
 
////////////////////////////////////////////////////////////////////
//
// Memory Logic
//
 
initial
        begin
                //adr = 32'hxxxx_xxxx;
                //adr = 0;
                adr  = 32'hxxxx_xxxx;
                dout = 8'hxx;
                cyc  = 1'b0;
                stb  = 1'bx;
                we   = 1'hx;
                #1;
                $display("\nINFO: WISHBONE MASTER MODEL INSTANTIATED (%m)\n");
        end
 
////////////////////////////////////////////////////////////////////
//
// Wishbone write cycle
//
 
task wb_write;
        input        delay;
        integer delay;
 
        input   [31:0]   a;
        input   [ 7:0]   d;
 
        begin
 
                repeat(delay) @(posedge clk);
                #1;
                adr  = a;
                dout = d;
                cyc  = 1'b1;
                stb  = 1'b1;
                we   = 1'b1;
 
                @(posedge clk);
                while(~ack)     @(posedge clk);
                #1;
                cyc  = 1'b0;
                stb  = 1'bx;
                adr  = 32'hxxxx_xxxx;
                dout = 8'hxx;
                we   = 1'hx;
 
        end
endtask
 
////////////////////////////////////////////////////////////////////
//
// Wishbone read cycle
//
 
task wb_read;
        input        delay;
        integer delay;
 
        input    [31:0]  a;
        output  [ 7:0]   d;
 
        begin
 
                repeat(delay) @(posedge clk);
                #1;
                adr  = a;
                dout = 8'hxx;
                cyc  = 1'b1;
                stb  = 1'b1;
                we   = 1'b0;
 
                @(posedge clk);
                while(~ack)     @(posedge clk);
                #1;
                cyc  = 1'b0;
                stb  = 1'bx;
                adr  = 32'hxxxx_xxxx;
                dout = 8'hxx;
                we   = 1'hx;
                d    = din;
 
        end
endtask
 
endmodule

Line No.	Rev	Author	Line
1	10	rherveille	`//`
2			`// Wishbone master model`
3			`//`
4
5			`include "timescale.v"
6
7			`module wb_master_model(clk, rst, adr, din, dout, cyc, stb, we, ack, err, rty);`
8
9			`input clk, rst;`
10			`output [31:0] adr;`
11			`input [ 7:0] din;`
12			`output [ 7:0] dout;`
13			`output cyc, stb;`
14			`output we;`
15			`input ack, err, rty;`
16
17			`////////////////////////////////////////////////////////////////////`
18			`//`
19			`// Local Wires`
20			`//`
21
22			`reg [31:0] adr;`
23			`reg [ 7:0] dout;`
24			`reg cyc, stb;`
25			`reg we;`
26
27			`////////////////////////////////////////////////////////////////////`
28			`//`
29			`// Memory Logic`
30			`//`
31
32			`initial`
33			`begin`
34			`//adr = 32'hxxxx_xxxx;`
35			`//adr = 0;`
36			`adr = 32'hxxxx_xxxx;`
37			`dout = 8'hxx;`
38			`cyc = 1'b0;`
39			`stb = 1'bx;`
40			`we = 1'hx;`
41			`#1;`
42			`$display("\nINFO: WISHBONE MASTER MODEL INSTANTIATED (%m)\n");`
43			`end`
44
45			`////////////////////////////////////////////////////////////////////`
46			`//`
47			`// Wishbone write cycle`
48			`//`
49
50			`task wb_write;`
51			`input delay;`
52			`integer delay;`
53
54			`input [31:0] a;`
55			`input [ 7:0] d;`
56
57			`begin`
58
59			`repeat(delay) @(posedge clk);`
60			`#1;`
61			`adr = a;`
62			`dout = d;`
63			`cyc = 1'b1;`
64			`stb = 1'b1;`
65			`we = 1'b1;`
66
67			`@(posedge clk);`
68			`while(~ack) @(posedge clk);`
69			`#1;`
70			`cyc = 1'b0;`
71			`stb = 1'bx;`
72			`adr = 32'hxxxx_xxxx;`
73			`dout = 8'hxx;`
74			`we = 1'hx;`
75
76			`end`
77			`endtask`
78
79			`////////////////////////////////////////////////////////////////////`
80			`//`
81			`// Wishbone read cycle`
82			`//`
83
84			`task wb_read;`
85			`input delay;`
86			`integer delay;`
87
88			`input [31:0] a;`
89			`output [ 7:0] d;`
90
91			`begin`
92
93			`repeat(delay) @(posedge clk);`
94			`#1;`
95			`adr = a;`
96			`dout = 8'hxx;`
97			`cyc = 1'b1;`
98			`stb = 1'b1;`
99			`we = 1'b0;`
100
101			`@(posedge clk);`
102			`while(~ack) @(posedge clk);`
103			`#1;`
104			`cyc = 1'b0;`
105			`stb = 1'bx;`
106			`adr = 32'hxxxx_xxxx;`
107			`dout = 8'hxx;`
108			`we = 1'hx;`
109			`d = din;`
110
111			`end`
112			`endtask`
113
114			`endmodule`

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[/] [i2c/] [trunk/] [bench/] [verilog/] [wb_master_model.v] - Blame information for rev 10