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[/] [i2c/] [trunk/] [bench/] [verilog/] [wb_master_model.v] - Blame information for rev 10

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1 10 rherveille
//
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// Wishbone master model
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//
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`include "timescale.v"
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module wb_master_model(clk, rst, adr, din, dout, cyc, stb, we, ack, err, rty);
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input         clk, rst;
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output [31:0]    adr;
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input  [ 7:0]    din;
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output [ 7:0]    dout;
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output        cyc, stb;
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output          we;
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input                  ack, err, rty;
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////////////////////////////////////////////////////////////////////
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//
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// Local Wires
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//
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reg     [31:0]   adr;
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reg     [ 7:0]   dout;
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reg                   cyc, stb;
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reg                   we;
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////////////////////////////////////////////////////////////////////
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//
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// Memory Logic
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//
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initial
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        begin
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                //adr = 32'hxxxx_xxxx;
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                //adr = 0;
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                adr  = 32'hxxxx_xxxx;
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                dout = 8'hxx;
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                cyc  = 1'b0;
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                stb  = 1'bx;
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                we   = 1'hx;
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                #1;
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                $display("\nINFO: WISHBONE MASTER MODEL INSTANTIATED (%m)\n");
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        end
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////////////////////////////////////////////////////////////////////
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//
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// Wishbone write cycle
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//
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task wb_write;
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        input        delay;
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        integer delay;
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        input   [31:0]   a;
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        input   [ 7:0]   d;
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        begin
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                repeat(delay) @(posedge clk);
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                #1;
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                adr  = a;
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                dout = d;
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                cyc  = 1'b1;
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                stb  = 1'b1;
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                we   = 1'b1;
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                @(posedge clk);
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                while(~ack)     @(posedge clk);
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                #1;
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                cyc  = 1'b0;
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                stb  = 1'bx;
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                adr  = 32'hxxxx_xxxx;
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                dout = 8'hxx;
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                we   = 1'hx;
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        end
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endtask
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////////////////////////////////////////////////////////////////////
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//
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// Wishbone read cycle
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//
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task wb_read;
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        input        delay;
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        integer delay;
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        input    [31:0]  a;
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        output  [ 7:0]   d;
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        begin
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                repeat(delay) @(posedge clk);
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                #1;
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                adr  = a;
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                dout = 8'hxx;
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                cyc  = 1'b1;
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                stb  = 1'b1;
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                we   = 1'b0;
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                @(posedge clk);
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                while(~ack)     @(posedge clk);
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                #1;
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                cyc  = 1'b0;
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                stb  = 1'bx;
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                adr  = 32'hxxxx_xxxx;
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                dout = 8'hxx;
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                we   = 1'hx;
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                d    = din;
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        end
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endtask
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endmodule

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