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[/] [i2c/] [trunk/] [rtl/] [verilog/] [i2c_master_byte_ctrl.v] - Blame information for rev 10

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//
// WISHBONE revB2 compiant I2C master core
//
// author: Richard Herveille
// rev. 0.1 August 24th, 2001. Initial Verilog release.
//
 
`include "timescale.v"
`include "i2c_master_defines.v"
 
module i2c_master_byte_ctrl (
        clk, rst, nReset, ena, clk_cnt, start, stop, read, write, ack_in, din,
        cmd_ack, ack_out, dout, i2c_busy, scl_i, scl_o, scl_oen, sda_i, sda_o, sda_oen );
 
        //
        // inputs & outputs
        //
        input clk;     // master clock
        input rst;     // synchronous active high reset
        input nReset;  // asynchronous active low reset
        input ena;     // core enable signal
 
        input [15:0] clk_cnt; // 4x SCL
 
        // control inputs
        input       start;
        input       stop;
        input       read;
        input       write;
        input       ack_in;
        input [7:0] din;
 
        // status outputs
        output       cmd_ack;
        reg cmd_ack;
        output       ack_out;
        reg ack_out;
        output       i2c_busy;
        output [7:0] dout;
 
        // I2C signals
        input  scl_i;
        output scl_o;
        output scl_oen;
        input  sda_i;
        output sda_o;
        output sda_oen;
 
 
        //
        // Variable declarations
        //
 
        // statemachine
        parameter [4:0] ST_IDLE  = 5'b0_0000;
        parameter [4:0] ST_START = 5'b0_0001;
        parameter [4:0] ST_READ  = 5'b0_0010;
        parameter [4:0] ST_WRITE = 5'b0_0100;
        parameter [4:0] ST_ACK   = 5'b0_1000;
        parameter [4:0] ST_STOP  = 5'b1_0000;
 
        // signals for bit_controller
        reg  [3:0] core_cmd;
        reg        core_txd;
        wire       core_ack, core_rxd;
 
        // signals for shift register
        reg [7:0] sr; //8bit shift register
        reg       shift, ld;
 
        // signals for state machine
        wire       go;
        reg  [3:0] dcnt;
        wire       cnt_done;
 
        //
        // Module body
        //
 
        // hookup bit_controller
        i2c_master_bit_ctrl bit_controller (
                .clk(clk),
                .rst(rst),
                .nReset(nReset),
                .ena(ena),
                .clk_cnt(clk_cnt),
                .cmd(core_cmd),
                .cmd_ack(core_ack),
                .busy(i2c_busy),
                .din(core_txd),
                .dout(core_rxd),
                .scl_i(scl_i),
                .scl_o(scl_o),
                .scl_oen(scl_oen),
                .sda_i(sda_i),
                .sda_o(sda_o),
                .sda_oen(sda_oen)
        );
 
        // generate go-signal
        assign go = (read || write || stop) && !cmd_ack;
 
        // assign dout output to shift-register
        assign dout = sr;
 
        // generate shift register
        always@(posedge clk or negedge nReset)
                if (!nReset)
                        sr <= #1 8'h0;
                else if (rst)
                        sr <= #1 8'h0;
                else if (ld)
                        sr <= #1 din;
                else if (shift)
                        sr <= #1 {sr[6:0], core_rxd};
 
        // generate counter
        always@(posedge clk or negedge nReset)
                if (!nReset)
                        dcnt <= #1 4'h0;
                else if (rst)
                        dcnt <= #1 4'h0;
                else if (ld)
                        dcnt <= #1 4'h7;
                else if (shift)
                        dcnt <= #1 dcnt - 4'h1;
 
        assign cnt_done = !(|dcnt);
 
        //
        // state machine
        //
        reg [4:0] c_state; // synopsis enum_state
 
        always@(posedge clk or negedge nReset)
                if (!nReset)
                        begin
                                core_cmd <= #1 `I2C_CMD_NOP;
                                core_txd <= #1 sr[7];
 
                                shift    <= #1 1'b0;
                                ld       <= #1 1'b0;
 
                                cmd_ack  <= #1 1'b0;
                                c_state  <= #1 ST_IDLE;
                        end
                else if (rst)
                        begin
                                core_cmd <= #1 `I2C_CMD_NOP;
                                core_txd <= #1 1'b0;
 
                                shift    <= #1 1'b0;
                                ld       <= #1 1'b0;
 
                                cmd_ack  <= #1 1'b0;
                                c_state  <= #1 ST_IDLE;
                        end
        else
        begin
                // initially reset all signals
                core_txd <= #1 sr[7];
 
                shift    <= #1 1'b0;
                ld       <= #1 1'b0;
 
                cmd_ack  <= #1 1'b0;
 
                case (c_state) // synopsis full_case parallel_case
                        ST_IDLE:
                                if (go)
                                        begin
                                                if (start)
                                                        begin
                                                                c_state  <= #1 ST_START;
                                                                core_cmd <= #1 `I2C_CMD_START;
                                                        end
                                                else if (read)
                                                        begin
                                                                c_state  <= #1 ST_READ;
                                                                core_cmd <= #1 `I2C_CMD_READ;
                                                        end
                                                else if (write)
                                                        begin
                                                                c_state  <= #1 ST_WRITE;
                                                                core_cmd <= #1 `I2C_CMD_WRITE;
                                                        end
                                                else // stop
                                                        begin
                                                                c_state  <= #1 ST_STOP;
                                                                core_cmd <= #1 `I2C_CMD_STOP;
 
                                                                // generate command acknowledge signal
                                                                cmd_ack  <= #1 1'b1;
                                                        end
 
                                                ld       <= #1 1'b1;
                                        end
 
                        ST_START:
                                if (core_ack)
                                        begin
                                                if (read)
                                                        begin
                                                                c_state  <= #1 ST_READ;
                                                                core_cmd <= #1 `I2C_CMD_READ;
                                                        end
                                                else
                                                        begin
                                                                c_state  <= #1 ST_WRITE;
                                                                core_cmd <= #1 `I2C_CMD_WRITE;
                                                        end
 
                                                ld       <= #1 1'b1;
                                        end
 
                        ST_WRITE:
                                if (core_ack)
                                        if (cnt_done)
                                                begin
                                                        c_state  <= #1 ST_ACK;
                                                        core_cmd <= #1 `I2C_CMD_READ;
                                                end
                                        else
                                                begin
                                                        c_state  <= #1 ST_WRITE;       // stay in same state
                                                        core_cmd <= #1 `I2C_CMD_WRITE; // write next bit
 
                                                        shift    <= #1 1'b1;
                                                end
 
                        ST_READ:
                                        if (core_ack)
                                                begin
                                                        if (cnt_done)
                                                                begin
                                                                        c_state  <= #1 ST_ACK;
                                                                        core_cmd <= #1 `I2C_CMD_WRITE;
                                                                end
                                                        else
                                                                begin
                                                                        c_state  <= #1 ST_READ;       // stay in same state
                                                                        core_cmd <= #1 `I2C_CMD_READ; // read next bit
                                                                end
 
                                                        shift    <= #1 1'b1;
                                                end
 
                        ST_ACK:
                                if (core_ack)
                                        begin
                                                if (stop)
                                                        begin
                                                                c_state  <= #1 ST_STOP;
                                                                core_cmd <= #1 `I2C_CMD_STOP;
                                                        end
                                                else
                                                        begin
                                                                c_state  <= #1 ST_IDLE;
                                                                core_cmd <= #1 `I2C_CMD_NOP;
                                                        end
 
                                                // assign ack_out output to bit_controller_rxd (contains last received bit)
                                                ack_out = core_rxd;
 
                                                // generate command acknowledge signal
                                                cmd_ack  <= #1 1'b1;
 
                                                core_txd <= #1 1'b1;
                                        end
                                else
                                        core_txd <= #1 ack_in;
 
                        ST_STOP:
                                if (core_ack)
                                        begin
                                                c_state  <= #1 ST_IDLE;
                                                core_cmd <= #1 `I2C_CMD_NOP;
                                        end
 
                endcase
        end
endmodule
 
 

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[/] [i2c/] [trunk/] [rtl/] [verilog/] [i2c_master_byte_ctrl.v] - Blame information for rev 10

Line No.	Rev	Author	Line
1	10	rherveille	`//`
2			`// WISHBONE revB2 compiant I2C master core`
3			`//`
4			`// author: Richard Herveille`
5			`// rev. 0.1 August 24th, 2001. Initial Verilog release.`
6			`//`
7
8			`include "timescale.v"
9			`include "i2c_master_defines.v"
10
11			`module i2c_master_byte_ctrl (`
12			`clk, rst, nReset, ena, clk_cnt, start, stop, read, write, ack_in, din,`
13			`cmd_ack, ack_out, dout, i2c_busy, scl_i, scl_o, scl_oen, sda_i, sda_o, sda_oen );`
14
15			`//`
16			`// inputs & outputs`
17			`//`
18			`input clk; // master clock`
19			`input rst; // synchronous active high reset`
20			`input nReset; // asynchronous active low reset`
21			`input ena; // core enable signal`
22
23			`input [15:0] clk_cnt; // 4x SCL`
24
25			`// control inputs`
26			`input start;`
27			`input stop;`
28			`input read;`
29			`input write;`
30			`input ack_in;`
31			`input [7:0] din;`
32
33			`// status outputs`
34			`output cmd_ack;`
35			`reg cmd_ack;`
36			`output ack_out;`
37			`reg ack_out;`
38			`output i2c_busy;`
39			`output [7:0] dout;`
40
41			`// I2C signals`
42			`input scl_i;`
43			`output scl_o;`
44			`output scl_oen;`
45			`input sda_i;`
46			`output sda_o;`
47			`output sda_oen;`
48
49
50			`//`
51			`// Variable declarations`
52			`//`
53
54			`// statemachine`
55			`parameter [4:0] ST_IDLE = 5'b0_0000;`
56			`parameter [4:0] ST_START = 5'b0_0001;`
57			`parameter [4:0] ST_READ = 5'b0_0010;`
58			`parameter [4:0] ST_WRITE = 5'b0_0100;`
59			`parameter [4:0] ST_ACK = 5'b0_1000;`
60			`parameter [4:0] ST_STOP = 5'b1_0000;`
61
62			`// signals for bit_controller`
63			`reg [3:0] core_cmd;`
64			`reg core_txd;`
65			`wire core_ack, core_rxd;`
66
67			`// signals for shift register`
68			`reg [7:0] sr; //8bit shift register`
69			`reg shift, ld;`
70
71			`// signals for state machine`
72			`wire go;`
73			`reg [3:0] dcnt;`
74			`wire cnt_done;`
75
76			`//`
77			`// Module body`
78			`//`
79
80			`// hookup bit_controller`
81			`i2c_master_bit_ctrl bit_controller (`
82			`.clk(clk),`
83			`.rst(rst),`
84			`.nReset(nReset),`
85			`.ena(ena),`
86			`.clk_cnt(clk_cnt),`
87			`.cmd(core_cmd),`
88			`.cmd_ack(core_ack),`
89			`.busy(i2c_busy),`
90			`.din(core_txd),`
91			`.dout(core_rxd),`
92			`.scl_i(scl_i),`
93			`.scl_o(scl_o),`
94			`.scl_oen(scl_oen),`
95			`.sda_i(sda_i),`
96			`.sda_o(sda_o),`
97			`.sda_oen(sda_oen)`
98			`);`
99
100			`// generate go-signal`
101			`assign go = (read \|\| write \|\| stop) && !cmd_ack;`
102
103			`// assign dout output to shift-register`
104			`assign dout = sr;`
105
106			`// generate shift register`
107			`always@(posedge clk or negedge nReset)`
108			`if (!nReset)`
109			`sr <= #1 8'h0;`
110			`else if (rst)`
111			`sr <= #1 8'h0;`
112			`else if (ld)`
113			`sr <= #1 din;`
114			`else if (shift)`
115			`sr <= #1 {sr[6:0], core_rxd};`
116
117			`// generate counter`
118			`always@(posedge clk or negedge nReset)`
119			`if (!nReset)`
120			`dcnt <= #1 4'h0;`
121			`else if (rst)`
122			`dcnt <= #1 4'h0;`
123			`else if (ld)`
124			`dcnt <= #1 4'h7;`
125			`else if (shift)`
126			`dcnt <= #1 dcnt - 4'h1;`
127
128			`assign cnt_done = !(\|dcnt);`
129
130			`//`
131			`// state machine`
132			`//`
133			`reg [4:0] c_state; // synopsis enum_state`
134
135			`always@(posedge clk or negedge nReset)`
136			`if (!nReset)`
137			`begin`
138			core_cmd <= #1 `I2C_CMD_NOP;
139			`core_txd <= #1 sr[7];`
140
141			`shift <= #1 1'b0;`
142			`ld <= #1 1'b0;`
143
144			`cmd_ack <= #1 1'b0;`
145			`c_state <= #1 ST_IDLE;`
146			`end`
147			`else if (rst)`
148			`begin`
149			core_cmd <= #1 `I2C_CMD_NOP;
150			`core_txd <= #1 1'b0;`
151
152			`shift <= #1 1'b0;`
153			`ld <= #1 1'b0;`
154
155			`cmd_ack <= #1 1'b0;`
156			`c_state <= #1 ST_IDLE;`
157			`end`
158			`else`
159			`begin`
160			`// initially reset all signals`
161			`core_txd <= #1 sr[7];`
162
163			`shift <= #1 1'b0;`
164			`ld <= #1 1'b0;`
165
166			`cmd_ack <= #1 1'b0;`
167
168			`case (c_state) // synopsis full_case parallel_case`
169			`ST_IDLE:`
170			`if (go)`
171			`begin`
172			`if (start)`
173			`begin`
174			`c_state <= #1 ST_START;`
175			core_cmd <= #1 `I2C_CMD_START;
176			`end`
177			`else if (read)`
178			`begin`
179			`c_state <= #1 ST_READ;`
180			core_cmd <= #1 `I2C_CMD_READ;
181			`end`
182			`else if (write)`
183			`begin`
184			`c_state <= #1 ST_WRITE;`
185			core_cmd <= #1 `I2C_CMD_WRITE;
186			`end`
187			`else // stop`
188			`begin`
189			`c_state <= #1 ST_STOP;`
190			core_cmd <= #1 `I2C_CMD_STOP;
191
192			`// generate command acknowledge signal`
193			`cmd_ack <= #1 1'b1;`
194			`end`
195
196			`ld <= #1 1'b1;`
197			`end`
198
199			`ST_START:`
200			`if (core_ack)`
201			`begin`
202			`if (read)`
203			`begin`
204			`c_state <= #1 ST_READ;`
205			core_cmd <= #1 `I2C_CMD_READ;
206			`end`
207			`else`
208			`begin`
209			`c_state <= #1 ST_WRITE;`
210			core_cmd <= #1 `I2C_CMD_WRITE;
211			`end`
212
213			`ld <= #1 1'b1;`
214			`end`
215
216			`ST_WRITE:`
217			`if (core_ack)`
218			`if (cnt_done)`
219			`begin`
220			`c_state <= #1 ST_ACK;`
221			core_cmd <= #1 `I2C_CMD_READ;
222			`end`
223			`else`
224			`begin`
225			`c_state <= #1 ST_WRITE; // stay in same state`
226			core_cmd <= #1 `I2C_CMD_WRITE; // write next bit
227
228			`shift <= #1 1'b1;`
229			`end`
230
231			`ST_READ:`
232			`if (core_ack)`
233			`begin`
234			`if (cnt_done)`
235			`begin`
236			`c_state <= #1 ST_ACK;`
237			core_cmd <= #1 `I2C_CMD_WRITE;
238			`end`
239			`else`
240			`begin`
241			`c_state <= #1 ST_READ; // stay in same state`
242			core_cmd <= #1 `I2C_CMD_READ; // read next bit
243			`end`
244
245			`shift <= #1 1'b1;`
246			`end`
247
248			`ST_ACK:`
249			`if (core_ack)`
250			`begin`
251			`if (stop)`
252			`begin`
253			`c_state <= #1 ST_STOP;`
254			core_cmd <= #1 `I2C_CMD_STOP;
255			`end`
256			`else`
257			`begin`
258			`c_state <= #1 ST_IDLE;`
259			core_cmd <= #1 `I2C_CMD_NOP;
260			`end`
261
262			`// assign ack_out output to bit_controller_rxd (contains last received bit)`
263			`ack_out = core_rxd;`
264
265			`// generate command acknowledge signal`
266			`cmd_ack <= #1 1'b1;`
267
268			`core_txd <= #1 1'b1;`
269			`end`
270			`else`
271			`core_txd <= #1 ack_in;`
272
273			`ST_STOP:`
274			`if (core_ack)`
275			`begin`
276			`c_state <= #1 ST_IDLE;`
277			core_cmd <= #1 `I2C_CMD_NOP;
278			`end`
279
280			`endcase`
281			`end`
282			`endmodule`
283
284