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/////////////////////////////////////////////////////////////////////
////                                                             ////
////  WISHBONE rev.B2 compliant I2C Master byte-controller       ////
////                                                             ////
////                                                             ////
////  Author: Richard Herveille                                  ////
////          richard@asics.ws                                   ////
////          www.asics.ws                                       ////
////                                                             ////
////  Downloaded from: http://www.opencores.org/projects/i2c/    ////
////                                                             ////
/////////////////////////////////////////////////////////////////////
////                                                             ////
//// Copyright (C) 2001 Richard Herveille                        ////
////                    richard@asics.ws                         ////
////                                                             ////
//// This source file may be used and distributed without        ////
//// restriction provided that this copyright statement is not   ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer.////
////                                                             ////
////     THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY     ////
//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED   ////
//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS   ////
//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR      ////
//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,         ////
//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES    ////
//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE   ////
//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR        ////
//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF  ////
//// LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT  ////
//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT  ////
//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE         ////
//// POSSIBILITY OF SUCH DAMAGE.                                 ////
////                                                             ////
/////////////////////////////////////////////////////////////////////
 
//  CVS Log
//
//  $Id: i2c_master_byte_ctrl.v,v 1.7 2004-02-18 11:40:46 rherveille Exp $
//
//  $Date: 2004-02-18 11:40:46 $
//  $Revision: 1.7 $
//  $Author: rherveille $
//  $Locker:  $
//  $State: Exp $
//
// Change History:
//               $Log: not supported by cvs2svn $
//               Revision 1.6  2003/08/09 07:01:33  rherveille
//               Fixed a bug in the Arbitration Lost generation caused by delay on the (external) sda line.
//               Fixed a potential bug in the byte controller's host-acknowledge generation.
//
//               Revision 1.5  2002/12/26 15:02:32  rherveille
//               Core is now a Multimaster I2C controller
//
//               Revision 1.4  2002/11/30 22:24:40  rherveille
//               Cleaned up code
//
//               Revision 1.3  2001/11/05 11:59:25  rherveille
//               Fixed wb_ack_o generation bug.
//               Fixed bug in the byte_controller statemachine.
//               Added headers.
//
 
// synopsys translate_off
`include "timescale.v"
// synopsys translate_on
 
`include "i2c_master_defines.v"
 
module i2c_master_byte_ctrl (
        clk, rst, nReset, ena, clk_cnt, start, stop, read, write, ack_in, din,
        cmd_ack, ack_out, dout, i2c_busy, i2c_al, scl_i, scl_o, scl_oen, sda_i, sda_o, sda_oen );
 
        //
        // inputs & outputs
        //
        input clk;     // master clock
        input rst;     // synchronous active high reset
        input nReset;  // asynchronous active low reset
        input ena;     // core enable signal
 
        input [15:0] clk_cnt; // 4x SCL
 
        // control inputs
        input       start;
        input       stop;
        input       read;
        input       write;
        input       ack_in;
        input [7:0] din;
 
        // status outputs
        output       cmd_ack;
        reg cmd_ack;
        output       ack_out;
        reg ack_out;
        output       i2c_busy;
        output       i2c_al;
        output [7:0] dout;
 
        // I2C signals
        input  scl_i;
        output scl_o;
        output scl_oen;
        input  sda_i;
        output sda_o;
        output sda_oen;
 
 
        //
        // Variable declarations
        //
 
        // statemachine
        parameter [4:0] ST_IDLE  = 5'b0_0000;
        parameter [4:0] ST_START = 5'b0_0001;
        parameter [4:0] ST_READ  = 5'b0_0010;
        parameter [4:0] ST_WRITE = 5'b0_0100;
        parameter [4:0] ST_ACK   = 5'b0_1000;
        parameter [4:0] ST_STOP  = 5'b1_0000;
 
        // signals for bit_controller
        reg  [3:0] core_cmd;
        reg        core_txd;
        wire       core_ack, core_rxd;
 
        // signals for shift register
        reg [7:0] sr; //8bit shift register
        reg       shift, ld;
 
        // signals for state machine
        wire       go;
        reg  [2:0] dcnt;
        wire       cnt_done;
 
        //
        // Module body
        //
 
        // hookup bit_controller
        i2c_master_bit_ctrl bit_controller (
                .clk     ( clk      ),
                .rst     ( rst      ),
                .nReset  ( nReset   ),
                .ena     ( ena      ),
                .clk_cnt ( clk_cnt  ),
                .cmd     ( core_cmd ),
                .cmd_ack ( core_ack ),
                .busy    ( i2c_busy ),
                .al      ( i2c_al   ),
                .din     ( core_txd ),
                .dout    ( core_rxd ),
                .scl_i   ( scl_i    ),
                .scl_o   ( scl_o    ),
                .scl_oen ( scl_oen  ),
                .sda_i   ( sda_i    ),
                .sda_o   ( sda_o    ),
                .sda_oen ( sda_oen  )
        );
 
        // generate go-signal
        assign go = (read | write | stop) & ~cmd_ack;
 
        // assign dout output to shift-register
        assign dout = sr;
 
        // generate shift register
        always @(posedge clk or negedge nReset)
          if (!nReset)
            sr <= #1 8'h0;
          else if (rst)
            sr <= #1 8'h0;
          else if (ld)
            sr <= #1 din;
          else if (shift)
            sr <= #1 {sr[6:0], core_rxd};
 
        // generate counter
        always @(posedge clk or negedge nReset)
          if (!nReset)
            dcnt <= #1 3'h0;
          else if (rst)
            dcnt <= #1 3'h0;
          else if (ld)
            dcnt <= #1 3'h7;
          else if (shift)
            dcnt <= #1 dcnt - 3'h1;
 
        assign cnt_done = ~(|dcnt);
 
        //
        // state machine
        //
        reg [4:0] c_state; // synopsis enum_state
 
        always @(posedge clk or negedge nReset)
          if (!nReset)
            begin
                core_cmd <= #1 `I2C_CMD_NOP;
                core_txd <= #1 1'b0;
                shift    <= #1 1'b0;
                ld       <= #1 1'b0;
                cmd_ack  <= #1 1'b0;
                c_state  <= #1 ST_IDLE;
                ack_out  <= #1 1'b0;
            end
          else if (rst | i2c_al)
           begin
               core_cmd <= #1 `I2C_CMD_NOP;
               core_txd <= #1 1'b0;
               shift    <= #1 1'b0;
               ld       <= #1 1'b0;
               cmd_ack  <= #1 1'b0;
               c_state  <= #1 ST_IDLE;
               ack_out  <= #1 1'b0;
           end
        else
          begin
              // initially reset all signals
              core_txd <= #1 sr[7];
              shift    <= #1 1'b0;
              ld       <= #1 1'b0;
              cmd_ack  <= #1 1'b0;
 
              case (c_state) // synopsys full_case parallel_case
                ST_IDLE:
                  if (go)
                    begin
                        if (start)
                          begin
                              c_state  <= #1 ST_START;
                              core_cmd <= #1 `I2C_CMD_START;
                          end
                        else if (read)
                          begin
                              c_state  <= #1 ST_READ;
                              core_cmd <= #1 `I2C_CMD_READ;
                          end
                        else if (write)
                          begin
                              c_state  <= #1 ST_WRITE;
                              core_cmd <= #1 `I2C_CMD_WRITE;
                          end
                        else // stop
                          begin
                              c_state  <= #1 ST_STOP;
                              core_cmd <= #1 `I2C_CMD_STOP;
                          end
 
                        ld <= #1 1'b1;
                    end
 
                ST_START:
                  if (core_ack)
                    begin
                        if (read)
                          begin
                              c_state  <= #1 ST_READ;
                              core_cmd <= #1 `I2C_CMD_READ;
                          end
                        else
                          begin
                              c_state  <= #1 ST_WRITE;
                              core_cmd <= #1 `I2C_CMD_WRITE;
                          end
 
                        ld <= #1 1'b1;
                    end
 
                ST_WRITE:
                  if (core_ack)
                    if (cnt_done)
                      begin
                          c_state  <= #1 ST_ACK;
                          core_cmd <= #1 `I2C_CMD_READ;
                      end
                    else
                      begin
                          c_state  <= #1 ST_WRITE;       // stay in same state
                          core_cmd <= #1 `I2C_CMD_WRITE; // write next bit
                          shift    <= #1 1'b1;
                      end
 
                ST_READ:
                  if (core_ack)
                    begin
                        if (cnt_done)
                          begin
                              c_state  <= #1 ST_ACK;
                              core_cmd <= #1 `I2C_CMD_WRITE;
                          end
                        else
                          begin
                              c_state  <= #1 ST_READ;       // stay in same state
                              core_cmd <= #1 `I2C_CMD_READ; // read next bit
                          end
 
                        shift    <= #1 1'b1;
                        core_txd <= #1 ack_in;
                    end
 
                ST_ACK:
                  if (core_ack)
                    begin
                       if (stop)
                         begin
                             c_state  <= #1 ST_STOP;
                             core_cmd <= #1 `I2C_CMD_STOP;
                         end
                       else
                         begin
                             c_state  <= #1 ST_IDLE;
                             core_cmd <= #1 `I2C_CMD_NOP;
 
                             // generate command acknowledge signal
                             cmd_ack  <= #1 1'b1;
                         end
 
                         // assign ack_out output to bit_controller_rxd (contains last received bit)
                         ack_out <= #1 core_rxd;
 
                         core_txd <= #1 1'b1;
                     end
                   else
                     core_txd <= #1 ack_in;
 
                ST_STOP:
                  if (core_ack)
                    begin
                        c_state  <= #1 ST_IDLE;
                        core_cmd <= #1 `I2C_CMD_NOP;
 
                        // generate command acknowledge signal
                        cmd_ack  <= #1 1'b1;
                    end
 
              endcase
          end
endmodule

Line No.	Rev	Author	Line
1	14	rherveille	`/////////////////////////////////////////////////////////////////////`
2			`//// ////`
3			`//// WISHBONE rev.B2 compliant I2C Master byte-controller ////`
4			`//// ////`
5			`//// ////`
6			`//// Author: Richard Herveille ////`
7			`//// richard@asics.ws ////`
8			`//// www.asics.ws ////`
9			`//// ////`
10			`//// Downloaded from: http://www.opencores.org/projects/i2c/ ////`
11			`//// ////`
12			`/////////////////////////////////////////////////////////////////////`
13			`//// ////`
14			`//// Copyright (C) 2001 Richard Herveille ////`
15			`//// richard@asics.ws ////`
16			`//// ////`
17			`//// This source file may be used and distributed without ////`
18			`//// restriction provided that this copyright statement is not ////`
19			`//// removed from the file and that any derivative work contains ////`
20			`//// the original copyright notice and the associated disclaimer.////`
21			`//// ////`
22			//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY ////
23			`//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED ////`
24			`//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ////`
25			`//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR ////`
26			`//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ////`
27			`//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ////`
28			`//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE ////`
29			`//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR ////`
30			`//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ////`
31			`//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ////`
32			`//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT ////`
33			`//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ////`
34			`//// POSSIBILITY OF SUCH DAMAGE. ////`
35			`//// ////`
36			`/////////////////////////////////////////////////////////////////////`
37
38			`// CVS Log`
39	10	rherveille	`//`
40	47	rherveille	`// $Id: i2c_master_byte_ctrl.v,v 1.7 2004-02-18 11:40:46 rherveille Exp $`
41	10	rherveille	`//`
42	47	rherveille	`// $Date: 2004-02-18 11:40:46 $`
43			`// $Revision: 1.7 $`
44	14	rherveille	`// $Author: rherveille $`
45			`// $Locker: $`
46			`// $State: Exp $`
47	10	rherveille	`//`
48	14	rherveille	`// Change History:`
49			`// $Log: not supported by cvs2svn $`
50	47	rherveille	`// Revision 1.6 2003/08/09 07:01:33 rherveille`
51			`// Fixed a bug in the Arbitration Lost generation caused by delay on the (external) sda line.`
52			`// Fixed a potential bug in the byte controller's host-acknowledge generation.`
53			`//`
54	38	rherveille	`// Revision 1.5 2002/12/26 15:02:32 rherveille`
55			`// Core is now a Multimaster I2C controller`
56			`//`
57	29	rherveille	`// Revision 1.4 2002/11/30 22:24:40 rherveille`
58			`// Cleaned up code`
59			`//`
60	27	rherveille	`// Revision 1.3 2001/11/05 11:59:25 rherveille`
61			`// Fixed wb_ack_o generation bug.`
62			`// Fixed bug in the byte_controller statemachine.`
63			`// Added headers.`
64			`//`
65	10	rherveille
66	29	rherveille	`// synopsys translate_off`
67	10	rherveille	`include "timescale.v"
68	29	rherveille	`// synopsys translate_on`
69
70	10	rherveille	`include "i2c_master_defines.v"
71
72			`module i2c_master_byte_ctrl (`
73			`clk, rst, nReset, ena, clk_cnt, start, stop, read, write, ack_in, din,`
74	29	rherveille	`cmd_ack, ack_out, dout, i2c_busy, i2c_al, scl_i, scl_o, scl_oen, sda_i, sda_o, sda_oen );`
75	10	rherveille
76			`//`
77			`// inputs & outputs`
78			`//`
79			`input clk; // master clock`
80			`input rst; // synchronous active high reset`
81			`input nReset; // asynchronous active low reset`
82			`input ena; // core enable signal`
83
84			`input [15:0] clk_cnt; // 4x SCL`
85
86			`// control inputs`
87			`input start;`
88			`input stop;`
89			`input read;`
90			`input write;`
91			`input ack_in;`
92			`input [7:0] din;`
93
94			`// status outputs`
95			`output cmd_ack;`
96			`reg cmd_ack;`
97			`output ack_out;`
98			`reg ack_out;`
99			`output i2c_busy;`
100	29	rherveille	`output i2c_al;`
101	10	rherveille	`output [7:0] dout;`
102
103			`// I2C signals`
104			`input scl_i;`
105			`output scl_o;`
106			`output scl_oen;`
107			`input sda_i;`
108			`output sda_o;`
109			`output sda_oen;`
110
111
112			`//`
113			`// Variable declarations`
114			`//`
115
116			`// statemachine`
117			`parameter [4:0] ST_IDLE = 5'b0_0000;`
118			`parameter [4:0] ST_START = 5'b0_0001;`
119			`parameter [4:0] ST_READ = 5'b0_0010;`
120			`parameter [4:0] ST_WRITE = 5'b0_0100;`
121			`parameter [4:0] ST_ACK = 5'b0_1000;`
122			`parameter [4:0] ST_STOP = 5'b1_0000;`
123
124			`// signals for bit_controller`
125			`reg [3:0] core_cmd;`
126			`reg core_txd;`
127			`wire core_ack, core_rxd;`
128
129			`// signals for shift register`
130			`reg [7:0] sr; //8bit shift register`
131			`reg shift, ld;`
132
133			`// signals for state machine`
134			`wire go;`
135	14	rherveille	`reg [2:0] dcnt;`
136	10	rherveille	`wire cnt_done;`
137
138			`//`
139			`// Module body`
140			`//`
141
142			`// hookup bit_controller`
143			`i2c_master_bit_ctrl bit_controller (`
144	27	rherveille	`.clk ( clk ),`
145			`.rst ( rst ),`
146			`.nReset ( nReset ),`
147			`.ena ( ena ),`
148			`.clk_cnt ( clk_cnt ),`
149			`.cmd ( core_cmd ),`
150			`.cmd_ack ( core_ack ),`
151			`.busy ( i2c_busy ),`
152	29	rherveille	`.al ( i2c_al ),`
153	27	rherveille	`.din ( core_txd ),`
154			`.dout ( core_rxd ),`
155			`.scl_i ( scl_i ),`
156			`.scl_o ( scl_o ),`
157			`.scl_oen ( scl_oen ),`
158			`.sda_i ( sda_i ),`
159			`.sda_o ( sda_o ),`
160			`.sda_oen ( sda_oen )`
161	10	rherveille	`);`
162
163			`// generate go-signal`
164	27	rherveille	`assign go = (read \| write \| stop) & ~cmd_ack;`
165	10	rherveille
166			`// assign dout output to shift-register`
167			`assign dout = sr;`
168
169			`// generate shift register`
170	27	rherveille	`always @(posedge clk or negedge nReset)`
171			`if (!nReset)`
172			`sr <= #1 8'h0;`
173			`else if (rst)`
174			`sr <= #1 8'h0;`
175			`else if (ld)`
176			`sr <= #1 din;`
177			`else if (shift)`
178			`sr <= #1 {sr[6:0], core_rxd};`
179	10	rherveille
180			`// generate counter`
181	27	rherveille	`always @(posedge clk or negedge nReset)`
182			`if (!nReset)`
183			`dcnt <= #1 3'h0;`
184			`else if (rst)`
185			`dcnt <= #1 3'h0;`
186			`else if (ld)`
187			`dcnt <= #1 3'h7;`
188			`else if (shift)`
189			`dcnt <= #1 dcnt - 3'h1;`
190	10	rherveille
191	29	rherveille	`assign cnt_done = ~(\|dcnt);`
192	10	rherveille
193			`//`
194			`// state machine`
195			`//`
196			`reg [4:0] c_state; // synopsis enum_state`
197
198	27	rherveille	`always @(posedge clk or negedge nReset)`
199			`if (!nReset)`
200			`begin`
201			core_cmd <= #1 `I2C_CMD_NOP;
202			`core_txd <= #1 1'b0;`
203			`shift <= #1 1'b0;`
204			`ld <= #1 1'b0;`
205			`cmd_ack <= #1 1'b0;`
206			`c_state <= #1 ST_IDLE;`
207			`ack_out <= #1 1'b0;`
208			`end`
209	29	rherveille	`else if (rst \| i2c_al)`
210	27	rherveille	`begin`
211			core_cmd <= #1 `I2C_CMD_NOP;
212			`core_txd <= #1 1'b0;`
213			`shift <= #1 1'b0;`
214			`ld <= #1 1'b0;`
215			`cmd_ack <= #1 1'b0;`
216			`c_state <= #1 ST_IDLE;`
217			`ack_out <= #1 1'b0;`
218			`end`
219	10	rherveille	`else`
220	27	rherveille	`begin`
221			`// initially reset all signals`
222			`core_txd <= #1 sr[7];`
223			`shift <= #1 1'b0;`
224			`ld <= #1 1'b0;`
225			`cmd_ack <= #1 1'b0;`
226	10	rherveille
227	47	rherveille	`case (c_state) // synopsys full_case parallel_case`
228	27	rherveille	`ST_IDLE:`
229			`if (go)`
230			`begin`
231			`if (start)`
232			`begin`
233			`c_state <= #1 ST_START;`
234			core_cmd <= #1 `I2C_CMD_START;
235			`end`
236			`else if (read)`
237			`begin`
238			`c_state <= #1 ST_READ;`
239			core_cmd <= #1 `I2C_CMD_READ;
240			`end`
241			`else if (write)`
242			`begin`
243			`c_state <= #1 ST_WRITE;`
244			core_cmd <= #1 `I2C_CMD_WRITE;
245			`end`
246			`else // stop`
247			`begin`
248			`c_state <= #1 ST_STOP;`
249			core_cmd <= #1 `I2C_CMD_STOP;
250			`end`
251	10	rherveille
252	29	rherveille	`ld <= #1 1'b1;`
253	27	rherveille	`end`
254	10	rherveille
255	27	rherveille	`ST_START:`
256			`if (core_ack)`
257			`begin`
258			`if (read)`
259			`begin`
260			`c_state <= #1 ST_READ;`
261			core_cmd <= #1 `I2C_CMD_READ;
262			`end`
263			`else`
264			`begin`
265			`c_state <= #1 ST_WRITE;`
266			core_cmd <= #1 `I2C_CMD_WRITE;
267			`end`
268	10	rherveille
269	29	rherveille	`ld <= #1 1'b1;`
270	27	rherveille	`end`
271	13	rherveille
272	27	rherveille	`ST_WRITE:`
273			`if (core_ack)`
274			`if (cnt_done)`
275			`begin`
276			`c_state <= #1 ST_ACK;`
277			core_cmd <= #1 `I2C_CMD_READ;
278			`end`
279			`else`
280			`begin`
281			`c_state <= #1 ST_WRITE; // stay in same state`
282			core_cmd <= #1 `I2C_CMD_WRITE; // write next bit
283			`shift <= #1 1'b1;`
284			`end`
285	13	rherveille
286	27	rherveille	`ST_READ:`
287			`if (core_ack)`
288			`begin`
289			`if (cnt_done)`
290			`begin`
291			`c_state <= #1 ST_ACK;`
292			core_cmd <= #1 `I2C_CMD_WRITE;
293			`end`
294			`else`
295			`begin`
296			`c_state <= #1 ST_READ; // stay in same state`
297			core_cmd <= #1 `I2C_CMD_READ; // read next bit
298			`end`
299	13	rherveille
300	27	rherveille	`shift <= #1 1'b1;`
301			`core_txd <= #1 ack_in;`
302			`end`
303	10	rherveille
304	27	rherveille	`ST_ACK:`
305			`if (core_ack)`
306			`begin`
307			`if (stop)`
308			`begin`
309			`c_state <= #1 ST_STOP;`
310			core_cmd <= #1 `I2C_CMD_STOP;
311			`end`
312			`else`
313			`begin`
314			`c_state <= #1 ST_IDLE;`
315			core_cmd <= #1 `I2C_CMD_NOP;
316	38	rherveille
317			`// generate command acknowledge signal`
318			`cmd_ack <= #1 1'b1;`
319	27	rherveille	`end`
320	10	rherveille
321	27	rherveille	`// assign ack_out output to bit_controller_rxd (contains last received bit)`
322			`ack_out <= #1 core_rxd;`
323	10	rherveille
324	27	rherveille	`core_txd <= #1 1'b1;`
325			`end`
326			`else`
327			`core_txd <= #1 ack_in;`
328	10	rherveille
329	27	rherveille	`ST_STOP:`
330			`if (core_ack)`
331			`begin`
332			`c_state <= #1 ST_IDLE;`
333			core_cmd <= #1 `I2C_CMD_NOP;
334	38	rherveille
335			`// generate command acknowledge signal`
336			`cmd_ack <= #1 1'b1;`
337	27	rherveille	`end`
338	10	rherveille
339	27	rherveille	`endcase`
340			`end`
341	10	rherveille	`endmodule`

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[/] [i2c/] [trunk/] [rtl/] [verilog/] [i2c_master_byte_ctrl.v] - Blame information for rev 47