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---------------------------------------------------------------------
----                                                             ----
----  WISHBONE revB2 I2C Master Core; bit-controller             ----
----                                                             ----
----                                                             ----
----  Author: Richard Herveille                                  ----
----          richard@asics.ws                                   ----
----          www.asics.ws                                       ----
----                                                             ----
----  Downloaded from: http://www.opencores.org/projects/i2c/    ----
----                                                             ----
---------------------------------------------------------------------
----                                                             ----
---- Copyright (C) 2000 Richard Herveille                        ----
----                    richard@asics.ws                         ----
----                                                             ----
---- This source file may be used and distributed without        ----
---- restriction provided that this copyright statement is not   ----
---- removed from the file and that any derivative work contains ----
---- the original copyright notice and the associated disclaimer.----
----                                                             ----
----     THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY     ----
---- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED   ----
---- TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS   ----
---- FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR      ----
---- OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,         ----
---- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES    ----
---- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE   ----
---- GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR        ----
---- BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF  ----
---- LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT  ----
---- (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT  ----
---- OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE         ----
---- POSSIBILITY OF SUCH DAMAGE.                                 ----
----                                                             ----
---------------------------------------------------------------------
 
--  CVS Log
--
--  $Id: i2c_master_bit_ctrl.vhd,v 1.17 2009-02-04 20:17:34 rherveille Exp $
--
--  $Date: 2009-02-04 20:17:34 $
--  $Revision: 1.17 $
--  $Author: rherveille $
--  $Locker:  $
--  $State: Exp $
--
-- Change History:
--               $Log: not supported by cvs2svn $
--               Revision 1.16  2009/01/20 20:40:36  rherveille
--               Fixed type iscl_oen instead of scl_oen
--
--               Revision 1.15  2009/01/20 10:34:51  rherveille
--               Added SCL clock synchronization logic
--               Fixed slave_wait signal generation
--
--               Revision 1.14  2006/10/11 12:10:13  rherveille
--               Added missing semicolons ';' on endif
--
--               Revision 1.13  2006/10/06 10:48:24  rherveille
--               fixed short scl high pulse after clock stretch
--
--               Revision 1.12  2004/05/07 11:53:31  rherveille
--               Fixed previous fix :) Made a variable vs signal mistake.
--
--               Revision 1.11  2004/05/07 11:04:00  rherveille
--               Fixed a bug where the core would signal an arbitration lost (AL bit set), when another master controls the bus and the other master generates a STOP bit.
--
--               Revision 1.10  2004/02/27 07:49:43  rherveille
--               Fixed a bug in the arbitration-lost signal generation. VHDL version only.
--
--               Revision 1.9  2003/08/12 14:48:37  rherveille
--               Forgot an 'end if' :-/
--
--               Revision 1.8  2003/08/09 07:01:13  rherveille
--               Fixed a bug in the Arbitration Lost generation caused by delay on the (external) sda line.
--               Fixed a potential bug in the byte controller's host-acknowledge generation.
--
--               Revision 1.7  2003/02/05 00:06:02  rherveille
--               Fixed a bug where the core would trigger an erroneous 'arbitration lost' interrupt after being reset, when the reset pulse width < 3 clk cycles.
--
--               Revision 1.6  2003/02/01 02:03:06  rherveille
--               Fixed a few 'arbitration lost' bugs. VHDL version only.
--
--               Revision 1.5  2002/12/26 16:05:47  rherveille
--               Core is now a Multimaster I2C controller.
--
--               Revision 1.4  2002/11/30 22:24:37  rherveille
--               Cleaned up code
--
--               Revision 1.3  2002/10/30 18:09:53  rherveille
--               Fixed some reported minor start/stop generation timing issuess.
--
--               Revision 1.2  2002/06/15 07:37:04  rherveille
--               Fixed a small timing bug in the bit controller.\nAdded verilog simulation environment.
--
--               Revision 1.1  2001/11/05 12:02:33  rherveille
--               Split i2c_master_core.vhd into separate files for each entity; same layout as verilog version.
--               Code updated, is now up-to-date to doc. rev.0.4.
--               Added headers.
--
 
 
--
-------------------------------------
-- Bit controller section
------------------------------------
--
-- Translate simple commands into SCL/SDA transitions
-- Each command has 5 states, A/B/C/D/idle
--
-- start:    SCL  ~~~~~~~~~~~~~~\____
--           SDA  XX/~~~~~~~\______
--                x | A | B | C | D | i
--
-- repstart  SCL  ______/~~~~~~~\___
--           SDA  __/~~~~~~~\______
--                x | A | B | C | D | i
--
-- stop      SCL  _______/~~~~~~~~~~~
--           SDA  ==\___________/~~~~~
--                x | A | B | C | D | i
--
--- write    SCL  ______/~~~~~~~\____
--           SDA  XXX===============XX
--                x | A | B | C | D | i
--
--- read     SCL  ______/~~~~~~~\____
--           SDA  XXXXXXX=XXXXXXXXXXX
--                x | A | B | C | D | i
--
 
-- Timing:      Normal mode     Fast mode
-----------------------------------------------------------------
-- Fscl         100KHz          400KHz
-- Th_scl       4.0us           0.6us   High period of SCL
-- Tl_scl       4.7us           1.3us   Low period of SCL
-- Tsu:sta      4.7us           0.6us   setup time for a repeated start condition
-- Tsu:sto      4.0us           0.6us   setup time for a stop conditon
-- Tbuf         4.7us           1.3us   Bus free time between a stop and start condition
--
 
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
 
entity i2c_master_bit_ctrl is
    port (
          clk    : in std_logic;
          rst    : in std_logic;
          nReset : in std_logic;
          ena    : in std_logic;                     -- core enable signal
 
          clk_cnt : in unsigned(15 downto 0);        -- clock prescale value
 
          cmd     : in std_logic_vector(3 downto 0);
          cmd_ack : out std_logic;                   -- command completed
          busy    : out std_logic;                   -- i2c bus busy
          al      : out std_logic;                   -- arbitration lost
 
          din  : in std_logic;
          dout : out std_logic;
 
          -- i2c lines
          scl_i   : in std_logic;                    -- i2c clock line input
          scl_o   : out std_logic;                   -- i2c clock line output
          scl_oen : out std_logic;                   -- i2c clock line output enable, active low
          sda_i   : in std_logic;                    -- i2c data line input
          sda_o   : out std_logic;                   -- i2c data line output
          sda_oen : out std_logic                    -- i2c data line output enable, active low
    );
end entity i2c_master_bit_ctrl;
 
architecture structural of i2c_master_bit_ctrl is
    constant I2C_CMD_NOP    : std_logic_vector(3 downto 0) := "0000";
    constant I2C_CMD_START  : std_logic_vector(3 downto 0) := "0001";
    constant I2C_CMD_STOP   : std_logic_vector(3 downto 0) := "0010";
    constant I2C_CMD_READ   : std_logic_vector(3 downto 0) := "0100";
    constant I2C_CMD_WRITE  : std_logic_vector(3 downto 0) := "1000";
 
    type states is (idle, start_a, start_b, start_c, start_d, start_e,
                    stop_a, stop_b, stop_c, stop_d, rd_a, rd_b, rd_c, rd_d, wr_a, wr_b, wr_c, wr_d);
    signal c_state : states;
 
    signal iscl_oen, isda_oen   : std_logic;             -- internal I2C lines
    signal sda_chk              : std_logic;             -- check SDA status (multi-master arbitration)
    signal dscl_oen             : std_logic;             -- delayed scl_oen signals
    signal sSCL, sSDA           : std_logic;             -- synchronized SCL and SDA inputs
    signal dSCL, dSDA           : std_logic;             -- delayed versions ofsSCL and sSDA
    signal clk_en               : std_logic;             -- statemachine clock enable
    signal scl_sync, slave_wait : std_logic;             -- clock generation signals
    signal ial                  : std_logic;             -- internal arbitration lost signal
    signal cnt                  : unsigned(15 downto 0); -- clock divider counter (synthesis)
 
begin
    -- whenever the slave is not ready it can delay the cycle by pulling SCL low
    -- delay scl_oen
    process (clk, nReset)
    begin
        if (nReset = '0') then
            dscl_oen <= '0';
        elsif (clk'event and clk = '1') then
            dscl_oen <= iscl_oen;
        end if;
    end process;
 
    -- slave_wait is asserted when master wants to drive SCL high, but the slave pulls it low
    -- slave_wait remains asserted until the slave releases SCL
    process (clk, nReset)
    begin
        if (nReset = '0') then
            slave_wait <= '0';
        elsif (clk'event and clk = '1') then
               slave_wait <= (iscl_oen and not dscl_oen and not sSCL) or (slave_wait and not sSCL);
        end if;
    end process;
 
    -- master drives SCL high, but another master pulls it low
    -- master start counting down its low cycle now (clock synchronization)
    scl_sync <= dSCL and not sSCL and iscl_oen;
 
    -- generate clk enable signal
    gen_clken: process(clk, nReset)
    begin
        if (nReset = '0') then
            cnt    <= (others => '0');
            clk_en <= '1';
        elsif (clk'event and clk = '1') then
               if ((rst = '1') or (cnt = 0) or (ena = '0') or (scl_sync = '1')) then
                   cnt    <= clk_cnt;
                   clk_en <= '1';
               elsif (slave_wait = '1') then
                   cnt    <= cnt;
                   clk_en <= '0';
               else
                   cnt    <= cnt -1;
                   clk_en <= '0';
               end if;
        end if;
    end process gen_clken;
 
 
    -- generate bus status controller
    bus_status_ctrl: block
      signal cSCL, cSDA    : std_logic_vector( 1 downto 0); -- capture SDA and SCL
      signal fSCL, fSDA    : std_logic_vector( 2 downto 0); -- filter inputs for SCL and SDA
      signal filter_cnt    : unsigned(13 downto 0);         -- clock divider for filter
      signal sta_condition : std_logic;                     -- start detected
      signal sto_condition : std_logic;                     -- stop detected
      signal cmd_stop      : std_logic;                     -- STOP command
      signal ibusy         : std_logic;                     -- internal busy signal
    begin
        -- capture SCL and SDA
        capture_scl_sda: process(clk, nReset)
        begin
            if (nReset = '0') then
                cSCL <= "00";
                cSDA <= "00";
            elsif (clk'event and clk = '1') then
                if (rst = '1') then
                    cSCL <= "00";
                    cSDA <= "00";
                else
                    cSCL <= (cSCL(0) & scl_i);
                    cSDA <= (cSDA(0) & sda_i);
                end if;
            end if;
        end process capture_scl_sda;
 
        -- filter SCL and SDA; (attempt to) remove glitches
        filter_divider: process(clk, nReset)
        begin
            if (nReset = '0') then
                filter_cnt <= (others => '0');
            elsif (clk'event and clk = '1') then
                if ( (rst = '1') or (ena = '0') ) then
                    filter_cnt <= (others => '0');
                elsif (filter_cnt = 0) then
                    filter_cnt <= clk_cnt(15 downto 2);
                else
                    filter_cnt <= filter_cnt -1;
                end if;
            end if;
        end process filter_divider;
 
        filter_scl_sda: process(clk, nReset)
        begin
            if (nReset = '0') then
                fSCL <= (others => '1');
                fSDA <= (others => '1');
            elsif (clk'event and clk = '1') then
                if (rst = '1') then
                    fSCL <= (others => '1');
                    fSDA <= (others => '1');
                elsif (filter_cnt = 0) then
                    fSCL <= (fSCL(1 downto 0) & cSCL(1));
                    fSDA <= (fSDA(1 downto 0) & cSDA(1));
                end if;
            end if;
        end process filter_scl_sda;
 
       -- generate filtered SCL and SDA signals
       scl_sda: process(clk, nReset)
       begin
           if (nReset = '0') then
               sSCL <= '1';
               sSDA <= '1';
 
               dSCL <= '1';
               dSDA <= '1';
           elsif (clk'event and clk = '1') then
               if (rst = '1') then
                   sSCL <= '1';
                   sSDA <= '1';
 
                   dSCL <= '1';
                   dSDA <= '1';
               else
                  sSCL <= (fSCL(2) and fSCL(1)) or
                          (fSCL(2) and fSCL(0)) or
                          (fSCL(1) and fSCL(0));
                  sSDA <= (fSDA(2) and fSDA(1)) or
                          (fSDA(2) and fSDA(0)) or
                          (fSDA(1) and fSDA(0));
 
                  dSCL <= sSCL;
                  dSDA <= sSDA;
               end if;
           end if;
       end process scl_sda;
 
 
       -- detect start condition => detect falling edge on SDA while SCL is high
       -- detect stop condition  => detect rising edge on SDA while SCL is high
       detect_sta_sto: process(clk, nReset)
       begin
           if (nReset = '0') then
               sta_condition <= '0';
               sto_condition <= '0';
           elsif (clk'event and clk = '1') then
               if (rst = '1') then
                   sta_condition <= '0';
                   sto_condition <= '0';
               else
                   sta_condition <= (not sSDA and dSDA) and sSCL;
                   sto_condition <= (sSDA and not dSDA) and sSCL;
               end if;
           end if;
       end process detect_sta_sto;
 
 
       -- generate i2c-bus busy signal
       gen_busy: process(clk, nReset)
       begin
           if (nReset = '0') then
               ibusy <= '0';
           elsif (clk'event and clk = '1') then
               if (rst = '1') then
                   ibusy <= '0';
               else
                   ibusy <= (sta_condition or ibusy) and not sto_condition;
               end if;
           end if;
       end process gen_busy;
       busy <= ibusy;
 
 
       -- generate arbitration lost signal
       -- aribitration lost when:
       -- 1) master drives SDA high, but the i2c bus is low
       -- 2) stop detected while not requested (detect during 'idle' state)
       gen_al: process(clk, nReset)
       begin
           if (nReset = '0') then
               cmd_stop  <= '0';
               ial       <= '0';
           elsif (clk'event and clk = '1') then
               if (rst = '1') then
                   cmd_stop  <= '0';
                   ial       <= '0';
               else
                   if (clk_en = '1') then
                       if (cmd = I2C_CMD_STOP) then
                           cmd_stop <= '1';
                       else
                           cmd_stop <= '0';
                       end if;
                   end if;
 
                   if (c_state = idle) then
                       ial <= (sda_chk and not sSDA and isda_oen) or (sto_condition and not cmd_stop);
                   else
                       ial <= (sda_chk and not sSDA and isda_oen);
                   end if;
               end if;
          end if;
       end process gen_al;
       al <= ial;
 
 
       -- generate dout signal, store dout on rising edge of SCL
       gen_dout: process(clk, nReset)
       begin
           if (nReset = '0') then
               dout <= '0';
           elsif (clk'event and clk = '1') then
               if (sSCL = '1' and dSCL = '0') then
                   dout <= sSDA;
               end if;
           end if;
       end process gen_dout;
    end block bus_status_ctrl;
 
 
    -- generate statemachine
    nxt_state_decoder : process (clk, nReset)
    begin
        if (nReset = '0') then
            c_state  <= idle;
            cmd_ack  <= '0';
            iscl_oen <= '1';
            isda_oen <= '1';
            sda_chk  <= '0';
        elsif (clk'event and clk = '1') then
               if (rst = '1' or ial = '1') then
                   c_state  <= idle;
                   cmd_ack  <= '0';
                   iscl_oen <= '1';
                   isda_oen <= '1';
                   sda_chk  <= '0';
               else
                   cmd_ack <= '0'; -- default no acknowledge
 
                   if (clk_en = '1') then
                       case (c_state) is
                             -- idle
                             when idle =>
                                 case cmd is
                                     when I2C_CMD_START => c_state <= start_a;
                                     when I2C_CMD_STOP  => c_state <= stop_a;
                                     when I2C_CMD_WRITE => c_state <= wr_a;
                                     when I2C_CMD_READ  => c_state <= rd_a;
                                     when others        => c_state <= idle; -- NOP command
                                 end case;
 
                                 iscl_oen <= iscl_oen; -- keep SCL in same state
                                 isda_oen <= isda_oen; -- keep SDA in same state
                                 sda_chk  <= '0';      -- don't check SDA
 
                             -- start
                             when start_a =>
                                 c_state  <= start_b;
                                 iscl_oen <= iscl_oen; -- keep SCL in same state (for repeated start)
                                 isda_oen <= '1';      -- set SDA high
                                 sda_chk  <= '0';      -- don't check SDA
 
                             when start_b =>
                                 c_state  <= start_c;
                                 iscl_oen <= '1'; -- set SCL high
                                 isda_oen <= '1'; -- keep SDA high
                                 sda_chk  <= '0'; -- don't check SDA
 
                             when start_c =>
                                 c_state  <= start_d;
                                 iscl_oen <= '1'; -- keep SCL high
                                 isda_oen <= '0'; -- set SDA low
                                 sda_chk  <= '0'; -- don't check SDA
 
                             when start_d =>
                                 c_state  <= start_e;
                                 iscl_oen <= '1'; -- keep SCL high
                                 isda_oen <= '0'; -- keep SDA low
                                 sda_chk  <= '0'; -- don't check SDA
 
                             when start_e =>
                                 c_state  <= idle;
                                 cmd_ack  <= '1'; -- command completed
                                 iscl_oen <= '0'; -- set SCL low
                                 isda_oen <= '0'; -- keep SDA low
                                 sda_chk  <= '0'; -- don't check SDA
 
                             -- stop
                            when stop_a =>
                                c_state  <= stop_b;
                                iscl_oen <= '0'; -- keep SCL low
                                isda_oen <= '0'; -- set SDA low
                                sda_chk  <= '0'; -- don't check SDA
 
                            when stop_b =>
                                c_state  <= stop_c;
                                iscl_oen <= '1'; -- set SCL high
                                isda_oen <= '0'; -- keep SDA low
                                sda_chk  <= '0'; -- don't check SDA
 
                            when stop_c =>
                                c_state  <= stop_d;
                                iscl_oen <= '1'; -- keep SCL high
                                isda_oen <= '0'; -- keep SDA low
                                sda_chk  <= '0'; -- don't check SDA
 
                            when stop_d =>
                                c_state  <= idle;
                                cmd_ack  <= '1'; -- command completed
                                iscl_oen <= '1'; -- keep SCL high
                                isda_oen <= '1'; -- set SDA high
                                sda_chk  <= '0'; -- don't check SDA
 
                            -- read
                            when rd_a =>
                                c_state  <= rd_b;
                                iscl_oen <= '0'; -- keep SCL low
                                isda_oen <= '1'; -- tri-state SDA
                                sda_chk  <= '0'; -- don't check SDA
 
                            when rd_b =>
                                c_state  <= rd_c;
                                iscl_oen <= '1'; -- set SCL high
                                isda_oen <= '1'; -- tri-state SDA
                                sda_chk  <= '0'; -- don't check SDA
 
                            when rd_c =>
                                c_state  <= rd_d;
                                iscl_oen <= '1'; -- keep SCL high
                                isda_oen <= '1'; -- tri-state SDA
                                sda_chk  <= '0'; -- don't check SDA
 
                            when rd_d =>
                                c_state  <= idle;
                                cmd_ack  <= '1'; -- command completed
                                iscl_oen <= '0'; -- set SCL low
                                isda_oen <= '1'; -- tri-state SDA
                                sda_chk  <= '0'; -- don't check SDA
 
                            -- write
                            when wr_a =>
                                c_state  <= wr_b;
                                iscl_oen <= '0'; -- keep SCL low
                                isda_oen <= din; -- set SDA
                                sda_chk  <= '0'; -- don't check SDA (SCL low)
 
                            when wr_b =>
                                c_state  <= wr_c;
                                iscl_oen <= '1'; -- set SCL high
                                isda_oen <= din; -- keep SDA
                                sda_chk  <= '0'; -- don't check SDA yet
                                                 -- Allow some more time for SDA and SCL to settle
 
                            when wr_c =>
                                c_state  <= wr_d;
                                iscl_oen <= '1'; -- keep SCL high
                                isda_oen <= din; -- keep SDA
                                sda_chk  <= '1'; -- check SDA
 
                            when wr_d =>
                                c_state  <= idle;
                                cmd_ack  <= '1'; -- command completed
                                iscl_oen <= '0'; -- set SCL low
                                isda_oen <= din; -- keep SDA
                                sda_chk  <= '0'; -- don't check SDA (SCL low)
 
                            when others =>
 
                       end case;
                   end if;
               end if;
        end if;
    end process nxt_state_decoder;
 
 
    -- assign outputs
    scl_o   <= '0';
    scl_oen <= iscl_oen;
    sda_o   <= '0';
    sda_oen <= isda_oen;
end architecture structural;
 

Line No.	Rev	Author	Line
1	15	rherveille	`---------------------------------------------------------------------`
2			`---- ----`
3	27	rherveille	`---- WISHBONE revB2 I2C Master Core; bit-controller ----`
4	15	rherveille	`---- ----`
5			`---- ----`
6			`---- Author: Richard Herveille ----`
7			`---- richard@asics.ws ----`
8			`---- www.asics.ws ----`
9			`---- ----`
10			`---- Downloaded from: http://www.opencores.org/projects/i2c/ ----`
11			`---- ----`
12			`---------------------------------------------------------------------`
13			`---- ----`
14			`---- Copyright (C) 2000 Richard Herveille ----`
15			`---- richard@asics.ws ----`
16			`---- ----`
17			`---- This source file may be used and distributed without ----`
18			`---- restriction provided that this copyright statement is not ----`
19			`---- removed from the file and that any derivative work contains ----`
20			`---- the original copyright notice and the associated disclaimer.----`
21			`---- ----`
22			---- THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY ----
23			`---- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED ----`
24			`---- TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ----`
25			`---- FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR ----`
26			`---- OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ----`
27			`---- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ----`
28			`---- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE ----`
29			`---- GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR ----`
30			`---- BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ----`
31			`---- LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ----`
32			`---- (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT ----`
33			`---- OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ----`
34			`---- POSSIBILITY OF SUCH DAMAGE. ----`
35			`---- ----`
36			`---------------------------------------------------------------------`
37
38			`-- CVS Log`
39			`--`
40	67	rherveille	`-- $Id: i2c_master_bit_ctrl.vhd,v 1.17 2009-02-04 20:17:34 rherveille Exp $`
41	15	rherveille	`--`
42	67	rherveille	`-- $Date: 2009-02-04 20:17:34 $`
43			`-- $Revision: 1.17 $`
44	15	rherveille	`-- $Author: rherveille $`
45			`-- $Locker: $`
46			`-- $State: Exp $`
47			`--`
48			`-- Change History:`
49			`-- $Log: not supported by cvs2svn $`
50	67	rherveille	`-- Revision 1.16 2009/01/20 20:40:36 rherveille`
51			`-- Fixed type iscl_oen instead of scl_oen`
52			`--`
53	66	rherveille	`-- Revision 1.15 2009/01/20 10:34:51 rherveille`
54			`-- Added SCL clock synchronization logic`
55			`-- Fixed slave_wait signal generation`
56			`--`
57	64	rherveille	`-- Revision 1.14 2006/10/11 12:10:13 rherveille`
58			`-- Added missing semicolons ';' on endif`
59			`--`
60	60	rherveille	`-- Revision 1.13 2006/10/06 10:48:24 rherveille`
61			`-- fixed short scl high pulse after clock stretch`
62			`--`
63	59	rherveille	`-- Revision 1.12 2004/05/07 11:53:31 rherveille`
64			`-- Fixed previous fix :) Made a variable vs signal mistake.`
65			`--`
66	53	rherveille	`-- Revision 1.11 2004/05/07 11:04:00 rherveille`
67			`-- Fixed a bug where the core would signal an arbitration lost (AL bit set), when another master controls the bus and the other master generates a STOP bit.`
68			`--`
69	52	rherveille	`-- Revision 1.10 2004/02/27 07:49:43 rherveille`
70			`-- Fixed a bug in the arbitration-lost signal generation. VHDL version only.`
71			`--`
72	48	rherveille	`-- Revision 1.9 2003/08/12 14:48:37 rherveille`
73			`-- Forgot an 'end if' :-/`
74			`--`
75	39	rherveille	`-- Revision 1.8 2003/08/09 07:01:13 rherveille`
76			`-- Fixed a bug in the Arbitration Lost generation caused by delay on the (external) sda line.`
77			`-- Fixed a potential bug in the byte controller's host-acknowledge generation.`
78			`--`
79	38	rherveille	`-- Revision 1.7 2003/02/05 00:06:02 rherveille`
80			`-- Fixed a bug where the core would trigger an erroneous 'arbitration lost' interrupt after being reset, when the reset pulse width < 3 clk cycles.`
81			`--`
82	35	rherveille	`-- Revision 1.6 2003/02/01 02:03:06 rherveille`
83			`-- Fixed a few 'arbitration lost' bugs. VHDL version only.`
84			`--`
85	34	rherveille	`-- Revision 1.5 2002/12/26 16:05:47 rherveille`
86			`-- Core is now a Multimaster I2C controller.`
87			`--`
88	31	rherveille	`-- Revision 1.4 2002/11/30 22:24:37 rherveille`
89			`-- Cleaned up code`
90			`--`
91	27	rherveille	`-- Revision 1.3 2002/10/30 18:09:53 rherveille`
92			`-- Fixed some reported minor start/stop generation timing issuess.`
93			`--`
94	24	rherveille	`-- Revision 1.2 2002/06/15 07:37:04 rherveille`
95			`-- Fixed a small timing bug in the bit controller.\nAdded verilog simulation environment.`
96			`--`
97	22	rherveille	`-- Revision 1.1 2001/11/05 12:02:33 rherveille`
98			`-- Split i2c_master_core.vhd into separate files for each entity; same layout as verilog version.`
99			`-- Code updated, is now up-to-date to doc. rev.0.4.`
100			`-- Added headers.`
101			`--`
102	15	rherveille
103
104			`--`
105			`-------------------------------------`
106			`-- Bit controller section`
107			`------------------------------------`
108			`--`
109			`-- Translate simple commands into SCL/SDA transitions`
110			`-- Each command has 5 states, A/B/C/D/idle`
111			`--`
112	31	rherveille	`-- start: SCL ~~~~~~~~~~~~~~\____`
113	72	rherveille	`-- SDA XX/~~~~~~~\______`
114			`-- x \| A \| B \| C \| D \| i`
115	15	rherveille	`--`
116	31	rherveille	`-- repstart SCL ______/~~~~~~~\___`
117	72	rherveille	`-- SDA __/~~~~~~~\______`
118			`-- x \| A \| B \| C \| D \| i`
119	15	rherveille	`--`
120	31	rherveille	`-- stop SCL _______/~~~~~~~~~~~`
121	72	rherveille	`-- SDA ==\___________/~~~~~`
122			`-- x \| A \| B \| C \| D \| i`
123	15	rherveille	`--`
124	31	rherveille	`--- write SCL ______/~~~~~~~\____`
125	72	rherveille	`-- SDA XXX===============XX`
126			`-- x \| A \| B \| C \| D \| i`
127	15	rherveille	`--`
128	31	rherveille	`--- read SCL ______/~~~~~~~\____`
129	72	rherveille	`-- SDA XXXXXXX=XXXXXXXXXXX`
130			`-- x \| A \| B \| C \| D \| i`
131	15	rherveille	`--`
132
133	24	rherveille	`-- Timing: Normal mode Fast mode`
134	15	rherveille	`-----------------------------------------------------------------`
135	24	rherveille	`-- Fscl 100KHz 400KHz`
136			`-- Th_scl 4.0us 0.6us High period of SCL`
137			`-- Tl_scl 4.7us 1.3us Low period of SCL`
138			`-- Tsu:sta 4.7us 0.6us setup time for a repeated start condition`
139			`-- Tsu:sto 4.0us 0.6us setup time for a stop conditon`
140			`-- Tbuf 4.7us 1.3us Bus free time between a stop and start condition`
141	15	rherveille	`--`
142
143			`library ieee;`
144			`use ieee.std_logic_1164.all;`
145	72	rherveille	`use ieee.numeric_std.all;`
146	15	rherveille
147			`entity i2c_master_bit_ctrl is`
148	72	rherveille	`port (`
149			`clk : in std_logic;`
150			`rst : in std_logic;`
151			`nReset : in std_logic;`
152			`ena : in std_logic; -- core enable signal`
153	15	rherveille
154	72	rherveille	`clk_cnt : in unsigned(15 downto 0); -- clock prescale value`
155	15	rherveille
156	72	rherveille	`cmd : in std_logic_vector(3 downto 0);`
157			`cmd_ack : out std_logic; -- command completed`
158			`busy : out std_logic; -- i2c bus busy`
159			`al : out std_logic; -- arbitration lost`
160	15	rherveille
161	72	rherveille	`din : in std_logic;`
162			`dout : out std_logic;`
163	15	rherveille
164	72	rherveille	`-- i2c lines`
165			`scl_i : in std_logic; -- i2c clock line input`
166			`scl_o : out std_logic; -- i2c clock line output`
167			`scl_oen : out std_logic; -- i2c clock line output enable, active low`
168			`sda_i : in std_logic; -- i2c data line input`
169			`sda_o : out std_logic; -- i2c data line output`
170			`sda_oen : out std_logic -- i2c data line output enable, active low`
171			`);`
172	15	rherveille	`end entity i2c_master_bit_ctrl;`
173
174			`architecture structural of i2c_master_bit_ctrl is`
175	72	rherveille	`constant I2C_CMD_NOP : std_logic_vector(3 downto 0) := "0000";`
176			`constant I2C_CMD_START : std_logic_vector(3 downto 0) := "0001";`
177			`constant I2C_CMD_STOP : std_logic_vector(3 downto 0) := "0010";`
178			`constant I2C_CMD_READ : std_logic_vector(3 downto 0) := "0100";`
179			`constant I2C_CMD_WRITE : std_logic_vector(3 downto 0) := "1000";`
180	15	rherveille
181	72	rherveille	`type states is (idle, start_a, start_b, start_c, start_d, start_e,`
182			`stop_a, stop_b, stop_c, stop_d, rd_a, rd_b, rd_c, rd_d, wr_a, wr_b, wr_c, wr_d);`
183			`signal c_state : states;`
184	15	rherveille
185	72	rherveille	`signal iscl_oen, isda_oen : std_logic; -- internal I2C lines`
186			`signal sda_chk : std_logic; -- check SDA status (multi-master arbitration)`
187			`signal dscl_oen : std_logic; -- delayed scl_oen signals`
188			`signal sSCL, sSDA : std_logic; -- synchronized SCL and SDA inputs`
189			`signal dSCL, dSDA : std_logic; -- delayed versions ofsSCL and sSDA`
190			`signal clk_en : std_logic; -- statemachine clock enable`
191			`signal scl_sync, slave_wait : std_logic; -- clock generation signals`
192			`signal ial : std_logic; -- internal arbitration lost signal`
193			`signal cnt : unsigned(15 downto 0); -- clock divider counter (synthesis)`
194	15	rherveille
195			`begin`
196	72	rherveille	`-- whenever the slave is not ready it can delay the cycle by pulling SCL low`
197			`-- delay scl_oen`
198			`process (clk, nReset)`
199			`begin`
200			`if (nReset = '0') then`
201			`dscl_oen <= '0';`
202			`elsif (clk'event and clk = '1') then`
203			`dscl_oen <= iscl_oen;`
204			`end if;`
205			`end process;`
206	15	rherveille
207	72	rherveille	`-- slave_wait is asserted when master wants to drive SCL high, but the slave pulls it low`
208			`-- slave_wait remains asserted until the slave releases SCL`
209			`process (clk, nReset)`
210			`begin`
211			`if (nReset = '0') then`
212			`slave_wait <= '0';`
213			`elsif (clk'event and clk = '1') then`
214			`slave_wait <= (iscl_oen and not dscl_oen and not sSCL) or (slave_wait and not sSCL);`
215			`end if;`
216			`end process;`
217	64	rherveille
218	72	rherveille	`-- master drives SCL high, but another master pulls it low`
219			`-- master start counting down its low cycle now (clock synchronization)`
220			`scl_sync <= dSCL and not sSCL and iscl_oen;`
221	64	rherveille
222	72	rherveille	`-- generate clk enable signal`
223			`gen_clken: process(clk, nReset)`
224			`begin`
225			`if (nReset = '0') then`
226			`cnt <= (others => '0');`
227			`clk_en <= '1';`
228			`elsif (clk'event and clk = '1') then`
229			`if ((rst = '1') or (cnt = 0) or (ena = '0') or (scl_sync = '1')) then`
230			`cnt <= clk_cnt;`
231			`clk_en <= '1';`
232			`elsif (slave_wait = '1') then`
233			`cnt <= cnt;`
234			`clk_en <= '0';`
235			`else`
236			`cnt <= cnt -1;`
237			`clk_en <= '0';`
238			`end if;`
239			`end if;`
240			`end process gen_clken;`
241	15	rherveille
242
243	72	rherveille	`-- generate bus status controller`
244			`bus_status_ctrl: block`
245			`signal cSCL, cSDA : std_logic_vector( 1 downto 0); -- capture SDA and SCL`
246			`signal fSCL, fSDA : std_logic_vector( 2 downto 0); -- filter inputs for SCL and SDA`
247			`signal filter_cnt : unsigned(13 downto 0); -- clock divider for filter`
248			`signal sta_condition : std_logic; -- start detected`
249			`signal sto_condition : std_logic; -- stop detected`
250			`signal cmd_stop : std_logic; -- STOP command`
251			`signal ibusy : std_logic; -- internal busy signal`
252			`begin`
253			`-- capture SCL and SDA`
254			`capture_scl_sda: process(clk, nReset)`
255			`begin`
256			`if (nReset = '0') then`
257			`cSCL <= "00";`
258			`cSDA <= "00";`
259			`elsif (clk'event and clk = '1') then`
260			`if (rst = '1') then`
261			`cSCL <= "00";`
262			`cSDA <= "00";`
263			`else`
264			`cSCL <= (cSCL(0) & scl_i);`
265			`cSDA <= (cSDA(0) & sda_i);`
266			`end if;`
267			`end if;`
268			`end process capture_scl_sda;`
269	15	rherveille
270	72	rherveille	`-- filter SCL and SDA; (attempt to) remove glitches`
271			`filter_divider: process(clk, nReset)`
272			`begin`
273			`if (nReset = '0') then`
274			`filter_cnt <= (others => '0');`
275			`elsif (clk'event and clk = '1') then`
276	76	rherveille	`if ( (rst = '1') or (ena = '0') ) then`
277			`filter_cnt <= (others => '0');`
278			`elsif (filter_cnt = 0) then`
279	72	rherveille	`filter_cnt <= clk_cnt(15 downto 2);`
280			`else`
281			`filter_cnt <= filter_cnt -1;`
282			`end if;`
283			`end if;`
284			`end process filter_divider;`
285	35	rherveille
286	72	rherveille	`filter_scl_sda: process(clk, nReset)`
287			`begin`
288			`if (nReset = '0') then`
289			`fSCL <= (others => '1');`
290			`fSDA <= (others => '1');`
291			`elsif (clk'event and clk = '1') then`
292			`if (rst = '1') then`
293			`fSCL <= (others => '1');`
294			`fSDA <= (others => '1');`
295			`elsif (filter_cnt = 0) then`
296			`fSCL <= (fSCL(1 downto 0) & cSCL(1));`
297			`fSDA <= (fSDA(1 downto 0) & cSDA(1));`
298			`end if;`
299			`end if;`
300			`end process filter_scl_sda;`
301	35	rherveille
302	72	rherveille	`-- generate filtered SCL and SDA signals`
303			`scl_sda: process(clk, nReset)`
304			`begin`
305			`if (nReset = '0') then`
306			`sSCL <= '1';`
307			`sSDA <= '1';`
308	31	rherveille
309	72	rherveille	`dSCL <= '1';`
310			`dSDA <= '1';`
311			`elsif (clk'event and clk = '1') then`
312			`if (rst = '1') then`
313			`sSCL <= '1';`
314			`sSDA <= '1';`
315	15	rherveille
316	72	rherveille	`dSCL <= '1';`
317			`dSDA <= '1';`
318			`else`
319			`sSCL <= (fSCL(2) and fSCL(1)) or`
320			`(fSCL(2) and fSCL(0)) or`
321			`(fSCL(1) and fSCL(0));`
322			`sSDA <= (fSDA(2) and fSDA(1)) or`
323			`(fSDA(2) and fSDA(0)) or`
324	75	rherveille	`(fSDA(1) and fSDA(0));`
325	15	rherveille
326	72	rherveille	`dSCL <= sSCL;`
327			`dSDA <= sSDA;`
328			`end if;`
329			`end if;`
330			`end process scl_sda;`
331	31	rherveille
332
333	72	rherveille	`-- detect start condition => detect falling edge on SDA while SCL is high`
334			`-- detect stop condition => detect rising edge on SDA while SCL is high`
335			`detect_sta_sto: process(clk, nReset)`
336			`begin`
337			`if (nReset = '0') then`
338			`sta_condition <= '0';`
339			`sto_condition <= '0';`
340			`elsif (clk'event and clk = '1') then`
341			`if (rst = '1') then`
342			`sta_condition <= '0';`
343			`sto_condition <= '0';`
344			`else`
345			`sta_condition <= (not sSDA and dSDA) and sSCL;`
346			`sto_condition <= (sSDA and not dSDA) and sSCL;`
347			`end if;`
348			`end if;`
349			`end process detect_sta_sto;`
350	52	rherveille
351	34	rherveille
352	72	rherveille	`-- generate i2c-bus busy signal`
353			`gen_busy: process(clk, nReset)`
354			`begin`
355			`if (nReset = '0') then`
356			`ibusy <= '0';`
357			`elsif (clk'event and clk = '1') then`
358			`if (rst = '1') then`
359			`ibusy <= '0';`
360			`else`
361			`ibusy <= (sta_condition or ibusy) and not sto_condition;`
362			`end if;`
363			`end if;`
364			`end process gen_busy;`
365			`busy <= ibusy;`
366	15	rherveille
367
368	72	rherveille	`-- generate arbitration lost signal`
369			`-- aribitration lost when:`
370			`-- 1) master drives SDA high, but the i2c bus is low`
371			`-- 2) stop detected while not requested (detect during 'idle' state)`
372			`gen_al: process(clk, nReset)`
373			`begin`
374			`if (nReset = '0') then`
375			`cmd_stop <= '0';`
376			`ial <= '0';`
377			`elsif (clk'event and clk = '1') then`
378			`if (rst = '1') then`
379			`cmd_stop <= '0';`
380			`ial <= '0';`
381			`else`
382			`if (clk_en = '1') then`
383			`if (cmd = I2C_CMD_STOP) then`
384			`cmd_stop <= '1';`
385			`else`
386			`cmd_stop <= '0';`
387			`end if;`
388			`end if;`
389	15	rherveille
390	72	rherveille	`if (c_state = idle) then`
391			`ial <= (sda_chk and not sSDA and isda_oen) or (sto_condition and not cmd_stop);`
392			`else`
393			`ial <= (sda_chk and not sSDA and isda_oen);`
394			`end if;`
395			`end if;`
396			`end if;`
397			`end process gen_al;`
398			`al <= ial;`
399	15	rherveille
400
401	72	rherveille	`-- generate dout signal, store dout on rising edge of SCL`
402			`gen_dout: process(clk, nReset)`
403			`begin`
404			`if (nReset = '0') then`
405			`dout <= '0';`
406			`elsif (clk'event and clk = '1') then`
407			`if (sSCL = '1' and dSCL = '0') then`
408			`dout <= sSDA;`
409			`end if;`
410			`end if;`
411			`end process gen_dout;`
412			`end block bus_status_ctrl;`
413	15	rherveille
414
415	72	rherveille	`-- generate statemachine`
416			`nxt_state_decoder : process (clk, nReset)`
417			`begin`
418			`if (nReset = '0') then`
419			`c_state <= idle;`
420			`cmd_ack <= '0';`
421			`iscl_oen <= '1';`
422			`isda_oen <= '1';`
423			`sda_chk <= '0';`
424			`elsif (clk'event and clk = '1') then`
425			`if (rst = '1' or ial = '1') then`
426			`c_state <= idle;`
427			`cmd_ack <= '0';`
428			`iscl_oen <= '1';`
429			`isda_oen <= '1';`
430			`sda_chk <= '0';`
431			`else`
432			`cmd_ack <= '0'; -- default no acknowledge`
433	15	rherveille
434	72	rherveille	`if (clk_en = '1') then`
435			`case (c_state) is`
436			`-- idle`
437			`when idle =>`
438			`case cmd is`
439			`when I2C_CMD_START => c_state <= start_a;`
440			`when I2C_CMD_STOP => c_state <= stop_a;`
441			`when I2C_CMD_WRITE => c_state <= wr_a;`
442			`when I2C_CMD_READ => c_state <= rd_a;`
443			`when others => c_state <= idle; -- NOP command`
444			`end case;`
445	15	rherveille
446	72	rherveille	`iscl_oen <= iscl_oen; -- keep SCL in same state`
447			`isda_oen <= isda_oen; -- keep SDA in same state`
448			`sda_chk <= '0'; -- don't check SDA`
449	15	rherveille
450	72	rherveille	`-- start`
451			`when start_a =>`
452			`c_state <= start_b;`
453			`iscl_oen <= iscl_oen; -- keep SCL in same state (for repeated start)`
454			`isda_oen <= '1'; -- set SDA high`
455			`sda_chk <= '0'; -- don't check SDA`
456	15	rherveille
457	72	rherveille	`when start_b =>`
458			`c_state <= start_c;`
459			`iscl_oen <= '1'; -- set SCL high`
460			`isda_oen <= '1'; -- keep SDA high`
461			`sda_chk <= '0'; -- don't check SDA`
462	15	rherveille
463	72	rherveille	`when start_c =>`
464			`c_state <= start_d;`
465			`iscl_oen <= '1'; -- keep SCL high`
466			`isda_oen <= '0'; -- set SDA low`
467			`sda_chk <= '0'; -- don't check SDA`
468	15	rherveille
469	72	rherveille	`when start_d =>`
470			`c_state <= start_e;`
471			`iscl_oen <= '1'; -- keep SCL high`
472			`isda_oen <= '0'; -- keep SDA low`
473			`sda_chk <= '0'; -- don't check SDA`
474	15	rherveille
475	72	rherveille	`when start_e =>`
476			`c_state <= idle;`
477			`cmd_ack <= '1'; -- command completed`
478			`iscl_oen <= '0'; -- set SCL low`
479			`isda_oen <= '0'; -- keep SDA low`
480			`sda_chk <= '0'; -- don't check SDA`
481	15	rherveille
482	72	rherveille	`-- stop`
483			`when stop_a =>`
484			`c_state <= stop_b;`
485			`iscl_oen <= '0'; -- keep SCL low`
486			`isda_oen <= '0'; -- set SDA low`
487			`sda_chk <= '0'; -- don't check SDA`
488	15	rherveille
489	72	rherveille	`when stop_b =>`
490			`c_state <= stop_c;`
491			`iscl_oen <= '1'; -- set SCL high`
492			`isda_oen <= '0'; -- keep SDA low`
493			`sda_chk <= '0'; -- don't check SDA`
494	15	rherveille
495	72	rherveille	`when stop_c =>`
496			`c_state <= stop_d;`
497			`iscl_oen <= '1'; -- keep SCL high`
498			`isda_oen <= '0'; -- keep SDA low`
499			`sda_chk <= '0'; -- don't check SDA`
500	15	rherveille

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