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---------------------------------------------------------------------
----                                                             ----
----  WISHBONE revB2 compl. I2C Master Core; top level           ----
----                                                             ----
----                                                             ----
----  Author: Richard Herveille                                  ----
----          richard@asics.ws                                   ----
----          www.asics.ws                                       ----
----                                                             ----
----  Downloaded from: http://www.opencores.org/projects/i2c/    ----
----                                                             ----
---------------------------------------------------------------------
----                                                             ----
---- Copyright (C) 2000 Richard Herveille                        ----
----                    richard@asics.ws                         ----
----                                                             ----
---- This source file may be used and distributed without        ----
---- restriction provided that this copyright statement is not   ----
---- removed from the file and that any derivative work contains ----
---- the original copyright notice and the associated disclaimer.----
----                                                             ----
----     THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY     ----
---- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED   ----
---- TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS   ----
---- FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR      ----
---- OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,         ----
---- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES    ----
---- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE   ----
---- GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR        ----
---- BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF  ----
---- LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT  ----
---- (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT  ----
---- OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE         ----
---- POSSIBILITY OF SUCH DAMAGE.                                 ----
----                                                             ----
---------------------------------------------------------------------
 
--  CVS Log
--
--  $Id: i2c_master_top.vhd,v 1.4 2002-12-26 16:05:47 rherveille Exp $
--
--  $Date: 2002-12-26 16:05:47 $
--  $Revision: 1.4 $
--  $Author: rherveille $
--  $Locker:  $
--  $State: Exp $
--
-- Change History:
--               $Log: not supported by cvs2svn $
--               Revision 1.3  2002/11/30 22:24:37  rherveille
--               Cleaned up code
--
--               Revision 1.2  2001/11/10 10:52:44  rherveille
--               Changed PRER reset value from 0x0000 to 0xffff, conform specs.
--
 
 
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
 
entity i2c_master_top is
        generic(
                ARST_LVL : std_logic := '0'                   -- asynchronous reset level
        );
        port (
                -- wishbone signals
                wb_clk_i  : in  std_logic;                    -- master clock input
                wb_rst_i  : in  std_logic := '0';             -- synchronous active high reset
                arst_i    : in  std_logic := not ARST_LVL;    -- asynchronous reset
                wb_adr_i  : in  unsigned(2 downto 0);         -- lower address bits
                wb_dat_i  : in  std_logic_vector(7 downto 0); -- Databus input
                wb_dat_o  : out std_logic_vector(7 downto 0); -- Databus output
                wb_we_i   : in  std_logic;                    -- Write enable input
                wb_stb_i  : in  std_logic;                    -- Strobe signals / core select signal
                wb_cyc_i  : in  std_logic;                    -- Valid bus cycle input
                wb_ack_o  : out std_logic;                    -- Bus cycle acknowledge output
                wb_inta_o : out std_logic;                    -- interrupt request output signal
 
                -- i2c lines
                scl_pad_i     : in  std_logic;                -- i2c clock line input
                scl_pad_o     : out std_logic;                -- i2c clock line output
                scl_padoen_o  : out std_logic;                -- i2c clock line output enable, active low
                sda_pad_i     : in  std_logic;                -- i2c data line input
                sda_pad_o     : out std_logic;                -- i2c data line output
                sda_padoen_o  : out std_logic                 -- i2c data line output enable, active low
        );
end entity i2c_master_top;
 
architecture structural of i2c_master_top is
        component i2c_master_byte_ctrl is
        port (
                clk    : in std_logic;
                rst    : in std_logic; -- synchronous active high reset (WISHBONE compatible)
                nReset : in std_logic;  -- asynchornous active low reset (FPGA compatible)
                ena    : in std_logic; -- core enable signal
 
                clk_cnt : in unsigned(15 downto 0);      -- 4x SCL
 
                -- input signals
                start,
                stop,
                read,
                write,
                ack_in : std_logic;
                din    : in std_logic_vector(7 downto 0);
 
                -- output signals
                cmd_ack  : out std_logic;
                ack_out  : out std_logic;
                i2c_busy : out std_logic;
                i2c_al   : out std_logic;
                dout     : out std_logic_vector(7 downto 0);
 
                -- i2c lines
                scl_i   : in std_logic;  -- i2c clock line input
                scl_o   : out std_logic; -- i2c clock line output
                scl_oen : out std_logic; -- i2c clock line output enable, active low
                sda_i   : in std_logic;  -- i2c data line input
                sda_o   : out std_logic; -- i2c data line output
                sda_oen : out std_logic  -- i2c data line output enable, active low
        );
        end component i2c_master_byte_ctrl;
 
        -- registers
        signal prer : unsigned(15 downto 0);             -- clock prescale register
        signal ctr  : std_logic_vector(7 downto 0);      -- control register
        signal txr  : std_logic_vector(7 downto 0);      -- transmit register
        signal rxr  : std_logic_vector(7 downto 0);      -- receive register
        signal cr   : std_logic_vector(7 downto 0);      -- command register
        signal sr   : std_logic_vector(7 downto 0);      -- status register
 
        -- internal reset signal
        signal rst_i : std_logic;
 
        -- wishbone write access
        signal wb_wacc : std_logic;
 
        -- internal acknowledge signal
        signal iack_o : std_logic;
 
        -- done signal: command completed, clear command register
        signal done : std_logic;
 
        -- command register signals
        signal sta, sto, rd, wr, ack, iack : std_logic;
 
        signal core_en : std_logic;                      -- core enable signal
        signal ien     : std_logic;                      -- interrupt enable signal
 
        -- status register signals
        signal irxack, rxack : std_logic;                -- received aknowledge from slave
        signal tip           : std_logic;                -- transfer in progress
        signal irq_flag      : std_logic;                -- interrupt pending flag
        signal i2c_busy      : std_logic;                -- i2c bus busy (start signal detected)
        signal i2c_al, al    : std_logic;                -- arbitration lost
 
begin
        -- generate internal reset signal
        rst_i <= arst_i xor ARST_LVL;
 
        -- generate acknowledge output signal
        gen_ack_o : process(wb_clk_i)
        begin
            if (wb_clk_i'event and wb_clk_i = '1') then
              iack_o <= wb_cyc_i and wb_stb_i and not iack_o;         -- because timing is always honored
            end if;
        end process gen_ack_o;
        wb_ack_o <= iack_o;
 
 
        -- generate wishbone write access signal
        wb_wacc <= wb_cyc_i and wb_stb_i and wb_we_i;
 
        -- assign wb_dat_o
        assign_dato : process(wb_clk_i)
        begin
            if (wb_clk_i'event and wb_clk_i = '1') then
              case wb_adr_i is
                when "000"  => wb_dat_o <= std_logic_vector(prer( 7 downto 0));
                when "001"  => wb_dat_o <= std_logic_vector(prer(15 downto 8));
                when "010"  => wb_dat_o <= ctr;
                when "011"  => wb_dat_o <= rxr; -- write is transmit register TxR
                when "100"  => wb_dat_o <= sr;  -- write is command register CR
 
                -- Debugging registers:
                -- These registers are not documented.
                -- Functionality could change in future releases
                when "101"  => wb_dat_o <= txr;
                when "110"  => wb_dat_o <= cr;
                when "111"  => wb_dat_o <= (others => '0');
                when others => wb_dat_o <= (others => 'X');     -- for simulation only
              end case;
            end if;
        end process assign_dato;
 
 
        -- generate registers (CR, SR see below)
        gen_regs: process(rst_i, wb_clk_i)
        begin
            if (rst_i = '0') then
              prer <= (others => '1');
              ctr  <= (others => '0');
              txr  <= (others => '0');
            elsif (wb_clk_i'event and wb_clk_i = '1') then
              if (wb_rst_i = '1') then
                prer <= (others => '1');
                ctr  <= (others => '0');
                txr  <= (others => '0');
              elsif (wb_wacc = '1') then
                case wb_adr_i is
                   when "000" => prer( 7 downto 0) <= unsigned(wb_dat_i);
                   when "001" => prer(15 downto 8) <= unsigned(wb_dat_i);
                   when "010" => ctr               <= wb_dat_i;
                   when "011" => txr               <= wb_dat_i;
 
                   -- illegal cases, for simulation only
                   when others =>
                      report ("Illegal write address, setting all registers to unknown.");
                      prer <= (others => 'X');
                      ctr  <= (others => 'X');
                      txr  <= (others => 'X');
                end case;
              end if;
            end if;
        end process gen_regs;
 
 
        -- generate command register
        gen_cr: process(rst_i, wb_clk_i)
        begin
            if (rst_i = '0') then
              cr <= (others => '0');
            elsif (wb_clk_i'event and wb_clk_i = '1') then
              if (wb_rst_i = '1') then
                cr <= (others => '0');
              elsif (wb_wacc = '1') then
                if ( (core_en = '1') and (wb_adr_i = 4) ) then
                  -- only take new commands when i2c core enabled
                  -- pending commands are finished
                  cr <= wb_dat_i;
                        end if;
              else
                  if (done = '1' or i2c_al = '1') then
                    cr(7 downto 4) <= (others => '0'); -- clear command bits when command done
                                                       -- or arbitration lost
                          end if;
 
                  cr(2 downto 1) <= (others => '0');   -- reserved bits, always '0'
                  cr(0) <= '0';                        -- clear IRQ_ACK bit
              end if;
            end if;
        end process gen_cr;
 
        -- decode command register
        sta  <= cr(7);
        sto  <= cr(6);
        rd   <= cr(5);
        wr   <= cr(4);
        ack  <= cr(3);
        iack <= cr(0);
 
        -- decode control register
        core_en <= ctr(7);
        ien     <= ctr(6);
 
        -- hookup byte controller block
        byte_ctrl: i2c_master_byte_ctrl port map (
                clk      => wb_clk_i,
                rst      => wb_rst_i,
                nReset   => rst_i,
                ena      => core_en,
                clk_cnt  => prer,
                start    => sta,
                stop     => sto,
                read     => rd,
                write    => wr,
                ack_in   => ack,
                i2c_busy => i2c_busy,
                i2c_al   => i2c_al,
                din      => txr,
                cmd_ack  => done,
                ack_out  => irxack,
                dout     => rxr,
                scl_i    => scl_pad_i,
                scl_o    => scl_pad_o,
                scl_oen  => scl_padoen_o,
                sda_i    => sda_pad_i,
                sda_o    => sda_pad_o,
                sda_oen  => sda_padoen_o
        );
 
 
        -- status register block + interrupt request signal
        st_irq_block : block
        begin
            -- generate status register bits
            gen_sr_bits: process (wb_clk_i, rst_i)
            begin
                if (rst_i = '0') then
                  al       <= '0';
                  rxack    <= '0';
                  tip      <= '0';
                  irq_flag <= '0';
                elsif (wb_clk_i'event and wb_clk_i = '1') then
                  if (wb_rst_i = '1') then
                    al       <= '0';
                    rxack    <= '0';
                    tip      <= '0';
                    irq_flag <= '0';
                  else
                    al       <= i2c_al or (al and not sta);
                    rxack    <= irxack;
                    tip      <= (rd or wr);
 
                    -- interrupt request flag is always generated
                    irq_flag <= (done or i2c_al or irq_flag) and not iack;
                  end if;
                end if;
            end process gen_sr_bits;
 
            -- generate interrupt request signals
            gen_irq: process (wb_clk_i, rst_i)
            begin
                if (rst_i = '0') then
                  wb_inta_o <= '0';
                elsif (wb_clk_i'event and wb_clk_i = '1') then
                  if (wb_rst_i = '1') then
                    wb_inta_o <= '0';
                  else
                    -- interrupt signal is only generated when IEN (interrupt enable bit) is set
                    wb_inta_o <= irq_flag and ien;
                  end if;
                end if;
            end process gen_irq;
 
            -- assign status register bits
            sr(7)          <= rxack;
            sr(6)          <= i2c_busy;
            sr(5 downto 2) <= (others => '0'); -- reserved
            sr(1)          <= tip;
            sr(0)          <= irq_flag;
        end block;
 
end architecture structural;

Line No.	Rev	Author	Line
1	15	rherveille	`---------------------------------------------------------------------`
2			`---- ----`
3			`---- WISHBONE revB2 compl. I2C Master Core; top level ----`
4			`---- ----`
5			`---- ----`
6			`---- Author: Richard Herveille ----`
7			`---- richard@asics.ws ----`
8			`---- www.asics.ws ----`
9			`---- ----`
10			`---- Downloaded from: http://www.opencores.org/projects/i2c/ ----`
11			`---- ----`
12			`---------------------------------------------------------------------`
13			`---- ----`
14			`---- Copyright (C) 2000 Richard Herveille ----`
15			`---- richard@asics.ws ----`
16			`---- ----`
17			`---- This source file may be used and distributed without ----`
18			`---- restriction provided that this copyright statement is not ----`
19			`---- removed from the file and that any derivative work contains ----`
20			`---- the original copyright notice and the associated disclaimer.----`
21			`---- ----`
22			---- THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY ----
23			`---- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED ----`
24			`---- TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ----`
25			`---- FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR ----`
26			`---- OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ----`
27			`---- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ----`
28			`---- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE ----`
29			`---- GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR ----`
30			`---- BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ----`
31			`---- LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ----`
32			`---- (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT ----`
33			`---- OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ----`
34			`---- POSSIBILITY OF SUCH DAMAGE. ----`
35			`---- ----`
36			`---------------------------------------------------------------------`
37
38			`-- CVS Log`
39			`--`
40	31	rherveille	`-- $Id: i2c_master_top.vhd,v 1.4 2002-12-26 16:05:47 rherveille Exp $`
41	15	rherveille	`--`
42	31	rherveille	`-- $Date: 2002-12-26 16:05:47 $`
43			`-- $Revision: 1.4 $`
44	15	rherveille	`-- $Author: rherveille $`
45			`-- $Locker: $`
46			`-- $State: Exp $`
47			`--`
48			`-- Change History:`
49			`-- $Log: not supported by cvs2svn $`
50	31	rherveille	`-- Revision 1.3 2002/11/30 22:24:37 rherveille`
51			`-- Cleaned up code`
52			`--`
53	27	rherveille	`-- Revision 1.2 2001/11/10 10:52:44 rherveille`
54			`-- Changed PRER reset value from 0x0000 to 0xffff, conform specs.`
55			`--`
56	15	rherveille
57
58			`library ieee;`
59			`use ieee.std_logic_1164.all;`
60			`use ieee.std_logic_arith.all;`
61
62			`entity i2c_master_top is`
63			`generic(`
64	27	rherveille	`ARST_LVL : std_logic := '0' -- asynchronous reset level`
65	15	rherveille	`);`
66			`port (`
67			`-- wishbone signals`
68	27	rherveille	`wb_clk_i : in std_logic; -- master clock input`
69			`wb_rst_i : in std_logic := '0'; -- synchronous active high reset`
70			`arst_i : in std_logic := not ARST_LVL; -- asynchronous reset`
71			`wb_adr_i : in unsigned(2 downto 0); -- lower address bits`
72			`wb_dat_i : in std_logic_vector(7 downto 0); -- Databus input`
73			`wb_dat_o : out std_logic_vector(7 downto 0); -- Databus output`
74			`wb_we_i : in std_logic; -- Write enable input`
75			`wb_stb_i : in std_logic; -- Strobe signals / core select signal`
76			`wb_cyc_i : in std_logic; -- Valid bus cycle input`
77			`wb_ack_o : out std_logic; -- Bus cycle acknowledge output`
78			`wb_inta_o : out std_logic; -- interrupt request output signal`
79	15	rherveille
80			`-- i2c lines`
81			`scl_pad_i : in std_logic; -- i2c clock line input`
82			`scl_pad_o : out std_logic; -- i2c clock line output`
83			`scl_padoen_o : out std_logic; -- i2c clock line output enable, active low`
84			`sda_pad_i : in std_logic; -- i2c data line input`
85			`sda_pad_o : out std_logic; -- i2c data line output`
86			`sda_padoen_o : out std_logic -- i2c data line output enable, active low`
87			`);`
88			`end entity i2c_master_top;`
89
90			`architecture structural of i2c_master_top is`
91			`component i2c_master_byte_ctrl is`
92	27	rherveille	`port (`
93			`clk : in std_logic;`
94			`rst : in std_logic; -- synchronous active high reset (WISHBONE compatible)`
95			`nReset : in std_logic; -- asynchornous active low reset (FPGA compatible)`
96			`ena : in std_logic; -- core enable signal`
97	15	rherveille
98	27	rherveille	`clk_cnt : in unsigned(15 downto 0); -- 4x SCL`
99	15	rherveille
100	27	rherveille	`-- input signals`
101			`start,`
102			`stop,`
103			`read,`
104			`write,`
105			`ack_in : std_logic;`
106			`din : in std_logic_vector(7 downto 0);`
107	15	rherveille
108	27	rherveille	`-- output signals`
109			`cmd_ack : out std_logic;`
110			`ack_out : out std_logic;`
111			`i2c_busy : out std_logic;`
112	31	rherveille	`i2c_al : out std_logic;`
113	27	rherveille	`dout : out std_logic_vector(7 downto 0);`
114	15	rherveille
115	27	rherveille	`-- i2c lines`
116			`scl_i : in std_logic; -- i2c clock line input`
117			`scl_o : out std_logic; -- i2c clock line output`
118			`scl_oen : out std_logic; -- i2c clock line output enable, active low`
119			`sda_i : in std_logic; -- i2c data line input`
120			`sda_o : out std_logic; -- i2c data line output`
121			`sda_oen : out std_logic -- i2c data line output enable, active low`
122			`);`
123	15	rherveille	`end component i2c_master_byte_ctrl;`
124
125			`-- registers`
126	27	rherveille	`signal prer : unsigned(15 downto 0); -- clock prescale register`
127			`signal ctr : std_logic_vector(7 downto 0); -- control register`
128			`signal txr : std_logic_vector(7 downto 0); -- transmit register`
129			`signal rxr : std_logic_vector(7 downto 0); -- receive register`
130			`signal cr : std_logic_vector(7 downto 0); -- command register`
131			`signal sr : std_logic_vector(7 downto 0); -- status register`
132	15	rherveille
133			`-- internal reset signal`
134			`signal rst_i : std_logic;`
135
136	31	rherveille	`-- wishbone write access`
137			`signal wb_wacc : std_logic;`
138
139	27	rherveille	`-- internal acknowledge signal`
140			`signal iack_o : std_logic;`
141
142	15	rherveille	`-- done signal: command completed, clear command register`
143			`signal done : std_logic;`
144
145			`-- command register signals`
146			`signal sta, sto, rd, wr, ack, iack : std_logic;`
147
148	31	rherveille	`signal core_en : std_logic; -- core enable signal`
149			`signal ien : std_logic; -- interrupt enable signal`
150	15	rherveille
151			`-- status register signals`
152	27	rherveille	`signal irxack, rxack : std_logic; -- received aknowledge from slave`
153	31	rherveille	`signal tip : std_logic; -- transfer in progress`
154			`signal irq_flag : std_logic; -- interrupt pending flag`
155			`signal i2c_busy : std_logic; -- i2c bus busy (start signal detected)`
156			`signal i2c_al, al : std_logic; -- arbitration lost`
157	15	rherveille
158			`begin`
159			`-- generate internal reset signal`
160			`rst_i <= arst_i xor ARST_LVL;`
161
162			`-- generate acknowledge output signal`
163	27	rherveille	`gen_ack_o : process(wb_clk_i)`
164	15	rherveille	`begin`
165	27	rherveille	`if (wb_clk_i'event and wb_clk_i = '1') then`
166			`iack_o <= wb_cyc_i and wb_stb_i and not iack_o; -- because timing is always honored`
167			`end if;`
168			`end process gen_ack_o;`
169			`wb_ack_o <= iack_o;`
170	31	rherveille
171
172			`-- generate wishbone write access signal`
173			`wb_wacc <= wb_cyc_i and wb_stb_i and wb_we_i;`
174	15	rherveille
175	27	rherveille	`-- assign wb_dat_o`
176			`assign_dato : process(wb_clk_i)`
177			`begin`
178			`if (wb_clk_i'event and wb_clk_i = '1') then`
179			`case wb_adr_i is`
180			`when "000" => wb_dat_o <= std_logic_vector(prer( 7 downto 0));`
181			`when "001" => wb_dat_o <= std_logic_vector(prer(15 downto 8));`
182			`when "010" => wb_dat_o <= ctr;`
183			`when "011" => wb_dat_o <= rxr; -- write is transmit register TxR`
184			`when "100" => wb_dat_o <= sr; -- write is command register CR`
185	15	rherveille
186	27	rherveille	`-- Debugging registers:`
187			`-- These registers are not documented.`
188			`-- Functionality could change in future releases`
189			`when "101" => wb_dat_o <= txr;`
190			`when "110" => wb_dat_o <= cr;`
191			`when "111" => wb_dat_o <= (others => '0');`
192			`when others => wb_dat_o <= (others => 'X'); -- for simulation only`
193			`end case;`
194			`end if;`
195	15	rherveille	`end process assign_dato;`
196
197
198	31	rherveille	`-- generate registers (CR, SR see below)`
199			`gen_regs: process(rst_i, wb_clk_i)`
200	15	rherveille	`begin`
201	27	rherveille	`if (rst_i = '0') then`
202			`prer <= (others => '1');`
203			`ctr <= (others => '0');`
204			`txr <= (others => '0');`
205			`elsif (wb_clk_i'event and wb_clk_i = '1') then`
206			`if (wb_rst_i = '1') then`
207			`prer <= (others => '1');`
208			`ctr <= (others => '0');`
209			`txr <= (others => '0');`
210	31	rherveille	`elsif (wb_wacc = '1') then`
211			`case wb_adr_i is`
212			`when "000" => prer( 7 downto 0) <= unsigned(wb_dat_i);`
213			`when "001" => prer(15 downto 8) <= unsigned(wb_dat_i);`
214			`when "010" => ctr <= wb_dat_i;`
215			`when "011" => txr <= wb_dat_i;`
216	15	rherveille
217	31	rherveille	`-- illegal cases, for simulation only`
218			`when others =>`
219			`report ("Illegal write address, setting all registers to unknown.");`
220			`prer <= (others => 'X');`
221			`ctr <= (others => 'X');`
222			`txr <= (others => 'X');`
223			`end case;`
224			`end if;`
225			`end if;`
226			`end process gen_regs;`
227	15	rherveille
228
229	31	rherveille	`-- generate command register`
230			`gen_cr: process(rst_i, wb_clk_i)`
231			`begin`
232			`if (rst_i = '0') then`
233			`cr <= (others => '0');`
234			`elsif (wb_clk_i'event and wb_clk_i = '1') then`
235			`if (wb_rst_i = '1') then`
236			`cr <= (others => '0');`
237			`elsif (wb_wacc = '1') then`
238			`if ( (core_en = '1') and (wb_adr_i = 4) ) then`
239			`-- only take new commands when i2c core enabled`
240			`-- pending commands are finished`
241			`cr <= wb_dat_i;`
242			`end if;`
243			`else`
244			`if (done = '1' or i2c_al = '1') then`
245			`cr(7 downto 4) <= (others => '0'); -- clear command bits when command done`
246			`-- or arbitration lost`
247			`end if;`
248
249			`cr(2 downto 1) <= (others => '0'); -- reserved bits, always '0'`
250			`cr(0) <= '0'; -- clear IRQ_ACK bit`
251	27	rherveille	`end if;`
252			`end if;`
253	31	rherveille	`end process gen_cr;`
254	27	rherveille
255	15	rherveille	`-- decode command register`
256			`sta <= cr(7);`
257			`sto <= cr(6);`
258			`rd <= cr(5);`
259			`wr <= cr(4);`
260			`ack <= cr(3);`
261			`iack <= cr(0);`
262
263			`-- decode control register`
264			`core_en <= ctr(7);`
265			`ien <= ctr(6);`
266
267			`-- hookup byte controller block`
268	31	rherveille	`byte_ctrl: i2c_master_byte_ctrl port map (`
269	15	rherveille	`clk => wb_clk_i,`
270			`rst => wb_rst_i,`
271			`nReset => rst_i,`
272	27	rherveille	`ena => core_en,`
273	15	rherveille	`clk_cnt => prer,`
274			`start => sta,`
275			`stop => sto,`
276			`read => rd,`
277			`write => wr,`
278			`ack_in => ack,`
279			`i2c_busy => i2c_busy,`
280	31	rherveille	`i2c_al => i2c_al,`
281	15	rherveille	`din => txr,`
282			`cmd_ack => done,`
283			`ack_out => irxack,`
284			`dout => rxr,`
285			`scl_i => scl_pad_i,`
286			`scl_o => scl_pad_o,`
287			`scl_oen => scl_padoen_o,`
288			`sda_i => sda_pad_i,`
289			`sda_o => sda_pad_o,`
290			`sda_oen => sda_padoen_o`
291			`);`
292
293
294			`-- status register block + interrupt request signal`
295			`st_irq_block : block`
296			`begin`
297	27	rherveille	`-- generate status register bits`
298			`gen_sr_bits: process (wb_clk_i, rst_i)`
299			`begin`
300			`if (rst_i = '0') then`
301	31	rherveille	`al <= '0';`
302	27	rherveille	`rxack <= '0';`
303			`tip <= '0';`
304			`irq_flag <= '0';`
305			`elsif (wb_clk_i'event and wb_clk_i = '1') then`
306			`if (wb_rst_i = '1') then`
307	31	rherveille	`al <= '0';`
308	27	rherveille	`rxack <= '0';`
309			`tip <= '0';`
310			`irq_flag <= '0';`
311			`else`
312	31	rherveille	`al <= i2c_al or (al and not sta);`
313	27	rherveille	`rxack <= irxack;`
314			`tip <= (rd or wr);`
315	15	rherveille
316	27	rherveille	`-- interrupt request flag is always generated`
317	31	rherveille	`irq_flag <= (done or i2c_al or irq_flag) and not iack;`
318	27	rherveille	`end if;`
319			`end if;`
320			`end process gen_sr_bits;`
321	15	rherveille
322	27	rherveille	`-- generate interrupt request signals`
323			`gen_irq: process (wb_clk_i, rst_i)`
324			`begin`
325			`if (rst_i = '0') then`
326			`wb_inta_o <= '0';`
327			`elsif (wb_clk_i'event and wb_clk_i = '1') then`
328			`if (wb_rst_i = '1') then`
329			`wb_inta_o <= '0';`
330			`else`
331			`-- interrupt signal is only generated when IEN (interrupt enable bit) is set`
332			`wb_inta_o <= irq_flag and ien;`
333			`end if;`
334			`end if;`
335			`end process gen_irq;`
336	15	rherveille
337	27	rherveille	`-- assign status register bits`
338			`sr(7) <= rxack;`
339			`sr(6) <= i2c_busy;`
340			`sr(5 downto 2) <= (others => '0'); -- reserved`
341			`sr(1) <= tip;`
342			`sr(0) <= irq_flag;`
343	15	rherveille	`end block;`
344
345			`end architecture structural;`

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